{
unsigned long flags;
unsigned long mid = MCPCIA_HOSE2MID(hose->index);
- unsigned int stat0, value, temp, cpu;
+ unsigned int stat0, value, cpu;
cpu = smp_processor_id();
stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
*(vuip)MCPCIA_CAP_ERR(mid) = stat0;
mb();
- temp = *(vuip)MCPCIA_CAP_ERR(mid);
+ *(vuip)MCPCIA_CAP_ERR(mid);
DBG_CFG(("conf_read: MCPCIA_CAP_ERR(%d) was 0x%x\n", mid, stat0));
mb();
{
unsigned long flags;
unsigned long mid = MCPCIA_HOSE2MID(hose->index);
- unsigned int stat0, temp, cpu;
+ unsigned int stat0, cpu;
cpu = smp_processor_id();
/* Reset status register to avoid losing errors. */
stat0 = *(vuip)MCPCIA_CAP_ERR(mid);
*(vuip)MCPCIA_CAP_ERR(mid) = stat0; mb();
- temp = *(vuip)MCPCIA_CAP_ERR(mid);
+ *(vuip)MCPCIA_CAP_ERR(mid);
DBG_CFG(("conf_write: MCPCIA CAP_ERR(%d) was 0x%x\n", mid, stat0));
draina();
*((vuip)addr) = value;
mb();
mb(); /* magic */
- temp = *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */
+ *(vuip)MCPCIA_CAP_ERR(mid); /* read to force the write */
mcheck_expected(cpu) = 0;
mb();
void
mcpcia_machine_check(unsigned long vector, unsigned long la_ptr)
{
- struct el_common *mchk_header;
struct el_MCPCIA_uncorrected_frame_mcheck *mchk_logout;
unsigned int cpu = smp_processor_id();
int expected;
- mchk_header = (struct el_common *)la_ptr;
mchk_logout = (struct el_MCPCIA_uncorrected_frame_mcheck *)la_ptr;
expected = mcheck_expected(cpu);
static struct el_subpacket *
el_process_regatta_subpacket(struct el_subpacket *header)
{
- int status;
-
if (header->class != EL_CLASS__REGATTA_FAMILY) {
printk("%s ** Unexpected header CLASS %d TYPE %d, aborting\n",
err_print_prefix,
printk("%s ** Occurred on CPU %d:\n",
err_print_prefix,
(int)header->by_type.regatta_frame.cpuid);
- status = privateer_process_logout_frame((struct el_common *)
+ privateer_process_logout_frame((struct el_common *)
header->by_type.regatta_frame.data_start, 1);
break;
default:
case PCA56_CPU:
case PCA57_CPU:
{
- unsigned long cbox_config, size;
-
if (cpu_type == PCA56_CPU) {
L1I = CSHAPE(16*1024, 6, 1);
L1D = CSHAPE(8*1024, 5, 1);
}
L3 = -1;
+#if 0
+ unsigned long cbox_config, size;
+
cbox_config = *(vulp) phys_to_virt (0xfffff00008UL);
size = 512*1024 * (1 << ((cbox_config >> 12) & 3));
-#if 0
L2 = ((cbox_config >> 31) & 1 ? CSHAPE (size, 6, 1) : -1);
#else
L2 = external_cache_probe(512*1024, 6);
static unsigned long __init SMCConfigState(unsigned long baseAddr)
{
unsigned char devId;
- unsigned char devRev;
unsigned long configPort;
unsigned long indexPort;
devId = inb(dataPort);
if (devId == VALID_DEVICE_ID) {
outb(DEVICE_REV, indexPort);
- devRev = inb(dataPort);
+ /* unsigned char devRev = */ inb(dataPort);
break;
}
else
wildfire_init_irq_per_pca(int qbbno, int pcano)
{
int i, irq_bias;
- unsigned long io_bias;
static struct irqaction isa_enable = {
.handler = no_action,
.name = "isa_enable",
irq_bias = qbbno * (WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA)
+ pcano * WILDFIRE_IRQ_PER_PCA;
+#if 0
+ unsigned long io_bias;
+
/* Only need the following for first PCI bus per PCA. */
io_bias = WILDFIRE_IO(qbbno, pcano<<1) - WILDFIRE_IO_BIAS;
-#if 0
outb(0, DMA1_RESET_REG + io_bias);
outb(0, DMA2_RESET_REG + io_bias);
outb(DMA_MODE_CASCADE, DMA2_MODE_REG + io_bias);