+2007-02-05 Dave Brolley <brolley@redhat.com>
+
+ * Makefile.am: Add support for Toshiba MeP.
+ * configure.in: Likewise
+ * config/tc-mep.c:
+ * config/obj-elf.c: New file.
+ * config/tc-mep.c: New file.
+ * config/tc-mep.h: New file.
+ * testsuite/gas/mep: New testsuite with content.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
+2007-02-05 Dave Brolley <brolley@redhat.com>
+
+ * cgen.c (gas_cgen_install_complex_reloc): Removed.
+ (complex_reloc_installation_howto): Removed.
+
+2007-02-05 Dave Brolley <brolley@redhat.com>
+
+ * Contribute the following changes:
+ 2002-06-06 Graydon Hoare <graydon@redhat.com>
+
+ * symbols.c (use_complex_relocs_for): Tighten up conditions on
+ resolving expression symbols.
+
+ 2002-04-04 DJ Delorie <dj@redhat.com>
+
+ * symbols.c (use_complex_relocs_for): New, to decide
+ when to use complex relocs.
+ (resolve_symbol_value): Use it.
+
+ 2002-03-07 Graydon Hoare <graydon@redhat.com>
+
+ * cgen.c: Minor debugging touchups, warning removal.
+
+ 2002-02-17 Catherine Moore <clm@redhat.com>
+
+ * cgen.c (gas_cgen_md_apply_fix3): Only set signed_p if RELC.
+
+ 2002-01-23 Graydon Hoare <graydon@redhat.com>
+
+ * cgen.c (gas_cgen_parse_operand): Add signed RELC support.
+ (queue_fixup_recursively): Likewise.
+ (make_right_shifted_expr): Likewise.
+ * symbols.c (resolve_symbol_value): Likewise.
+
+ 2002-01-15 Graydon Hoare <graydon@redhat.com>
+
+ * write.h (struct fix): Add msb_field_p to fx_cgen sub-struct.
+ * cgen.c (make_masked_expr): Remove.
+ (gas_cgen_encode_addend): Add oplen, signed_p, trunc_p params.
+ (gas_cgen_md_apply_fix3): Call encode_addend with new args.
+ (queue_fixup_recursively): Change from masked expr to trunc flag.
+ (queue_fixup_recursively): Restore assignment of sub-field value to
+ temporary in fixups array (lost in recent merge).
+
+ 2002-01-01 Graydon Hoare <graydon@redhat.com>
+
+ * cgen.c (make_masked_expr): Add.
+ (queue_fixup_recursively): Call make_masked_expr on non-rightmost
+ fragments of multi-ifield complex relocs.
+ (gas_cgen_parse_operand): Reflect changed meaning of last arg to
+ queue_fixup_recursively.
+
+ 2001-12-18 Graydon Hoare <graydon@redhat.com>
+
+ * cgen.c (weak_operand_overflow_check): Improve accuracy of
+ detecting overflows.
+
+ 2001-12-17 Nick Clifton <nickc@cambridge.redhat.com>
+
+ * cgen.c: Tidy up RELC code after the merge.
+
+ 2001-11-15 graydon hoare <graydon@redhat.com>
+
+ * cgen.c (fixup): Add cgen_maybe_multi_ifield member.
+ (make_right_shifted_expr): New function.
+ (queue_fixup): Change to recursive function that fragments
+ fixups if operand has a multi-ifield.
+ (gas_cgen_parse_operand): Add RELC code to wrap expressions in
+ symbols, call weak_operand_overflow_check, and fragment call
+ queue_fixup with operand fields.
+ (gas_cgen_finish_insn) Modify to manage ifield pointer.
+ (gas_cgen_md_apply_fix3) Modify to get start, length from
+ ifield whenever it is set. Also change condition on which
+ self-describing relocs are encoded.
+ (weak_operand_overflow_check): New function to try to select
+ insns correctly.
+ * cgen.h (GAS_CGEN_MAX_FIXUPS): Bump from 3 up to 32.
+ * write.h (struct fix): Add cgen_maybe_multi_ifield field to
+ fx_cgen substructure
+ * config/tc-mep.c (md_cgen_lookup_reloc): Fall back to
+ BFD_RELOC_RELC when no other reloc types can be found.
+
+ 2001-10-03 graydon hoare <graydon@redhat.com>
+
+ * symbols.c (resolve_symbol_value): Unconditionally encode
+ expression symbols as mangled complex relocation symbols (when
+ compiled with -DOBJ_COMPLEX_RELOC)
+
+ * cgen.c (gas_cgen_encode_addend): New function for relc.
+ (gas_cgen_install_complex_reloc): Likewise.
+ (gas_cgen_md_apply_fix3): Add hook into gas_cgen_encode_addend.
+ (gas_cgen_tc_gen_reloc): Add hook into gas_cgen_install_complex_reloc.
+
+ 2001-06-24 Michael Chastain <chastain@redhat.com>
+
+ * symbols.c (symbol_relc_make_expr): Conform to K & R C.
+
+ 2001-06-20 Frank Ch. Eigler <fche@redhat.com>
+
+ * symbols.c (resolve_symbol_value): Conditionally generate relc
+ symbols from unresolved expressions.
+ (symbol_relc_make_sym,value,expr): New traversal/conversion routines.
+ * symbols.h: Declare them.
+
2007-02-03 DJ Delorie <dj@delorie.com>
* config/tc-m32c.c (m32c_cons_fix_new): New. Added to support 3
m68k \
maxq \
mcore \
+ mep \
mips \
mmix \
mn10200 \
config/tc-m68hc11.c \
config/tc-m68k.c \
config/tc-mcore.c \
+ config/tc-mep.c \
config/tc-mips.c \
config/tc-mmix.c \
config/tc-mn10200.c \
config/tc-m68hc11.h \
config/tc-m68k.h \
config/tc-mcore.h \
+ config/tc-mep.h \
config/tc-mips.h \
config/tc-mmix.h \
config/tc-mn10200.h \
DEPTC_mips_multi = $(DEPTC_mips_coff) $(DEPTC_mips_ecoff) \
$(DEPTC_mips_elf)
DEPTC_cris_multi = $(DEPTC_cris_aout) $(DEPTC_cris_elf)
+DEPTC_mep_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+ $(srcdir)/config/tc-mep.h $(INCDIR)/coff/internal.h \
+ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h dwarf2dbg.h \
+ subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mep-desc.h \
+ $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/mep-opc.h \
+ cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h \
+ $(BFDDIR)/libbfd.h $(INCDIR)/safe-ctype.h
+DEPTC_mep_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h \
+ dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mep-desc.h \
+ $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/mep-opc.h \
+ cgen.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h \
+ $(BFDDIR)/libbfd.h $(INCDIR)/safe-ctype.h
DEPOBJ_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
$(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
DEPOBJ_mips_multi = $(DEPOBJ_mips_coff) $(DEPOBJ_mips_ecoff) \
$(DEPOBJ_mips_elf)
DEPOBJ_cris_multi = $(DEPOBJ_cris_aout) $(DEPOBJ_cris_elf)
+DEPOBJ_mep_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+ $(srcdir)/config/tc-mep.h $(INCDIR)/coff/internal.h \
+ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+ subsegs.h $(INCDIR)/safe-ctype.h
+DEPOBJ_mep_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h \
+ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+ $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h \
+ $(INCDIR)/safe-ctype.h
DEP_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
DEP_alpha_elf = $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
DEP_mips_multi = $(DEP_mips_coff) $(DEP_mips_ecoff) \
$(DEP_mips_elf)
DEP_cris_multi = $(DEP_cris_aout) $(DEP_cris_elf)
+DEP_mep_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mep.h \
+ $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+ $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h
+DEP_mep_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h \
+ $(INCDIR)/safe-ctype.h
BMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING ABOVE.
#MKDEP DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
app.o: app.c
m68k \
maxq \
mcore \
+ mep \
mips \
mmix \
mn10200 \
config/tc-m68hc11.c \
config/tc-m68k.c \
config/tc-mcore.c \
+ config/tc-mep.c \
config/tc-mips.c \
config/tc-mmix.c \
config/tc-mn10200.c \
config/tc-m68hc11.h \
config/tc-m68k.h \
config/tc-mcore.h \
+ config/tc-mep.h \
config/tc-mips.h \
config/tc-mmix.h \
config/tc-mn10200.h \
$(DEPTC_mips_elf)
DEPTC_cris_multi = $(DEPTC_cris_aout) $(DEPTC_cris_elf)
+DEPTC_mep_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+ $(srcdir)/config/tc-mep.h $(INCDIR)/coff/internal.h \
+ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h dwarf2dbg.h \
+ subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mep-desc.h \
+ $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/mep-opc.h \
+ cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h \
+ $(BFDDIR)/libbfd.h $(INCDIR)/safe-ctype.h
+
+DEPTC_mep_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h \
+ dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mep-desc.h \
+ $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/mep-opc.h \
+ cgen.h $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h \
+ $(BFDDIR)/libbfd.h $(INCDIR)/safe-ctype.h
+
DEPOBJ_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h \
$(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
$(DEPOBJ_mips_elf)
DEPOBJ_cris_multi = $(DEPOBJ_cris_aout) $(DEPOBJ_cris_elf)
+DEPOBJ_mep_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+ $(srcdir)/config/tc-mep.h $(INCDIR)/coff/internal.h \
+ $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+ subsegs.h $(INCDIR)/safe-ctype.h
+
+DEPOBJ_mep_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h \
+ $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+ $(INCDIR)/elf/mep.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/aout/aout64.h \
+ $(INCDIR)/safe-ctype.h
+
DEP_alpha_ecoff = $(srcdir)/config/obj-ecoff.h $(srcdir)/config/tc-alpha.h \
ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
$(DEP_mips_elf)
DEP_cris_multi = $(DEP_cris_aout) $(DEP_cris_elf)
+DEP_mep_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mep.h \
+ $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+ $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h
+
+DEP_mep_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+ $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mep.h \
+ $(INCDIR)/safe-ctype.h
+
BMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING ABOVE.
all: config.h
$(MAKE) $(AM_MAKEFLAGS) all-recursive
#include "cgen.h"
#include "dwarf2dbg.h"
+#include "symbols.h"
+#include "struc-symbol.h"
+
+#ifdef OBJ_COMPLEX_RELC
+static expressionS * make_right_shifted_expr
+ (expressionS *, const int, const int);
+
+static unsigned long gas_cgen_encode_addend
+ (const unsigned long, const unsigned long, const unsigned long, \
+ const unsigned long, const unsigned long, const unsigned long, \
+ const unsigned long);
+
+static char * weak_operand_overflow_check
+ (const expressionS *, const CGEN_OPERAND *);
+
+static void queue_fixup_recursively
+ (const int, const int, expressionS *, \
+ const CGEN_MAYBE_MULTI_IFLD *, const int, const int);
+
+static int rightshift = 0;
+#endif
static void queue_fixup (int, int, expressionS *);
/* Opcode table descriptor, must be set by md_begin. */
int opindex;
int opinfo;
expressionS exp;
+ struct cgen_maybe_multi_ifield * field;
+ int msb_field_p;
};
static struct fixup fixups[GAS_CGEN_MAX_FIXUPS];
+ (int) operand->type));
fixP->fx_cgen.insn = insn;
fixP->fx_cgen.opinfo = opinfo;
+ fixP->fx_cgen.field = NULL;
+ fixP->fx_cgen.msb_field_p = 0;
return fixP;
}
+ (int) operand->type));
fixP->fx_cgen.insn = insn;
fixP->fx_cgen.opinfo = opinfo;
+ fixP->fx_cgen.field = NULL;
+ fixP->fx_cgen.msb_field_p = 0;
return fixP;
}
+#ifdef OBJ_COMPLEX_RELC
+static symbolS *
+expr_build_binary (operatorT op, symbolS * s1, symbolS * s2)
+{
+ expressionS e;
+
+ e.X_op = op;
+ e.X_add_symbol = s1;
+ e.X_op_symbol = s2;
+ e.X_add_number = 0;
+ return make_expr_symbol (& e);
+}
+#endif
+
/* Used for communication between the next two procedures. */
static jmp_buf expr_jmp_buf;
static int expr_jmp_buf_p;
const char *
gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
+
+#ifdef OBJ_COMPLEX_RELC
+ CGEN_CPU_DESC cd;
+#else
CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
+#endif
enum cgen_parse_operand_type want;
const char **strP;
int opindex;
const char *errmsg;
expressionS exp;
+#ifdef OBJ_COMPLEX_RELC
+ volatile int signed_p = 0;
+ symbolS * stmp = NULL;
+ bfd_reloc_code_real_type reloc_type;
+ const CGEN_OPERAND * operand;
+ fixS dummy_fixup;
+#endif
if (want == CGEN_PARSE_OPERAND_INIT)
{
gas_cgen_init_parse ();
break;
de_fault:
default:
+#ifdef OBJ_COMPLEX_RELC
+ /* Look up operand, check to see if there's an obvious
+ overflow (this helps disambiguate some insn parses). */
+ operand = cgen_operand_lookup_by_num (cd, opindex);
+ errmsg = weak_operand_overflow_check (& exp, operand);
+
+ if (! errmsg)
+ {
+ /* Fragment the expression as necessary, and queue a reloc. */
+ memset (& dummy_fixup, 0, sizeof (fixS));
+
+ reloc_type = md_cgen_lookup_reloc (0, operand, & dummy_fixup);
+
+ if (exp.X_op == O_symbol
+ && reloc_type == BFD_RELOC_RELC
+ && exp.X_add_symbol->sy_value.X_op == O_constant
+ && exp.X_add_symbol->bsym->section != expr_section
+ && exp.X_add_symbol->bsym->section != absolute_section
+ && exp.X_add_symbol->bsym->section != undefined_section)
+ {
+ /* Local labels will have been (eagerly) turned into constants
+ by now, due to the inappropriately deep insight of the
+ expression parser. Unfortunately make_expr_symbol
+ prematurely dives into the symbol evaluator, and in this
+ case it gets a bad answer, so we manually create the
+ expression symbol we want here. */
+ stmp = symbol_create (FAKE_LABEL_NAME, expr_section, 0,
+ & zero_address_frag);
+ symbol_set_value_expression (stmp, & exp);
+ }
+ else
+ stmp = make_expr_symbol (& exp);
+
+ /* If this is a pc-relative RELC operand, we
+ need to subtract "." from the expression. */
+ if (reloc_type == BFD_RELOC_RELC
+ && CGEN_OPERAND_ATTR_VALUE (operand, CGEN_OPERAND_PCREL_ADDR))
+ stmp = expr_build_binary (O_subtract, stmp, expr_build_dot ());
+
+ /* FIXME: this is not a perfect heuristic for figuring out
+ whether an operand is signed: it only works when the operand
+ is an immediate. it's not terribly likely that any other
+ values will be signed relocs, but it's possible. */
+ if (operand && (operand->hw_type == HW_H_SINT))
+ signed_p = 1;
+
+ if (stmp->bsym && (stmp->bsym->section == expr_section))
+ {
+ if (signed_p)
+ stmp->bsym->flags |= BSF_SRELC;
+ else
+ stmp->bsym->flags |= BSF_RELC;
+ }
+
+ /* Now package it all up for the fixup emitter. */
+ exp.X_op = O_symbol;
+ exp.X_op_symbol = 0;
+ exp.X_add_symbol = stmp;
+ exp.X_add_number = 0;
+
+ /* Re-init rightshift quantity, just in case. */
+ rightshift = operand->length;
+ queue_fixup_recursively (opindex, opinfo_1, & exp,
+ (reloc_type == BFD_RELOC_RELC) ?
+ & (operand->index_fields) : 0,
+ signed_p, -1);
+ }
+ * resultP = errmsg
+ ? CGEN_PARSE_OPERAND_RESULT_ERROR
+ : CGEN_PARSE_OPERAND_RESULT_QUEUED;
+ *valueP = 0;
+#else
queue_fixup (opindex, opinfo_1, &exp);
*valueP = 0;
*resultP = CGEN_PARSE_OPERAND_RESULT_QUEUED;
+#endif
break;
}
insn, length, operand,
fixups[i].opinfo,
&fixups[i].exp);
+ fixP->fx_cgen.field = fixups[i].field;
+ fixP->fx_cgen.msb_field_p = fixups[i].msb_field_p;
if (result)
result->fixups[i] = fixP;
}
}
}
+#ifdef OBJ_COMPLEX_RELC
+/* Queue many fixups, recursively. If the field is a multi-ifield,
+ repeatedly queue its sub-parts, right shifted to fit into the field (we
+ assume here multi-fields represent a left-to-right, MSB0-LSB0
+ reading). */
+
+static void
+queue_fixup_recursively (const int opindex,
+ const int opinfo,
+ expressionS * expP,
+ const CGEN_MAYBE_MULTI_IFLD * field,
+ const int signed_p,
+ const int part_of_multi)
+{
+ if (field && field->count)
+ {
+ int i;
+
+ for (i = 0; i < field->count; ++ i)
+ queue_fixup_recursively (opindex, opinfo, expP,
+ & (field->val.multi[i]), signed_p, i);
+ }
+ else
+ {
+ expressionS * new_exp = expP;
+
+#ifdef DEBUG
+ printf ("queueing fixup for field %s\n",
+ (field ? field->val.leaf->name : "??"));
+ print_symbol_value (expP->X_add_symbol);
+#endif
+ if (field && part_of_multi != -1)
+ {
+ rightshift -= field->val.leaf->length;
+
+ /* Shift reloc value by number of bits remaining after this
+ field. */
+ if (rightshift)
+ new_exp = make_right_shifted_expr (expP, rightshift, signed_p);
+ }
+
+ /* Truncate reloc values to length, *after* leftmost one. */
+ fixups[num_fixups].msb_field_p = (part_of_multi <= 0);
+ fixups[num_fixups].field = (CGEN_MAYBE_MULTI_IFLD *) field;
+
+ queue_fixup (opindex, opinfo, new_exp);
+ }
+}
+
+/* Encode the self-describing RELC reloc format's addend. */
+
+static unsigned long
+gas_cgen_encode_addend (const unsigned long start, /* in bits */
+ const unsigned long len, /* in bits */
+ const unsigned long oplen, /* in bits */
+ const unsigned long wordsz, /* in bytes */
+ const unsigned long chunksz, /* in bytes */
+ const unsigned long signed_p,
+ const unsigned long trunc_p)
+{
+ unsigned long res = 0L;
+
+ res |= start & 0x3F;
+ res |= (oplen & 0x3F) << 6;
+ res |= (len & 0x3F) << 12;
+ res |= (wordsz & 0xF) << 18;
+ res |= (chunksz & 0xF) << 22;
+ res |= (CGEN_INSN_LSB0_P ? 1 : 0) << 27;
+ res |= signed_p << 28;
+ res |= trunc_p << 29;
+
+ return res;
+}
+
+/* Purpose: make a weak check that the expression doesn't overflow the
+ operand it's to be inserted into.
+
+ Rationale: some insns used to use %operators to disambiguate during a
+ parse. when these %operators are translated to expressions by the macro
+ expander, the ambiguity returns. we attempt to disambiguate by field
+ size.
+
+ Method: check to see if the expression's top node is an O_and operator,
+ and the mask is larger than the operand length. This would be an
+ overflow, so signal it by returning an error string. Any other case is
+ ambiguous, so we assume it's OK and return NULL. */
+
+static char *
+weak_operand_overflow_check (const expressionS * exp,
+ const CGEN_OPERAND * operand)
+{
+ const unsigned long len = operand->length;
+ unsigned long mask;
+ unsigned long opmask = (((1L << (len - 1)) - 1) << 1) | 1;
+
+ if (!exp)
+ return NULL;
+
+ if (exp->X_op != O_bit_and)
+ {
+ /* Check for implicit overflow flag. */
+ if (CGEN_OPERAND_ATTR_VALUE
+ (operand, CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW))
+ return _("a reloc on this operand implies an overflow");
+ return NULL;
+ }
+
+ mask = exp->X_add_number;
+
+ if (exp->X_add_symbol &&
+ exp->X_add_symbol->sy_value.X_op == O_constant)
+ mask |= exp->X_add_symbol->sy_value.X_add_number;
+
+ if (exp->X_op_symbol &&
+ exp->X_op_symbol->sy_value.X_op == O_constant)
+ mask |= exp->X_op_symbol->sy_value.X_add_number;
+
+ /* Want to know if mask covers more bits than opmask.
+ this is the same as asking if mask has any bits not in opmask,
+ or whether (mask & ~opmask) is nonzero. */
+ if (mask && (mask & ~opmask))
+ {
+#ifdef DEBUG
+ printf ("overflow: (mask = %8.8x, ~opmask = %8.8x, AND = %8.8x)\n",
+ mask, ~opmask, (mask & ~opmask));
+#endif
+ return _("operand mask overflow");
+ }
+
+ return NULL;
+}
+
+
+static expressionS *
+make_right_shifted_expr (expressionS * exp,
+ const int amount,
+ const int signed_p)
+{
+ symbolS * stmp = 0;
+ expressionS * new_exp;
+
+ stmp = expr_build_binary (O_right_shift,
+ make_expr_symbol (exp),
+ expr_build_uconstant (amount));
+
+ if (signed_p)
+ stmp->bsym->flags |= BSF_SRELC;
+ else
+ stmp->bsym->flags |= BSF_RELC;
+
+ /* Then wrap that in a "symbol expr" for good measure. */
+ new_exp = xmalloc (sizeof (expressionS));
+ memset (new_exp, 0, sizeof (expressionS));
+ new_exp->X_op = O_symbol;
+ new_exp->X_op_symbol = 0;
+ new_exp->X_add_symbol = stmp;
+ new_exp->X_add_number = 0;
+
+ return new_exp;
+}
+#endif
/* Apply a fixup to the object code. This is called for all the
fixups we generated by the call to fix_new_exp, above. In the call
above we used a reloc code which was the largest legal reloc code
bfd_reloc_code_real_type reloc_type;
CGEN_FIELDS *fields = alloca (CGEN_CPU_SIZEOF_FIELDS (cd));
const CGEN_INSN *insn = fixP->fx_cgen.insn;
+ int start;
+ int length;
+ int signed_p = 0;
+
+ if (fixP->fx_cgen.field)
+ {
+ /* Use the twisty little pointer path
+ back to the ifield if it exists. */
+ start = fixP->fx_cgen.field->val.leaf->start;
+ length = fixP->fx_cgen.field->val.leaf->length;
+ }
+ else
+ {
+ /* Or the far less useful operand-size guesstimate. */
+ start = operand->start;
+ length = operand->length;
+ }
+
+ /* FIXME: this is not a perfect heuristic for figuring out
+ whether an operand is signed: it only works when the operand
+ is an immediate. it's not terribly likely that any other
+ values will be signed relocs, but it's possible. */
+ if (operand && (operand->hw_type == HW_H_SINT))
+ signed_p = 1;
/* If the reloc has been fully resolved finish the operand here. */
/* FIXME: This duplicates the capabilities of code in BFD. */
partial_inplace == false. */
reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+#ifdef OBJ_COMPLEX_RELC
+ if (reloc_type == BFD_RELOC_RELC)
+ {
+ /* Change addend to "self-describing" form,
+ for BFD to handle in the linker. */
+ value = gas_cgen_encode_addend (start, operand->length,
+ length, fixP->fx_size,
+ cd->insn_chunk_bitsize / 8,
+ signed_p,
+ ! (fixP->fx_cgen.msb_field_p));
+ }
+#endif
if (reloc_type != BFD_RELOC_NONE)
fixP->fx_r_type = reloc_type;
fixS * fixP;
{
arelent *reloc;
-
reloc = (arelent *) xmalloc (sizeof (arelent));
reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
else
cgen_clear_signed_overflow_ok (gas_cgen_cpu_desc);
}
+
#include "elf/x86-64.h"
#endif
+#ifdef TC_MEP
+#include "elf/mep.h"
+#endif
+
static void obj_elf_line (int);
static void obj_elf_size (int);
static void obj_elf_type (int);
--- /dev/null
+/* tc-mep.c -- Assembler for the Toshiba Media Processor.
+ Copyright (C) 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#include <stdio.h>
+#include "as.h"
+#include "dwarf2dbg.h"
+#include "subsegs.h"
+#include "symcat.h"
+#include "opcodes/mep-desc.h"
+#include "opcodes/mep-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/mep.h"
+#include "libbfd.h"
+#include "xregex.h"
+
+/* Structure to hold all of the different components describing
+ an individual instruction. */
+typedef struct
+{
+ const CGEN_INSN * insn;
+ const CGEN_INSN * orig_insn;
+ CGEN_FIELDS fields;
+#if CGEN_INT_INSN_P
+ CGEN_INSN_INT buffer [1];
+#define INSN_VALUE(buf) (*(buf))
+#else
+ unsigned char buffer [CGEN_MAX_INSN_SIZE];
+#define INSN_VALUE(buf) (buf)
+#endif
+ char * addr;
+ fragS * frag;
+ int num_fixups;
+ fixS * fixups [GAS_CGEN_MAX_FIXUPS];
+ int indices [MAX_OPERAND_INSTANCES];
+} mep_insn;
+
+static int mode = CORE; /* Start in core mode. */
+static int pluspresent = 0;
+static int allow_disabled_registers = 0;
+static int library_flag = 0;
+
+/* We're going to need to store all of the instructions along with
+ their fixups so that we can parallelization grouping rules. */
+
+static mep_insn saved_insns[MAX_SAVED_FIXUP_CHAINS];
+static int num_insns_saved = 0;
+
+const char comment_chars[] = "#";
+const char line_comment_chars[] = ";#";
+const char line_separator_chars[] = ";";
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "dD";
+
+static void mep_switch_to_vliw_mode (int);
+static void mep_switch_to_core_mode (int);
+static void mep_s_vtext (int);
+static void mep_noregerr (int);
+
+/* The target specific pseudo-ops which we support. */
+const pseudo_typeS md_pseudo_table[] =
+{
+ { "word", cons, 4 },
+ { "file", (void (*) (int)) dwarf2_directive_file, 0 },
+ { "loc", dwarf2_directive_loc, 0 },
+ { "vliw", mep_switch_to_vliw_mode, 0 },
+ { "core", mep_switch_to_core_mode, 0 },
+ { "vtext", mep_s_vtext, 0 },
+ { "noregerr", mep_noregerr, 0 },
+ { NULL, NULL, 0 }
+};
+
+/* Relocations against symbols are done in two
+ parts, with a HI relocation and a LO relocation. Each relocation
+ has only 16 bits of space to store an addend. This means that in
+ order for the linker to handle carries correctly, it must be able
+ to locate both the HI and the LO relocation. This means that the
+ relocations must appear in order in the relocation table.
+
+ In order to implement this, we keep track of each unmatched HI
+ relocation. We then sort them so that they immediately precede the
+ corresponding LO relocation. */
+
+struct mep_hi_fixup
+{
+ struct mep_hi_fixup * next; /* Next HI fixup. */
+ fixS * fixp; /* This fixup. */
+ segT seg; /* The section this fixup is in. */
+};
+
+/* The list of unmatched HI relocs. */
+static struct mep_hi_fixup * mep_hi_fixup_list;
+
+\f
+#define OPTION_EB (OPTION_MD_BASE + 0)
+#define OPTION_EL (OPTION_MD_BASE + 1)
+#define OPTION_CONFIG (OPTION_MD_BASE + 2)
+#define OPTION_AVERAGE (OPTION_MD_BASE + 3)
+#define OPTION_NOAVERAGE (OPTION_MD_BASE + 4)
+#define OPTION_MULT (OPTION_MD_BASE + 5)
+#define OPTION_NOMULT (OPTION_MD_BASE + 6)
+#define OPTION_DIV (OPTION_MD_BASE + 7)
+#define OPTION_NODIV (OPTION_MD_BASE + 8)
+#define OPTION_BITOPS (OPTION_MD_BASE + 9)
+#define OPTION_NOBITOPS (OPTION_MD_BASE + 10)
+#define OPTION_LEADZ (OPTION_MD_BASE + 11)
+#define OPTION_NOLEADZ (OPTION_MD_BASE + 12)
+#define OPTION_ABSDIFF (OPTION_MD_BASE + 13)
+#define OPTION_NOABSDIFF (OPTION_MD_BASE + 14)
+#define OPTION_MINMAX (OPTION_MD_BASE + 15)
+#define OPTION_NOMINMAX (OPTION_MD_BASE + 16)
+#define OPTION_CLIP (OPTION_MD_BASE + 17)
+#define OPTION_NOCLIP (OPTION_MD_BASE + 18)
+#define OPTION_SATUR (OPTION_MD_BASE + 19)
+#define OPTION_NOSATUR (OPTION_MD_BASE + 20)
+#define OPTION_COP32 (OPTION_MD_BASE + 21)
+#define OPTION_REPEAT (OPTION_MD_BASE + 25)
+#define OPTION_NOREPEAT (OPTION_MD_BASE + 26)
+#define OPTION_DEBUG (OPTION_MD_BASE + 27)
+#define OPTION_NODEBUG (OPTION_MD_BASE + 28)
+#define OPTION_LIBRARY (OPTION_MD_BASE + 29)
+
+struct option md_longopts[] = {
+ { "EB", no_argument, NULL, OPTION_EB},
+ { "EL", no_argument, NULL, OPTION_EL},
+ { "mconfig", required_argument, NULL, OPTION_CONFIG},
+ { "maverage", no_argument, NULL, OPTION_AVERAGE},
+ { "mno-average", no_argument, NULL, OPTION_NOAVERAGE},
+ { "mmult", no_argument, NULL, OPTION_MULT},
+ { "mno-mult", no_argument, NULL, OPTION_NOMULT},
+ { "mdiv", no_argument, NULL, OPTION_DIV},
+ { "mno-div", no_argument, NULL, OPTION_NODIV},
+ { "mbitops", no_argument, NULL, OPTION_BITOPS},
+ { "mno-bitops", no_argument, NULL, OPTION_NOBITOPS},
+ { "mleadz", no_argument, NULL, OPTION_LEADZ},
+ { "mno-leadz", no_argument, NULL, OPTION_NOLEADZ},
+ { "mabsdiff", no_argument, NULL, OPTION_ABSDIFF},
+ { "mno-absdiff", no_argument, NULL, OPTION_NOABSDIFF},
+ { "mminmax", no_argument, NULL, OPTION_MINMAX},
+ { "mno-minmax", no_argument, NULL, OPTION_NOMINMAX},
+ { "mclip", no_argument, NULL, OPTION_CLIP},
+ { "mno-clip", no_argument, NULL, OPTION_NOCLIP},
+ { "msatur", no_argument, NULL, OPTION_SATUR},
+ { "mno-satur", no_argument, NULL, OPTION_NOSATUR},
+ { "mcop32", no_argument, NULL, OPTION_COP32},
+ { "mdebug", no_argument, NULL, OPTION_DEBUG},
+ { "mno-debug", no_argument, NULL, OPTION_NODEBUG},
+ { "mlibrary", no_argument, NULL, OPTION_LIBRARY},
+ { NULL, 0, NULL, 0 } };
+size_t md_longopts_size = sizeof (md_longopts);
+
+const char * md_shortopts = "";
+static int optbits = 0;
+static int optbitset = 0;
+
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+ int i, idx;
+ switch (c)
+ {
+ case OPTION_EB:
+ target_big_endian = 1;
+ break;
+ case OPTION_EL:
+ target_big_endian = 0;
+ break;
+ case OPTION_CONFIG:
+ idx = 0;
+ for (i=1; mep_config_map[i].name; i++)
+ if (strcmp (mep_config_map[i].name, arg) == 0)
+ {
+ idx = i;
+ break;
+ }
+ if (!idx)
+ {
+ fprintf (stderr, "Error: unknown configuration %s\n", arg);
+ return 0;
+ }
+ mep_config_index = idx;
+ target_big_endian = mep_config_map[idx].big_endian;
+ break;
+ case OPTION_AVERAGE:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+ break;
+ case OPTION_NOAVERAGE:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_AVE_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_AVE_INSN;
+ break;
+ case OPTION_MULT:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+ break;
+ case OPTION_NOMULT:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_MUL_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_MUL_INSN;
+ break;
+ case OPTION_DIV:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+ break;
+ case OPTION_NODIV:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_DIV_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_DIV_INSN;
+ break;
+ case OPTION_BITOPS:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+ break;
+ case OPTION_NOBITOPS:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_BIT_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_BIT_INSN;
+ break;
+ case OPTION_LEADZ:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+ break;
+ case OPTION_NOLEADZ:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_LDZ_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_LDZ_INSN;
+ break;
+ case OPTION_ABSDIFF:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+ break;
+ case OPTION_NOABSDIFF:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_ABS_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_ABS_INSN;
+ break;
+ case OPTION_MINMAX:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+ break;
+ case OPTION_NOMINMAX:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_MINMAX_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN;
+ break;
+ case OPTION_CLIP:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+ break;
+ case OPTION_NOCLIP:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_CLIP_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_CLIP_INSN;
+ break;
+ case OPTION_SATUR:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+ break;
+ case OPTION_NOSATUR:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_SAT_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_SAT_INSN;
+ break;
+ case OPTION_COP32:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_CP_INSN;
+ break;
+ case OPTION_DEBUG:
+ optbits |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+ break;
+ case OPTION_NODEBUG:
+ optbits &= ~(1 << CGEN_INSN_OPTIONAL_DEBUG_INSN);
+ optbitset |= 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN;
+ break;
+ case OPTION_LIBRARY:
+ library_flag = EF_MEP_LIBRARY;
+ break;
+ case OPTION_REPEAT:
+ case OPTION_NOREPEAT:
+ break;
+ default:
+ return 0;
+ }
+ return 1;
+}
+
+void
+md_show_usage (FILE *stream)
+{
+ fprintf (stream, _("MeP specific command line options:\n\
+ -EB assemble for a big endian system (default)\n\
+ -EL assemble for a little endian system\n\
+ -mconfig=<name> specify a chip configuration to use\n\
+ -maverage -mno-average -mmult -mno-mult -mdiv -mno-div\n\
+ -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff\n\
+ -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32\n\
+ enable/disable the given opcodes\n\
+\n\
+ If -mconfig is given, the other -m options modify it. Otherwise,\n\
+ if no -m options are given, all core opcodes are enabled;\n\
+ if any enabling -m options are given, only those are enabled;\n\
+ if only disabling -m options are given, only those are disabled.\n\
+"));
+ if (mep_config_map[1].name)
+ {
+ int i;
+ fprintf (stream, " -mconfig=STR specify the configuration to use\n");
+ fprintf (stream, " Configurations:");
+ for (i=0; mep_config_map[i].name; i++)
+ fprintf (stream, " %s", mep_config_map[i].name);
+ fprintf (stream, "\n");
+ }
+}
+
+\f
+
+static void
+mep_check_for_disabled_registers (mep_insn *insn)
+{
+ static int initted = 0;
+ static int has_mul_div = 0;
+ static int has_cop = 0;
+ static int has_debug = 0;
+ unsigned int b, r;
+
+ if (allow_disabled_registers)
+ return;
+
+#if !CGEN_INT_INSN_P
+ if (target_big_endian)
+ b = insn->buffer[0] * 256 + insn->buffer[1];
+ else
+ b = insn->buffer[1] * 256 + insn->buffer[0];
+#else
+ b = insn->buffer[0];
+#endif
+
+ if ((b & 0xfffff00e) == 0x7008 /* stc */
+ || (b & 0xfffff00e) == 0x700a /* ldc */)
+ {
+ if (!initted)
+ {
+ initted = 1;
+ if ((MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_MUL_INSN))
+ || (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DIV_INSN)))
+ has_mul_div = 1;
+ if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN))
+ has_debug = 1;
+ if (MEP_OMASK & (1 << CGEN_INSN_OPTIONAL_CP_INSN))
+ has_cop = 1;
+ }
+
+ r = ((b & 0x00f0) >> 4) | ((b & 0x0001) << 4);
+ switch (r)
+ {
+ case 7: /* $hi */
+ case 8: /* $lo */
+ if (!has_mul_div)
+ as_bad ("$hi and $lo are disabled when MUL and DIV are off");
+ break;
+ case 12: /* $mb0 */
+ case 13: /* $me0 */
+ case 14: /* $mb1 */
+ case 15: /* $me1 */
+ if (!has_cop)
+ as_bad ("$mb0, $me0, $mb1, and $me1 are disabled when COP is off");
+ break;
+ case 24: /* $dbg */
+ case 25: /* $depc */
+ if (!has_debug)
+ as_bad ("$dbg and $depc are disabled when DEBUG is off");
+ break;
+ }
+ }
+}
+
+static int
+mep_machine (void)
+{
+ switch (MEP_CPU)
+ {
+ default: break;
+ case EF_MEP_CPU_C2: return bfd_mach_mep;
+ case EF_MEP_CPU_C3: return bfd_mach_mep;
+ case EF_MEP_CPU_C4: return bfd_mach_mep;
+ case EF_MEP_CPU_H1: return bfd_mach_mep_h1;
+ }
+
+ return bfd_mach_mep;
+}
+
+/* The MeP version of the cgen parse_operand function. The only difference
+ from the standard version is that we want to avoid treating '$foo' and
+ '($foo...)' as references to a symbol called '$foo'. The chances are
+ that '$foo' is really a misspelt register. */
+
+static const char *
+mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
+ const char **strP, int opindex, int opinfo,
+ enum cgen_parse_operand_result *resultP, bfd_vma *valueP)
+{
+ if (want == CGEN_PARSE_OPERAND_INTEGER || want == CGEN_PARSE_OPERAND_ADDRESS)
+ {
+ const char *next;
+
+ next = *strP;
+ while (*next == '(')
+ next++;
+ if (*next == '$')
+ return "Not a valid literal";
+ }
+ return gas_cgen_parse_operand (cd, want, strP, opindex, opinfo,
+ resultP, valueP);
+}
+
+void
+md_begin ()
+{
+ /* Initialize the `cgen' interface. */
+
+ /* If the user specifies no options, we default to allowing
+ everything. If the user specifies any enabling options, we
+ default to allowing only what is specified. If the user
+ specifies only disabling options, we only disable what is
+ specified. If the user specifies options and a config, the
+ options modify the config. */
+ if (optbits && mep_config_index == 0)
+ MEP_OMASK = optbits;
+ else
+ MEP_OMASK = (MEP_OMASK & ~optbitset) | optbits;
+
+ /* Set the machine number and endian. */
+ gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
+ CGEN_CPU_OPEN_ENDIAN,
+ target_big_endian
+ ? CGEN_ENDIAN_BIG
+ : CGEN_ENDIAN_LITTLE,
+ CGEN_CPU_OPEN_ISAS, 0,
+ CGEN_CPU_OPEN_END);
+ mep_cgen_init_asm (gas_cgen_cpu_desc);
+
+ /* This is a callback from cgen to gas to parse operands. */
+ cgen_set_parse_operand_fn (gas_cgen_cpu_desc, mep_parse_operand);
+
+ /* Identify the architecture. */
+ bfd_default_set_arch_mach (stdoutput, bfd_arch_mep, mep_machine ());
+
+ /* Store the configuration number and core. */
+ bfd_set_private_flags (stdoutput, MEP_CPU | MEP_CONFIG | library_flag);
+
+ /* Initialize the array we'll be using to store fixups. */
+ gas_cgen_initialize_saved_fixups_array();
+}
+
+/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a
+ coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */
+
+static const CGEN_INSN *
+mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd,
+ const char *str,
+ CGEN_FIELDS *fields,
+ CGEN_INSN_BYTES_PTR buf,
+ const struct cgen_insn *pinsn)
+{
+ const char *start;
+ CGEN_INSN_LIST *ilist;
+ const char *errmsg = NULL;
+
+ /* The instructions are stored in hashed lists. */
+ ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc,
+ CGEN_INSN_MNEMONIC (pinsn));
+
+ start = str;
+ for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+ {
+ const CGEN_INSN *insn = ilist->insn;
+ if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn),
+ CGEN_INSN_MNEMONIC (pinsn)) == 0
+ && MEP_INSN_COP_P (ilist->insn)
+ && mep_cgen_insn_supported (cd, insn))
+ {
+ str = start;
+
+ /* skip this insn if str doesn't look right lexically */
+ if (CGEN_INSN_RX (insn) != NULL &&
+ regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+ continue;
+
+ /* Allow parse/insert handlers to obtain length of insn. */
+ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+ errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+ if (errmsg != NULL)
+ continue;
+
+ errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+ (bfd_vma) 0);
+ if (errmsg != NULL)
+ continue;
+
+ return insn;
+ }
+ }
+ return pinsn;
+}
+
+static void
+mep_save_insn (mep_insn insn)
+{
+ /* Consider change MAX_SAVED_FIXUP_CHAINS to MAX_PARALLEL_INSNS. */
+ if (num_insns_saved < 0 || num_insns_saved >= MAX_SAVED_FIXUP_CHAINS)
+ {
+ as_fatal("index into saved_insns[] out of bounds.");
+ return;
+ }
+ saved_insns[num_insns_saved] = insn;
+ gas_cgen_save_fixups(num_insns_saved);
+ num_insns_saved++;
+}
+
+static void
+mep_check_parallel32_scheduling (void)
+{
+ int insn0iscopro, insn1iscopro, insn0length, insn1length;
+
+ /* More than two instructions means that either someone is referring to
+ an internally parallel core or an internally parallel coprocessor,
+ neither of which are supported at this time. */
+ if ( num_insns_saved > 2 )
+ as_fatal("Internally paralled cores and coprocessors not supported.");
+
+ /* If there are no insns saved, that's ok. Just return. This will
+ happen when mep_process_saved_insns is called when the end of the
+ source file is reached and there are no insns left to be processed. */
+ if (num_insns_saved == 0)
+ return;
+
+ /* Check some of the attributes of the first insn. */
+ insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
+ insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
+
+ if (num_insns_saved == 2)
+ {
+ /* Check some of the attributes of the first insn. */
+ insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
+ insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
+
+ if ((insn0iscopro && !insn1iscopro)
+ || (insn1iscopro && !insn0iscopro))
+ {
+ /* We have one core and one copro insn. If their sizes
+ add up to 32, then the combination is valid. */
+ if (insn0length + insn1length == 32)
+ return;
+ else
+ as_bad ("core and copro insn lengths must total 32 bits.");
+ }
+ else
+ as_bad ("vliw group must consist of 1 core and 1 copro insn.");
+ }
+ else
+ {
+ /* If we arrive here, we have one saved instruction. There are a
+ number of possible cases:
+
+ 1. The instruction is a 32 bit core or coprocessor insn and
+ can be executed by itself. Valid.
+
+ 2. The instrucion is a core instruction for which a cop nop
+ exists. In this case, insert the cop nop into the saved
+ insn array after the core insn and return. Valid.
+
+ 3. The instruction is a coprocessor insn for which a core nop
+ exists. In this case, move the coprocessor insn to the
+ second element of the array and put the nop in the first
+ element then return. Valid.
+
+ 4. The instruction is a core or coprocessor instruction for
+ which there is no matching coprocessor or core nop to use
+ to form a valid vliw insn combination. In this case, we
+ we have to abort. */
+
+ if (insn0length > 32)
+ as_fatal ("Cannot use 48- or 64-bit insns with a 32 bit datapath.");
+
+ if (insn0length == 32)
+ return;
+
+ /* Insn is smaller than datapath. If there are no matching
+ nops for this insn, then terminate assembly. */
+ if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
+ CGEN_INSN_VLIW32_NO_MATCHING_NOP))
+ as_fatal ("No valid nop.");
+
+ /* At this point we know that we have a single 16-bit insn that has
+ a matching nop. We have to assemble it and put it into the saved
+ insn and fixup chain arrays. */
+
+ if (insn0iscopro)
+ {
+ char *errmsg;
+ mep_insn insn;
+
+ /* Move the insn and it's fixups to the second element of the
+ saved insns arrary and insert a 16 bit core nope into the
+ first element. */
+ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
+ &insn.fields, insn.buffer,
+ &errmsg);
+ if (!insn.insn)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+
+ /* Move the insn in element 0 to element 1 and insert the
+ nop into element 0. Move the fixups in element 0 to
+ element 1 and save the current fixups to element 0.
+ Really there aren't any fixups at this point because we're
+ inserting a nop but we might as well be general so that
+ if there's ever a need to insert a general insn, we'll
+ have an example. */
+ saved_insns[1] = saved_insns[0];
+ saved_insns[0] = insn;
+ num_insns_saved++;
+ gas_cgen_swap_fixups (0);
+ gas_cgen_save_fixups (1);
+ }
+ else
+ {
+ char * errmsg;
+ mep_insn insn;
+ int insn_num = saved_insns[0].insn->base->num;
+
+ /* Use 32 bit branches and skip the nop. */
+ if (insn_num == MEP_INSN_BSR12
+ || insn_num == MEP_INSN_BEQZ
+ || insn_num == MEP_INSN_BNEZ)
+ return;
+
+ /* Insert a 16-bit coprocessor nop. Note that at the time */
+ /* this was done, no 16-bit coprocessor nop was defined. */
+ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
+ &insn.fields, insn.buffer,
+ &errmsg);
+ if (!insn.insn)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+
+ /* Now put the insn and fixups into the arrays. */
+ mep_save_insn (insn);
+ }
+ }
+}
+
+static void
+mep_check_parallel64_scheduling (void)
+{
+ int insn0iscopro, insn1iscopro, insn0length, insn1length;
+
+ /* More than two instructions means that someone is referring to an
+ internally parallel core or an internally parallel coprocessor. */
+ /* These are not currently supported. */
+ if (num_insns_saved > 2)
+ as_fatal ("Internally parallel cores of coprocessors not supported.");
+
+ /* If there are no insns saved, that's ok. Just return. This will
+ happen when mep_process_saved_insns is called when the end of the
+ source file is reached and there are no insns left to be processed. */
+ if (num_insns_saved == 0)
+ return;
+
+ /* Check some of the attributes of the first insn. */
+ insn0iscopro = MEP_INSN_COP_P (saved_insns[0].insn);
+ insn0length = CGEN_FIELDS_BITSIZE (& saved_insns[0].fields);
+
+ if (num_insns_saved == 2)
+ {
+ /* Check some of the attributes of the first insn. */
+ insn1iscopro = MEP_INSN_COP_P (saved_insns[1].insn);
+ insn1length = CGEN_FIELDS_BITSIZE (& saved_insns[1].fields);
+
+ if ((insn0iscopro && !insn1iscopro)
+ || (insn1iscopro && !insn0iscopro))
+ {
+ /* We have one core and one copro insn. If their sizes
+ add up to 64, then the combination is valid. */
+ if (insn0length + insn1length == 64)
+ return;
+ else
+ as_bad ("core and copro insn lengths must total 64 bits.");
+ }
+ else
+ as_bad ("vliw group must consist of 1 core and 1 copro insn.");
+ }
+ else
+ {
+ /* If we arrive here, we have one saved instruction. There are a
+ number of possible cases:
+
+ 1. The instruction is a 64 bit coprocessor insn and can be
+ executed by itself. Valid.
+
+ 2. The instrucion is a core instruction for which a cop nop
+ exists. In this case, insert the cop nop into the saved
+ insn array after the core insn and return. Valid.
+
+ 3. The instruction is a coprocessor insn for which a core nop
+ exists. In this case, move the coprocessor insn to the
+ second element of the array and put the nop in the first
+ element then return. Valid.
+
+ 4. The instruction is a core or coprocessor instruction for
+ which there is no matching coprocessor or core nop to use
+ to form a valid vliw insn combination. In this case, we
+ we have to abort. */
+
+ /* If the insn is 64 bits long, it can run alone. The size check
+ is done indepependantly of whether the insn is core or copro
+ in case 64 bit coprocessor insns are added later. */
+ if (insn0length == 64)
+ return;
+
+ /* Insn is smaller than datapath. If there are no matching
+ nops for this insn, then terminate assembly. */
+ if (CGEN_INSN_ATTR_VALUE (saved_insns[0].insn,
+ CGEN_INSN_VLIW64_NO_MATCHING_NOP))
+ as_fatal ("No valid nop.");
+
+ if (insn0iscopro)
+ {
+ char *errmsg;
+ mep_insn insn;
+ int i;
+
+ /* Initialize the insn buffer. */
+ for (i = 0; i < 64; i++)
+ insn.buffer[i] = '\0';
+
+ /* We have a coprocessor insn. At this point in time there
+ are is 32-bit core nop. There is only a 16-bit core
+ nop. The idea is to allow for a relatively arbitrary
+ coprocessor to be specified. We aren't looking at
+ trying to cover future changes in the core at this time
+ since it is assumed that the core will remain fairly
+ static. If there ever are 32 or 48 bit core nops added,
+ they will require entries below. */
+
+ if (insn0length == 48)
+ {
+ /* Move the insn and fixups to the second element of the
+ arrays then assemble and insert a 16 bit core nop. */
+ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
+ & insn.fields, insn.buffer,
+ & errmsg);
+ }
+ else
+ {
+ /* If this is reached, then we have a single coprocessor
+ insn that is not 48 bits long, but for which the assembler
+ thinks there is a matching core nop. If a 32-bit core
+ nop has been added, then make the necessary changes and
+ handle its assembly and insertion here. Otherwise,
+ go figure out why either:
+
+ 1. The assembler thinks that there is a 32-bit core nop
+ to match a 32-bit coprocessor insn, or
+ 2. The assembler thinks that there is a 48-bit core nop
+ to match a 16-bit coprocessor insn. */
+
+ as_fatal ("Assembler expects a non-existent core nop.");
+ }
+
+ if (!insn.insn)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+
+ /* Move the insn in element 0 to element 1 and insert the
+ nop into element 0. Move the fixups in element 0 to
+ element 1 and save the current fixups to element 0.
+ Really there aren't any fixups at this point because we're
+ inserting a nop but we might as well be general so that
+ if there's ever a need to insert a general insn, we'll
+ have an example. */
+
+ saved_insns[1] = saved_insns[0];
+ saved_insns[0] = insn;
+ num_insns_saved++;
+ gas_cgen_swap_fixups(0);
+ gas_cgen_save_fixups(1);
+
+ }
+ else
+ {
+ char * errmsg;
+ mep_insn insn;
+ int i;
+
+ /* Initialize the insn buffer */
+ for (i = 0; i < 64; i++)
+ insn.buffer[i] = '\0';
+
+ /* We have a core insn. We have to handle all possible nop
+ lengths. If a coprocessor doesn't have a nop of a certain
+ length but there exists core insns that when combined with
+ a nop of that length would fill the datapath, those core
+ insns will be flagged with the VLIW_NO_CORRESPONDING_NOP
+ attribute. That will ensure that when used in a way that
+ requires a nop to be inserted, assembly will terminate
+ before reaching this section of code. This guarantees
+ that cases below which would result in the attempted
+ insertion of nop that doesn't exist will never be entered. */
+ if (insn0length == 16)
+ {
+ /* Insert 48 bit coprocessor nop. */
+ /* Assemble it and put it into the arrays. */
+ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop48",
+ &insn.fields, insn.buffer,
+ &errmsg);
+ }
+ else if (insn0length == 32)
+ {
+ /* Insert 32 bit coprocessor nop. */
+ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop32",
+ &insn.fields, insn.buffer,
+ &errmsg);
+ }
+ else if (insn0length == 48)
+ {
+ /* Insert 16 bit coprocessor nop. */
+ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "cpnop16",
+ &insn.fields, insn.buffer,
+ &errmsg);
+ }
+ else
+ /* Core insn has an invalid length. Something has gone wrong. */
+ as_fatal ("Core insn has invalid length! Something is wrong!");
+
+ if (!insn.insn)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+
+ /* Now put the insn and fixups into the arrays. */
+ mep_save_insn (insn);
+ }
+ }
+}
+
+/* The scheduling functions are just filters for invalid combinations.
+ If there is a violation, they terminate assembly. Otherise they
+ just fall through. Succesful combinations cause no side effects
+ other than valid nop insertion. */
+
+static void
+mep_check_parallel_scheduling (void)
+{
+ /* This is where we will eventually read the config information
+ and choose which scheduling checking function to call. */
+ if (MEP_VLIW64)
+ mep_check_parallel64_scheduling ();
+ else
+ mep_check_parallel32_scheduling ();
+}
+
+static void
+mep_process_saved_insns (void)
+{
+ int i;
+
+ gas_cgen_save_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
+
+ /* We have to check for valid scheduling here. */
+ mep_check_parallel_scheduling ();
+
+ /* If the last call didn't cause assembly to terminate, we have
+ a valid vliw insn/insn pair saved. Restore this instructions'
+ fixups and process the insns. */
+ for (i = 0;i<num_insns_saved;i++)
+ {
+ gas_cgen_restore_fixups (i);
+ gas_cgen_finish_insn (saved_insns[i].insn, saved_insns[i].buffer,
+ CGEN_FIELDS_BITSIZE (& saved_insns[i].fields),
+ 1, NULL);
+ }
+ gas_cgen_restore_fixups (MAX_SAVED_FIXUP_CHAINS - 1);
+
+ /* Clear the fixups and reset the number insn saved to 0. */
+ gas_cgen_initialize_saved_fixups_array ();
+ num_insns_saved = 0;
+ listing_prev_line ();
+}
+
+void
+md_assemble (char * str)
+{
+ static CGEN_BITSET* isas = NULL;
+ char * errmsg;
+
+ /* Initialize GAS's cgen interface for a new instruction. */
+ gas_cgen_init_parse ();
+
+ /* There are two possible modes: core and vliw. We have to assemble
+ differently for each.
+
+ Core Mode: We assemble normally. All instructions are on a
+ single line and are made up of one mnemonic and one
+ set of operands.
+ VLIW Mode: Vliw combinations are indicated as follows:
+
+ core insn
+ + copro insn
+
+ We want to handle the general case where more than
+ one instruction can be preceeded by a +. This will
+ happen later if we add support for internally parallel
+ coprocessors. We'll make the parsing nice and general
+ so that it can handle an arbitrary number of insns
+ with leading +'s. The actual checking for valid
+ combinations is done elsewhere. */
+
+ /* Initialize the isa to refer to the core. */
+ if (isas == NULL)
+ isas = cgen_bitset_copy (& MEP_CORE_ISA);
+ else
+ {
+ cgen_bitset_clear (isas);
+ cgen_bitset_union (isas, & MEP_CORE_ISA, isas);
+ }
+ gas_cgen_cpu_desc->isas = isas;
+
+ if (mode == VLIW)
+ {
+ /* VLIW mode. */
+
+ int thisInsnIsCopro = 0;
+ mep_insn insn;
+ int i;
+
+ /* Initialize the insn buffer */
+
+ if (! CGEN_INT_INSN_P)
+ for (i=0; i < CGEN_MAX_INSN_SIZE; i++)
+ insn.buffer[i]='\0';
+
+ /* Can't tell core / copro insns apart at parse time! */
+ cgen_bitset_union (isas, & MEP_COP_ISA, isas);
+
+ /* Assemble the insn so we can examine its attributes. */
+ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, str,
+ &insn.fields, insn.buffer,
+ &errmsg);
+ if (!insn.insn)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+ mep_check_for_disabled_registers (&insn);
+
+ /* Check to see if it's a coprocessor instruction. */
+ thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
+
+ if (!thisInsnIsCopro)
+ {
+ insn.insn = mep_cgen_assemble_cop_insn (gas_cgen_cpu_desc, str,
+ &insn.fields, insn.buffer,
+ insn.insn);
+ thisInsnIsCopro = MEP_INSN_COP_P (insn.insn);
+ mep_check_for_disabled_registers (&insn);
+ }
+
+ if (pluspresent)
+ {
+ /* A plus was present. */
+ /* Check for a + with a core insn and abort if found. */
+ if (!thisInsnIsCopro)
+ {
+ as_fatal("A core insn cannot be preceeded by a +.\n");
+ return;
+ }
+
+ if (num_insns_saved > 0)
+ {
+ /* There are insns in the queue. Add this one. */
+ mep_save_insn (insn);
+ }
+ else
+ {
+ /* There are no insns in the queue and a plus is present.
+ This is a syntax error. Let's not tolerate this.
+ We can relax this later if necessary. */
+ as_bad (_("Invalid use of parallelization operator."));
+ return;
+ }
+ }
+ else
+ {
+ /* No plus was present. */
+ if (num_insns_saved > 0)
+ {
+ /* There are insns saved and we came across an insn without a
+ leading +. That's the signal to process the saved insns
+ before proceeding then treat the current insn as the first
+ in a new vliw group. */
+ mep_process_saved_insns ();
+ num_insns_saved = 0;
+ /* mep_save_insn (insn); */
+ }
+ mep_save_insn (insn);
+#if 0
+ else
+ {
+
+ /* Core Insn. Add it to the beginning of the queue. */
+ mep_save_insn (insn);
+ /* gas_cgen_save_fixups(num_insns_saved); */
+ }
+#endif
+ }
+
+ pluspresent = 0;
+ }
+ else
+ {
+ /* Core mode. */
+
+ /* Only single instructions are assembled in core mode. */
+ mep_insn insn;
+
+ /* If a leading '+' was present, issue an error.
+ That's not allowed in core mode. */
+ if (pluspresent)
+ {
+ as_bad (_("Leading plus sign not allowed in core mode"));
+ return;
+ }
+
+ insn.insn = mep_cgen_assemble_insn
+ (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
+
+ if (!insn.insn)
+ {
+ as_bad ("%s", errmsg);
+ return;
+ }
+ gas_cgen_finish_insn (insn.insn, insn.buffer,
+ CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
+ mep_check_for_disabled_registers (&insn);
+ }
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+ int align = bfd_get_section_alignment (stdoutput, segment);
+ return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+\f
+/* Interface to relax_segment. */
+
+
+const relax_typeS md_relax_table[] =
+{
+ /* The fields are:
+ 1) most positive reach of this state,
+ 2) most negative reach of this state,
+ 3) how many bytes this mode will have in the variable part of the frag
+ 4) which index into the table to try if we can't fit into this one. */
+ /* Note that we use "beq" because "jmp" has a peculiarity - it cannot
+ jump to addresses with any bits 27..24 set. So, we use beq as a
+ 17-bit pc-relative branch to avoid using jmp, just in case. */
+
+ /* 0 */ { 0, 0, 0, 0 }, /* unused */
+ /* 1 */ { 0, 0, 0, 0 }, /* marker for "don't know yet" */
+
+ /* 2 */ { 2047, -2048, 0, 3 }, /* bsr12 */
+ /* 3 */ { 0, 0, 2, 0 }, /* bsr16 */
+
+ /* 4 */ { 2047, -2048, 0, 5 }, /* bra */
+ /* 5 */ { 65535, -65536, 2, 6 }, /* beq $0,$0 */
+ /* 6 */ { 0, 0, 2, 0 }, /* jmp24 */
+
+ /* 7 */ { 65535, -65536, 0, 8 }, /* beqi */
+ /* 8 */ { 0, 0, 4, 0 }, /* bnei/jmp */
+
+ /* 9 */ { 127, -128, 0, 10 }, /* beqz */
+ /* 10 */ { 65535, -65536, 2, 11 }, /* beqi */
+ /* 11 */ { 0, 0, 4, 0 }, /* bnei/jmp */
+
+ /* 12 */ { 65535, -65536, 0, 13 }, /* bnei */
+ /* 13 */ { 0, 0, 4, 0 }, /* beqi/jmp */
+
+ /* 14 */ { 127, -128, 0, 15 }, /* bnez */
+ /* 15 */ { 65535, -65536, 2, 16 }, /* bnei */
+ /* 16 */ { 0, 0, 4, 0 }, /* beqi/jmp */
+
+ /* 17 */ { 65535, -65536, 0, 13 }, /* bgei */
+ /* 18 */ { 0, 0, 4, 0 },
+ /* 19 */ { 65535, -65536, 0, 13 }, /* blti */
+ /* 20 */ { 0, 0, 4, 0 },
+ /* 19 */ { 65535, -65536, 0, 13 }, /* bcpeq */
+ /* 20 */ { 0, 0, 4, 0 },
+ /* 19 */ { 65535, -65536, 0, 13 }, /* bcpne */
+ /* 20 */ { 0, 0, 4, 0 },
+ /* 19 */ { 65535, -65536, 0, 13 }, /* bcpat */
+ /* 20 */ { 0, 0, 4, 0 },
+ /* 19 */ { 65535, -65536, 0, 13 }, /* bcpaf */
+ /* 20 */ { 0, 0, 4, 0 }
+};
+
+/* Pseudo-values for 64 bit "insns" which are combinations of two 32
+ bit insns. */
+typedef enum {
+ MEP_PSEUDO64_NONE,
+ MEP_PSEUDO64_16BITCC,
+ MEP_PSEUDO64_32BITCC,
+} MepPseudo64Values;
+
+static struct {
+ int insn;
+ int growth;
+ int insn_for_extern;
+} subtype_mappings[] = {
+ { 0, 0, 0 },
+ { 0, 0, 0 },
+ { MEP_INSN_BSR12, 0, MEP_INSN_BSR24 },
+ { MEP_INSN_BSR24, 2, MEP_INSN_BSR24 },
+ { MEP_INSN_BRA, 0, MEP_INSN_BRA },
+ { MEP_INSN_BEQ, 2, MEP_INSN_BEQ },
+ { MEP_INSN_JMP, 2, MEP_INSN_JMP },
+ { MEP_INSN_BEQI, 0, MEP_INSN_BEQI },
+ { -1, 4, MEP_PSEUDO64_32BITCC },
+ { MEP_INSN_BEQZ, 0, MEP_INSN_BEQZ },
+ { MEP_INSN_BEQI, 2, MEP_INSN_BEQI },
+ { -1, 4, MEP_PSEUDO64_16BITCC },
+ { MEP_INSN_BNEI, 0, MEP_INSN_BNEI },
+ { -1, 4, MEP_PSEUDO64_32BITCC },
+ { MEP_INSN_BNEZ, 0, MEP_INSN_BNEZ },
+ { MEP_INSN_BNEI, 2, MEP_INSN_BNEI },
+ { -1, 4, MEP_PSEUDO64_16BITCC },
+ { MEP_INSN_BGEI, 0, MEP_INSN_BGEI },
+ { -1, 4, MEP_PSEUDO64_32BITCC },
+ { MEP_INSN_BLTI, 0, MEP_INSN_BLTI },
+ { -1, 4, MEP_PSEUDO64_32BITCC },
+ { MEP_INSN_BCPEQ, 0, MEP_INSN_BCPEQ },
+ { -1, 4, MEP_PSEUDO64_32BITCC },
+ { MEP_INSN_BCPNE, 0, MEP_INSN_BCPNE },
+ { -1, 4, MEP_PSEUDO64_32BITCC },
+ { MEP_INSN_BCPAT, 0, MEP_INSN_BCPAT },
+ { -1, 4, MEP_PSEUDO64_32BITCC },
+ { MEP_INSN_BCPAF, 0, MEP_INSN_BCPAF },
+ { -1, 4, MEP_PSEUDO64_32BITCC }
+};
+#define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
+
+void
+mep_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
+{
+ symbolS *symbolP = fragP->fr_symbol;
+ if (symbolP && !S_IS_DEFINED (symbolP))
+ *aim = 0;
+ /* Adjust for MeP pcrel not being relative to the next opcode. */
+ *aim += 2 + md_relax_table[this_state].rlx_length;
+}
+
+static int
+insn_to_subtype (int insn)
+{
+ unsigned int i;
+ for (i=0; i<NUM_MAPPINGS; i++)
+ if (insn == subtype_mappings[i].insn)
+ return i;
+ abort ();
+}
+
+/* Return an initial guess of the length by which a fragment must grow
+ to hold a branch to reach its destination. Also updates fr_type
+ and fr_subtype as necessary.
+
+ Called just before doing relaxation. Any symbol that is now
+ undefined will not become defined. The guess for fr_var is
+ ACTUALLY the growth beyond fr_fix. Whatever we do to grow fr_fix
+ or fr_var contributes to our returned value. Although it may not
+ be explicit in the frag, pretend fr_var starts with a 0 value. */
+
+int
+md_estimate_size_before_relax (fragS * fragP, segT segment)
+{
+ if (fragP->fr_subtype == 1)
+ fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
+
+ if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
+ {
+ int new_insn;
+
+ new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
+ fragP->fr_subtype = insn_to_subtype (new_insn);
+ }
+
+ if (MEP_VLIW && ! MEP_VLIW64
+ && (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW))
+ {
+ /* Use 32 bit branches for vliw32 so the vliw word is not split. */
+ switch (fragP->fr_cgen.insn->base->num)
+ {
+ case MEP_INSN_BSR12:
+ fragP->fr_subtype = insn_to_subtype
+ (subtype_mappings[fragP->fr_subtype].insn_for_extern);
+ break;
+ case MEP_INSN_BEQZ:
+ fragP->fr_subtype ++;
+ break;
+ case MEP_INSN_BNEZ:
+ fragP->fr_subtype ++;
+ break;
+ }
+ }
+
+ if (fragP->fr_cgen.insn->base
+ && fragP->fr_cgen.insn->base->num
+ != subtype_mappings[fragP->fr_subtype].insn)
+ {
+ int new_insn= subtype_mappings[fragP->fr_subtype].insn;
+ if (new_insn != -1)
+ {
+ fragP->fr_cgen.insn = (fragP->fr_cgen.insn
+ - fragP->fr_cgen.insn->base->num
+ + new_insn);
+ }
+ }
+
+ return subtype_mappings[fragP->fr_subtype].growth;
+}
+
+/* *fragP has been relaxed to its final size, and now needs to have
+ the bytes inside it modified to conform to the new size.
+
+ Called after relaxation is finished.
+ fragP->fr_type == rs_machine_dependent.
+ fragP->fr_subtype is the subtype of what the address relaxed to. */
+
+static int
+target_address_for (fragS *frag)
+{
+ int rv = frag->fr_offset;
+ symbolS *sym = frag->fr_symbol;
+
+ if (sym)
+ rv += S_GET_VALUE (sym);
+
+ return rv;
+}
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+ segT sec ATTRIBUTE_UNUSED,
+ fragS *fragP)
+{
+ int addend, rn, bit = 0;
+ int operand;
+ int where = fragP->fr_opcode - fragP->fr_literal;
+ int e = target_big_endian ? 0 : 1;
+
+ addend = target_address_for (fragP) - (fragP->fr_address + where);
+
+ if (subtype_mappings[fragP->fr_subtype].insn == -1)
+ {
+ fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
+ switch (subtype_mappings[fragP->fr_subtype].insn_for_extern)
+ {
+ case MEP_PSEUDO64_16BITCC:
+ fragP->fr_opcode[1^e] = ((fragP->fr_opcode[1^e] & 1) ^ 1) | 0x06;
+ fragP->fr_opcode[2^e] = 0xd8;
+ fragP->fr_opcode[3^e] = 0x08;
+ fragP->fr_opcode[4^e] = 0;
+ fragP->fr_opcode[5^e] = 0;
+ where += 2;
+ break;
+ case MEP_PSEUDO64_32BITCC:
+ if (fragP->fr_opcode[0^e] & 0x10)
+ fragP->fr_opcode[1^e] ^= 0x01;
+ else
+ fragP->fr_opcode[1^e] ^= 0x04;
+ fragP->fr_opcode[2^e] = 0;
+ fragP->fr_opcode[3^e] = 4;
+ fragP->fr_opcode[4^e] = 0xd8;
+ fragP->fr_opcode[5^e] = 0x08;
+ fragP->fr_opcode[6^e] = 0;
+ fragP->fr_opcode[7^e] = 0;
+ where += 4;
+ break;
+ default:
+ abort ();
+ }
+ fragP->fr_cgen.insn = (fragP->fr_cgen.insn
+ - fragP->fr_cgen.insn->base->num
+ + MEP_INSN_JMP);
+ operand = MEP_OPERAND_PCABS24A2;
+ }
+ else
+ switch (fragP->fr_cgen.insn->base->num)
+ {
+ case MEP_INSN_BSR12:
+ fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
+ fragP->fr_opcode[1^e] = 0x01 | (addend & 0xfe);
+ operand = MEP_OPERAND_PCREL12A2;
+ break;
+
+ case MEP_INSN_BSR24:
+ fragP->fr_fix += 2;
+ fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
+ fragP->fr_opcode[1^e] = 0x09 | ((addend << 3) & 0xf0);
+ fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
+ fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
+ operand = MEP_OPERAND_PCREL24A2;
+ break;
+
+ case MEP_INSN_BRA:
+ fragP->fr_opcode[0^e] = 0xb0 | ((addend >> 8) & 0x0f);
+ fragP->fr_opcode[1^e] = 0x00 | (addend & 0xfe);
+ operand = MEP_OPERAND_PCREL12A2;
+ break;
+
+ case MEP_INSN_BEQ:
+ /* The default relax_frag doesn't change the state if there is no
+ growth, so we must manually handle converting out-of-range BEQ
+ instructions to JMP. */
+ if (addend <= 65535 && addend >= -65536)
+ {
+ fragP->fr_fix += 2;
+ fragP->fr_opcode[0^e] = 0xe0;
+ fragP->fr_opcode[1^e] = 0x01;
+ fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
+ fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
+ operand = MEP_OPERAND_PCREL17A2;
+ break;
+ }
+ /* ...FALLTHROUGH... */
+
+ case MEP_INSN_JMP:
+ addend = target_address_for (fragP);
+ fragP->fr_fix += 2;
+ fragP->fr_opcode[0^e] = 0xd8 | ((addend >> 5) & 0x07);
+ fragP->fr_opcode[1^e] = 0x08 | ((addend << 3) & 0xf0);
+ fragP->fr_opcode[2^e] = 0x00 | ((addend >>16) & 0xff);
+ fragP->fr_opcode[3^e] = 0x00 | ((addend >> 8) & 0xff);
+ operand = MEP_OPERAND_PCABS24A2;
+ break;
+
+ case MEP_INSN_BNEZ:
+ bit = 1;
+ case MEP_INSN_BEQZ:
+ fragP->fr_opcode[1^e] = bit | (addend & 0xfe);
+ operand = MEP_OPERAND_PCREL8A2;
+ break;
+
+ case MEP_INSN_BNEI:
+ bit = 4;
+ case MEP_INSN_BEQI:
+ if (subtype_mappings[fragP->fr_subtype].growth)
+ {
+ fragP->fr_fix += subtype_mappings[fragP->fr_subtype].growth;
+ rn = fragP->fr_opcode[0^e] & 0x0f;
+ fragP->fr_opcode[0^e] = 0xe0 | rn;
+ fragP->fr_opcode[1^e] = bit;
+ }
+ fragP->fr_opcode[2^e] = 0x00 | ((addend >> 9) & 0xff);
+ fragP->fr_opcode[3^e] = 0x00 | ((addend >> 1) & 0xff);
+ operand = MEP_OPERAND_PCREL17A2;
+ break;
+
+ case MEP_INSN_BLTI:
+ case MEP_INSN_BGEI:
+ case MEP_INSN_BCPEQ:
+ case MEP_INSN_BCPNE:
+ case MEP_INSN_BCPAT:
+ case MEP_INSN_BCPAF:
+ /* No opcode change needed, just operand. */
+ fragP->fr_opcode[2^e] = (addend >> 9) & 0xff;
+ fragP->fr_opcode[3^e] = (addend >> 1) & 0xff;
+ operand = MEP_OPERAND_PCREL17A2;
+ break;
+
+ default:
+ abort ();
+ }
+
+ if (S_GET_SEGMENT (fragP->fr_symbol) != sec
+ || operand == MEP_OPERAND_PCABS24A2)
+ {
+ assert (fragP->fr_cgen.insn != 0);
+ gas_cgen_record_fixup (fragP,
+ where,
+ fragP->fr_cgen.insn,
+ (fragP->fr_fix - where) * 8,
+ cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+ operand),
+ fragP->fr_cgen.opinfo,
+ fragP->fr_symbol, fragP->fr_offset);
+ }
+}
+
+\f
+/* Functions concerning relocs. */
+
+void
+mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+ /* If we already know the fixup value, adjust it in the same
+ way that the linker would have done. */
+ if (fixP->fx_addsy == 0)
+ switch (fixP->fx_cgen.opinfo)
+ {
+ case BFD_RELOC_MEP_LOW16:
+ *valP = ((long)(*valP & 0xffff)) << 16 >> 16;
+ break;
+ case BFD_RELOC_MEP_HI16U:
+ *valP >>= 16;
+ break;
+ case BFD_RELOC_MEP_HI16S:
+ *valP = (*valP + 0x8000) >> 16;
+ break;
+ }
+
+ /* Now call cgen's md_aply_fix. */
+ gas_cgen_md_apply_fix (fixP, valP, seg);
+}
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+ if (fixP->fx_addsy != (symbolS *) NULL
+ && (! S_IS_DEFINED (fixP->fx_addsy)
+ || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+ /* The symbol is undefined (or is defined but not in this section).
+ Let the linker figure it out. */
+ return 0;
+
+ /* Return the address of the opcode - cgen adjusts for opcode size
+ itself, to be consistent with the disassembler, which must do
+ so. */
+ return fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
+ Returns BFD_RELOC_NONE if no reloc type can be found.
+ *FIXP may be modified if desired. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define MAP(n) case MEP_OPERAND_##n: return BFD_RELOC_MEP_##n;
+#else
+#define MAP(n) case MEP_OPERAND_/**/n: return BFD_RELOC_MEP_/**/n;
+#endif
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+ const CGEN_OPERAND *operand,
+ fixS *fixP)
+{
+ enum bfd_reloc_code_real reloc = fixP->fx_cgen.opinfo;
+ static char printed[MEP_OPERAND_MAX] = { 0 };
+
+ /* If there's a reloc here, it's because the parser saw a %foo() and
+ is giving us the correct reloc to use, or because we converted to
+ a different size reloc below and want to avoid "converting" more
+ than once. */
+ if (reloc && reloc != BFD_RELOC_NONE)
+ return reloc;
+
+ switch (operand->type)
+ {
+ MAP (PCREL8A2); /* beqz */
+ MAP (PCREL12A2); /* bsr16 */
+ MAP (PCREL17A2); /* beqi */
+ MAP (PCREL24A2); /* bsr24 */
+ MAP (PCABS24A2); /* jmp */
+ MAP (UIMM24); /* mov */
+ MAP (ADDR24A4); /* sw/lw */
+
+ /* The rest of the relocs should be generated by the parser,
+ for things such as %tprel(), etc. */
+ case MEP_OPERAND_SIMM16:
+#ifdef OBJ_COMPLEX_RELC
+ /* coalescing this into RELOC_MEP_16 is actually a bug,
+ since it's a signed operand. let the relc code handle it. */
+ return BFD_RELOC_RELC;
+#endif
+
+ case MEP_OPERAND_UIMM16:
+ case MEP_OPERAND_SDISP16:
+ case MEP_OPERAND_CODE16:
+ fixP->fx_where += 2;
+ /* to avoid doing the above add twice */
+ fixP->fx_cgen.opinfo = BFD_RELOC_MEP_16;
+ return BFD_RELOC_MEP_16;
+
+ default:
+#ifdef OBJ_COMPLEX_RELC
+ /* this is not an error, yet.
+ pass it to the linker. */
+ return BFD_RELOC_RELC;
+#endif
+ if (printed[operand->type])
+ return BFD_RELOC_NONE;
+ printed[operand->type] = 1;
+
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("Don't know how to relocate plain operands of type %s"),
+ operand->name);
+
+ /* Print some helpful hints for the user. */
+ switch (operand->type)
+ {
+ case MEP_OPERAND_UDISP7:
+ case MEP_OPERAND_UDISP7A2:
+ case MEP_OPERAND_UDISP7A4:
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("Perhaps you are missing %%tpoff()?"));
+ break;
+ default:
+ break;
+ }
+ return BFD_RELOC_NONE;
+ }
+}
+
+/* Called while parsing an instruction to create a fixup.
+ We need to check for HI16 relocs and queue them up for later sorting. */
+
+fixS *
+mep_cgen_record_fixup_exp (fragS *frag,
+ int where,
+ const CGEN_INSN *insn,
+ int length,
+ const CGEN_OPERAND *operand,
+ int opinfo,
+ expressionS *exp)
+{
+ fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
+ operand, opinfo, exp);
+ return fixP;
+}
+
+/* Return BFD reloc type from opinfo field in a fixS.
+ It's tricky using fx_r_type in mep_frob_file because the values
+ are BFD_RELOC_UNUSED + operand number. */
+#define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
+
+/* Sort any unmatched HI16 relocs so that they immediately precede
+ the corresponding LO16 reloc. This is called before md_apply_fix and
+ tc_gen_reloc. */
+
+void
+mep_frob_file ()
+{
+ struct mep_hi_fixup * l;
+
+ for (l = mep_hi_fixup_list; l != NULL; l = l->next)
+ {
+ segment_info_type * seginfo;
+ int pass;
+
+ assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_HI16
+ || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_LO16);
+
+ /* Check quickly whether the next fixup happens to be a matching low. */
+ if (l->fixp->fx_next != NULL
+ && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_LO16
+ && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy
+ && l->fixp->fx_offset == l->fixp->fx_next->fx_offset)
+ continue;
+
+ /* Look through the fixups for this segment for a matching
+ `low'. When we find one, move the high just in front of it.
+ We do this in two passes. In the first pass, we try to find
+ a unique `low'. In the second pass, we permit multiple
+ high's relocs for a single `low'. */
+ seginfo = seg_info (l->seg);
+ for (pass = 0; pass < 2; pass++)
+ {
+ fixS * f;
+ fixS * prev;
+
+ prev = NULL;
+ for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
+ {
+ /* Check whether this is a `low' fixup which matches l->fixp. */
+ if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_LO16
+ && f->fx_addsy == l->fixp->fx_addsy
+ && f->fx_offset == l->fixp->fx_offset
+ && (pass == 1
+ || prev == NULL
+ || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_HI16)
+ || prev->fx_addsy != f->fx_addsy
+ || prev->fx_offset != f->fx_offset))
+ {
+ fixS ** pf;
+
+ /* Move l->fixp before f. */
+ for (pf = &seginfo->fix_root;
+ * pf != l->fixp;
+ pf = & (* pf)->fx_next)
+ assert (* pf != NULL);
+
+ * pf = l->fixp->fx_next;
+
+ l->fixp->fx_next = f;
+ if (prev == NULL)
+ seginfo->fix_root = l->fixp;
+ else
+ prev->fx_next = l->fixp;
+
+ break;
+ }
+
+ prev = f;
+ }
+
+ if (f != NULL)
+ break;
+
+ if (pass == 1)
+ as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
+ _("Unmatched high relocation"));
+ }
+ }
+}
+
+/* See whether we need to force a relocation into the output file. */
+
+int
+mep_force_relocation (fixS *fixp)
+{
+ if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+ return 1;
+
+ /* Allow branches to global symbols to be resolved at assembly time.
+ This is consistent with way relaxable branches are handled, since
+ branches to both global and local symbols are relaxed. It also
+ corresponds to the assumptions made in md_pcrel_from_section. */
+ return S_FORCE_RELOC (fixp->fx_addsy, !fixp->fx_pcrel);
+}
+\f
+/* Write a value out to the object file, using the appropriate endianness. */
+
+void
+md_number_to_chars (char *buf, valueT val, int n)
+{
+ if (target_big_endian)
+ number_to_chars_bigendian (buf, val, n);
+ else
+ number_to_chars_littleendian (buf, val, n);
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+ of type type, and store the appropriate bytes in *litP. The number
+ of LITTLENUMS emitted is stored in *sizeP . An error message is
+ returned, or NULL on OK. */
+
+/* Equal to MAX_PRECISION in atof-ieee.c */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+ int i;
+ int prec;
+ LITTLENUM_TYPE words [MAX_LITTLENUMS];
+ char * t;
+
+ switch (type)
+ {
+ case 'f':
+ case 'F':
+ case 's':
+ case 'S':
+ prec = 2;
+ break;
+
+ case 'd':
+ case 'D':
+ case 'r':
+ case 'R':
+ prec = 4;
+ break;
+
+ /* FIXME: Some targets allow other format chars for bigger sizes here. */
+ default:
+ *sizeP = 0;
+ return _("Bad call to md_atof()");
+ }
+
+ t = atof_ieee (input_line_pointer, type, words);
+ if (t)
+ input_line_pointer = t;
+ * sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+ for (i = 0; i < prec; i++)
+ {
+ md_number_to_chars (litP, (valueT) words[i],
+ sizeof (LITTLENUM_TYPE));
+ litP += sizeof (LITTLENUM_TYPE);
+ }
+
+ return 0;
+}
+
+
+bfd_boolean
+mep_fix_adjustable (fixS *fixP)
+{
+ bfd_reloc_code_real_type reloc_type;
+
+ if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+ {
+ const CGEN_INSN *insn = NULL;
+ int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
+ const CGEN_OPERAND *operand
+ = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+ reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+ }
+ else
+ reloc_type = fixP->fx_r_type;
+
+ if (fixP->fx_addsy == NULL)
+ return 1;
+
+ /* Prevent all adjustments to global symbols. */
+ if (S_IS_EXTERNAL (fixP->fx_addsy))
+ return 0;
+
+ if (S_IS_WEAK (fixP->fx_addsy))
+ return 0;
+
+ /* We need the symbol name for the VTABLE entries */
+ if (reloc_type == BFD_RELOC_VTABLE_INHERIT
+ || reloc_type == BFD_RELOC_VTABLE_ENTRY)
+ return 0;
+
+ return 1;
+}
+
+int
+mep_elf_section_letter (int letter, char **ptrmsg)
+{
+ if (letter == 'v')
+ return SHF_MEP_VLIW;
+
+ *ptrmsg = _("Bad .section directive: want a,v,w,x,M,S in string");
+ return 0;
+}
+
+flagword
+mep_elf_section_flags (flagword flags, int attr, int type ATTRIBUTE_UNUSED)
+{
+ if (attr & SHF_MEP_VLIW)
+ flags |= SEC_MEP_VLIW;
+ return flags;
+}
+
+/* In vliw mode, the default section is .vtext. We have to be able
+ to switch into .vtext using only the .vtext directive. */
+
+static segT
+mep_vtext_section (void)
+{
+ static segT vtext_section;
+
+ if (! vtext_section)
+ {
+ flagword applicable = bfd_applicable_section_flags (stdoutput);
+ vtext_section = subseg_new (VTEXT_SECTION_NAME, 0);
+ bfd_set_section_flags (stdoutput, vtext_section,
+ applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC
+ | SEC_CODE | SEC_READONLY
+ | SEC_MEP_VLIW));
+ }
+
+ return vtext_section;
+}
+
+static void
+mep_s_vtext (int ignore ATTRIBUTE_UNUSED)
+{
+ int temp;
+
+ /* Record previous_section and previous_subsection. */
+ obj_elf_section_change_hook ();
+
+ temp = get_absolute_expression ();
+ subseg_set (mep_vtext_section (), (subsegT) temp);
+ demand_empty_rest_of_line ();
+}
+
+static void
+mep_switch_to_core_mode (int dummy ATTRIBUTE_UNUSED)
+{
+ mep_process_saved_insns ();
+ pluspresent = 0;
+ mode = CORE;
+}
+
+static void
+mep_switch_to_vliw_mode (int dummy ATTRIBUTE_UNUSED)
+{
+ if (! MEP_VLIW)
+ as_bad (_(".vliw unavailable when VLIW is disabled."));
+ mode = VLIW;
+ /* Switch into .vtext here too. */
+ /* mep_s_vtext(); */
+}
+
+/* This is an undocumented pseudo-op used to disable gas's
+ "disabled_registers" check. Used for code which checks for those
+ registers at runtime. */
+static void
+mep_noregerr (int i ATTRIBUTE_UNUSED)
+{
+ allow_disabled_registers = 1;
+}
+
+/* mep_unrecognized_line: This is called when a line that can't be parsed
+ is encountered. We use it to check for a leading '+' sign which indicates
+ that the current instruction is a coprocessor instruction that is to be
+ parallelized with a previous core insn. This function accepts the '+' and
+ rejects all other characters that might indicate garbage at the beginning
+ of the line. The '+' character gets lost as the calling loop continues,
+ so we need to indicate that we saw it. */
+
+int
+mep_unrecognized_line (int ch)
+{
+ switch (ch)
+ {
+ case '+':
+ pluspresent = 1;
+ return 1; /* '+' indicates an instruction to be parallelized. */
+ default:
+ return 0; /* If it's not a '+', the line can't be parsed. */
+ }
+}
+
+void
+mep_cleanup (void)
+{
+ /* Take care of any insns left to be parallelized when the file ends.
+ This is mainly here to handle the case where the file ends with an
+ insn preceeded by a + or the file ends unexpectedly. */
+ if (mode == VLIW)
+ mep_process_saved_insns ();
+}
+
+int
+mep_flush_pending_output (void)
+{
+ if (mode == VLIW)
+ {
+ mep_process_saved_insns ();
+ pluspresent = 0;
+ }
+
+ return 1;
+}
--- /dev/null
+/* tc-mep.h -- Header file for tc-mep.c.
+ Copyright (C) 2001, 2002, 2005 Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#define TC_MEP
+
+/* Support computed relocations. */
+#define OBJ_COMPLEX_RELC
+
+/* Support many operands per instruction. */
+#define GAS_CGEN_MAX_FIXUPS 10
+
+#define LISTING_HEADER "MEP GAS "
+
+/* The target BFD architecture. */
+#define TARGET_ARCH bfd_arch_mep
+
+#define TARGET_FORMAT (target_big_endian ? "elf32-mep" : "elf32-mep-little")
+
+/* This is the default. */
+#define TARGET_BYTES_BIG_ENDIAN 1
+
+/* Permit temporary numeric labels. */
+#define LOCAL_LABELS_FB 1
+
+/* .-foo gets turned into PC relative relocs. */
+#define DIFF_EXPR_OK
+
+/* We don't need to handle .word strangely. */
+#define WORKING_DOT_WORD
+
+/* Values passed to md_apply_fix don't include the symbol value. */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define MD_APPLY_FIX
+#define md_apply_fix mep_apply_fix
+extern void mep_apply_fix (struct fix *, valueT *, segT);
+
+/* Call md_pcrel_from_section(), not md_pcrel_from(). */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+#define tc_frob_file() mep_frob_file ()
+extern void mep_frob_file (void);
+
+#define tc_fix_adjustable(fixP) mep_fix_adjustable (fixP)
+extern bfd_boolean mep_fix_adjustable (struct fix *);
+
+/* After creating a fixup for an instruction operand, we need
+ to check for HI16 relocs and queue them up for later sorting. */
+#define md_cgen_record_fixup_exp mep_cgen_record_fixup_exp
+
+/* When relaxing, we need to emit various relocs we otherwise wouldn't. */
+#define TC_FORCE_RELOCATION(fix) mep_force_relocation (fix)
+extern int mep_force_relocation (struct fix *);
+
+#define tc_gen_reloc gas_cgen_tc_gen_reloc
+
+extern void gas_cgen_md_operand (expressionS *);
+#define md_operand(x) gas_cgen_md_operand (x)
+
+#define md_flush_pending_output() mep_flush_pending_output()
+extern int mep_flush_pending_output(void);
+
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+/* Account for inserting a jmp after the insn. */
+#define TC_CGEN_MAX_RELAX(insn, len) ((len) + 4)
+
+extern void mep_prepare_relax_scan (fragS *, offsetT *, relax_substateT);
+#define md_prepare_relax_scan(FRAGP, ADDR, AIM, STATE, TYPE) \
+ mep_prepare_relax_scan (FRAGP, &AIM, STATE)
+
+#define skip_whitespace(str) while (*(str) == ' ') ++(str)
+
+/* Support for core/vliw mode switching. */
+#define CORE 0
+#define VLIW 1
+#define MAX_PARALLEL_INSNS 56 /* From email from Toshiba. */
+#define VTEXT_SECTION_NAME ".vtext"
+
+/* Needed to process pending instructions when a label is encountered. */
+#define TC_START_LABEL(ch, ptr) ((ch == ':') && mep_flush_pending_output ())
+
+#define tc_unrecognized_line(c) mep_unrecognized_line (c)
+extern int mep_unrecognized_line (int);
+#define md_cleanup mep_cleanup
+extern void mep_cleanup (void);
+
+#define md_elf_section_letter mep_elf_section_letter
+extern int mep_elf_section_letter (int, char **);
+#define md_elf_section_flags mep_elf_section_flags
+extern flagword mep_elf_section_flags (flagword, int, int);
+
+#define ELF_TC_SPECIAL_SECTIONS \
+ { VTEXT_SECTION_NAME, SHT_PROGBITS, SHF_ALLOC|SHF_EXECINSTR|SHF_MEP_VLIW },
+
+/* The values of the following enum are for use with parinsnum, which
+ is a variable in md_assemble that keeps track of whether or not the
+ next instruction is expected to be the first or second instrucion in
+ a parallelization group. */
+typedef enum exp_par_insn_{FIRST, SECOND} EXP_PAR_INSN;
esac
;;
+ mep)
+ using_cgen=yes
+ ;;
+
mips)
echo ${extra_objects} | grep -s "itbl-parse.o"
if test $? -ne 0 ; then
esac
;;
+ mep)
+ using_cgen=yes
+ ;;
+
mips)
echo ${extra_objects} | grep -s "itbl-parse.o"
if test $? -ne 0 ; then
m6811|m6812|m68hc12) cpu_type=m68hc11 ;;
m683??) cpu_type=m68k ;;
maxq) cpu_type=maxq ;;
+ mep-*-elf) cpu_type=mep endian=big ;;
mips*el) cpu_type=mips endian=little ;;
mips*) cpu_type=mips endian=big ;;
mt) cpu_type=mt endian=big ;;
maxq-*-coff) fmt=coff bfd_gas=yes ;;
+ mep-*-elf) fmt=elf ;;
+
mcore-*-elf) fmt=elf ;;
mcore-*-pe) fmt=coff em=pe bfd_gas=yes ;;
assert (lastP == symbolP);
}
+#ifdef OBJ_COMPLEX_RELC
+
+static int
+use_complex_relocs_for (symbolS * symp)
+{
+ switch (symp->sy_value.X_op)
+ {
+ case O_constant:
+ return 0;
+
+ case O_symbol:
+ case O_symbol_rva:
+ case O_uminus:
+ case O_bit_not:
+ case O_logical_not:
+ if ( (S_IS_COMMON (symp->sy_value.X_add_symbol)
+ || S_IS_LOCAL (symp->sy_value.X_add_symbol))
+ &&
+ (S_IS_DEFINED (symp->sy_value.X_add_symbol)
+ && S_GET_SEGMENT (symp->sy_value.X_add_symbol) != expr_section))
+ return 0;
+ break;
+
+ case O_multiply:
+ case O_divide:
+ case O_modulus:
+ case O_left_shift:
+ case O_right_shift:
+ case O_bit_inclusive_or:
+ case O_bit_or_not:
+ case O_bit_exclusive_or:
+ case O_bit_and:
+ case O_add:
+ case O_subtract:
+ case O_eq:
+ case O_ne:
+ case O_lt:
+ case O_le:
+ case O_ge:
+ case O_gt:
+ case O_logical_and:
+ case O_logical_or:
+
+ if ( (S_IS_COMMON (symp->sy_value.X_add_symbol)
+ || S_IS_LOCAL (symp->sy_value.X_add_symbol))
+ &&
+ (S_IS_COMMON (symp->sy_value.X_op_symbol)
+ || S_IS_LOCAL (symp->sy_value.X_op_symbol))
+
+ && S_IS_DEFINED (symp->sy_value.X_add_symbol)
+ && S_IS_DEFINED (symp->sy_value.X_op_symbol)
+ && S_GET_SEGMENT (symp->sy_value.X_add_symbol) != expr_section
+ && S_GET_SEGMENT (symp->sy_value.X_op_symbol) != expr_section)
+ return 0;
+ break;
+
+ default:
+ break;
+ }
+ return 1;
+}
+#endif
+
static void
report_op_error (symbolS *symp, symbolS *left, symbolS *right)
{
final_val = 0;
resolved = 1;
}
+#ifdef OBJ_COMPLEX_RELC
+ else if (final_seg == expr_section
+ && use_complex_relocs_for (symp))
+ {
+ symbolS * relc_symbol = NULL;
+ char * relc_symbol_name = NULL;
+
+ relc_symbol_name = symbol_relc_make_expr (& symp->sy_value);
+
+ /* For debugging, print out conversion input & output. */
+#ifdef DEBUG_SYMS
+ print_expr (& symp->sy_value);
+ if (relc_symbol_name)
+ fprintf (stderr, "-> relc symbol: %s\n", relc_symbol_name);
+#endif
+
+ if (relc_symbol_name != NULL)
+ relc_symbol = symbol_new (relc_symbol_name, undefined_section,
+ 0, & zero_address_frag);
+
+ if (relc_symbol == NULL)
+ {
+ as_bad (_("cannot convert expression symbol %s to complex relocation"),
+ S_GET_NAME (symp));
+ resolved = 0;
+ }
+ else
+ {
+ symbol_table_insert (relc_symbol);
+
+ /* S_CLEAR_EXTERNAL (relc_symbol); */
+ if (symp->bsym->flags & BSF_SRELC)
+ relc_symbol->bsym->flags |= BSF_SRELC;
+ else
+ relc_symbol->bsym->flags |= BSF_RELC;
+ /* symp->bsym->flags |= BSF_RELC; */
+ copy_symbol_attributes (symp, relc_symbol);
+ symp->sy_value.X_op = O_symbol;
+ symp->sy_value.X_add_symbol = relc_symbol;
+ symp->sy_value.X_add_number = 0;
+ resolved = 1;
+ }
+
+ final_seg = undefined_section;
+ goto exit_dont_set_value;
+ }
+#endif
else
{
symbolS *add_symbol, *op_symbol;
fprintf (file, "%lu mini local symbols created, %lu converted\n",
local_symbol_count, local_symbol_conversion_count);
}
+
+#ifdef OBJ_COMPLEX_RELC
+
+/* Convert given symbol to a new complex-relocation symbol name. This
+ may bee a recursive function, since it might be called for non-leaf
+ nodes (plain symbols) in the expression tree. The caller owns the
+ returning string, so should free() it eventually. Errors are
+ indicated via as_bad() and a NULL return value. The given symbol
+ is marked with sy_used_in_reloc. */
+
+char *
+symbol_relc_make_sym (symbolS * sym)
+{
+ char * terminal = NULL;
+ const char * sname;
+ char typetag;
+ int sname_len;
+
+ assert (sym != NULL);
+
+ /* Recurse to symbol_relc_make_expr if this symbol
+ is defined as an expression or a plain value. */
+ if ( S_GET_SEGMENT (sym) == expr_section
+ || S_GET_SEGMENT (sym) == absolute_section)
+ return symbol_relc_make_expr (& sym->sy_value);
+
+ /* This may be a "fake symbol" L0\001, referring to ".".
+ Write out a special null symbol to refer to this position. */
+ if (! strcmp (S_GET_NAME (sym), FAKE_LABEL_NAME))
+ return xstrdup (".");
+
+ /* We hope this is a plain leaf symbol. Construct the encoding
+ as {S,s}II...:CCCCCCC....
+ where 'S'/'s' means section symbol / plain symbol
+ III is decimal for the symbol name length
+ CCC is the symbol name itself. */
+ symbol_mark_used_in_reloc (sym);
+
+ sname = S_GET_NAME (sym);
+ sname_len = strlen (sname);
+ typetag = symbol_section_p (sym) ? 'S' : 's';
+
+ terminal = xmalloc (1 /* S or s */
+ + 8 /* sname_len in decimal */
+ + 1 /* _ spacer */
+ + sname_len /* name itself */
+ + 1 /* \0 */ );
+
+ sprintf (terminal, "%c%d:%s", typetag, sname_len, sname);
+ return terminal;
+}
+
+/* Convert given value to a new complex-relocation symbol name. This
+ is a non-recursive function, since it is be called for leaf nodes
+ (plain values) in the expression tree. The caller owns the
+ returning string, so should free() it eventually. No errors. */
+
+char *
+symbol_relc_make_value (offsetT val)
+{
+ char * terminal = xmalloc (28); /* Enough for long long. */
+
+ terminal[0] = '#';
+ sprintf_vma (& terminal[1], val);
+ return terminal;
+}
+
+/* Convert given expression to a new complex-relocation symbol name.
+ This is a recursive function, since it traverses the entire given
+ expression tree. The caller owns the returning string, so should
+ free() it eventually. Errors are indicated via as_bad() and a NULL
+ return value. */
+
+char *
+symbol_relc_make_expr (expressionS * exp)
+{
+ char * opstr = NULL; /* Operator prefix string. */
+ int arity = 0; /* Arity of this operator. */
+ char * operands[3]; /* Up to three operands. */
+ char * concat_string = NULL;
+
+ operands[0] = operands[1] = operands[2] = NULL;
+
+ assert (exp != NULL);
+
+ /* Match known operators -> fill in opstr, arity, operands[] and fall
+ through to construct subexpression fragments; may instead return
+ string directly for leaf nodes. */
+
+ /* See expr.h for the meaning of all these enums. Many operators
+ have an unnatural arity (X_add_number implicitly added). The
+ conversion logic expands them to explicit "+" subexpressions. */
+
+ switch (exp->X_op)
+ {
+ default:
+ as_bad ("Unknown expression operator (enum %d)", exp->X_op);
+ break;
+
+ /* Leaf nodes. */
+ case O_constant:
+ return symbol_relc_make_value (exp->X_add_number);
+
+ case O_symbol:
+ if (exp->X_add_number)
+ {
+ arity = 2;
+ opstr = "+";
+ operands[0] = symbol_relc_make_sym (exp->X_add_symbol);
+ operands[1] = symbol_relc_make_value (exp->X_add_number);
+ break;
+ }
+ else
+ return symbol_relc_make_sym (exp->X_add_symbol);
+
+ /* Helper macros for nesting nodes. */
+
+#define HANDLE_XADD_OPT1(str_) \
+ if (exp->X_add_number) \
+ { \
+ arity = 2; \
+ opstr = "+:" str_; \
+ operands[0] = symbol_relc_make_sym (exp->X_add_symbol); \
+ operands[1] = symbol_relc_make_value (exp->X_add_number); \
+ break; \
+ } \
+ else \
+ { \
+ arity = 1; \
+ opstr = str_; \
+ operands[0] = symbol_relc_make_sym (exp->X_add_symbol); \
+ } \
+ break
+
+#define HANDLE_XADD_OPT2(str_) \
+ if (exp->X_add_number) \
+ { \
+ arity = 3; \
+ opstr = "+:" str_; \
+ operands[0] = symbol_relc_make_sym (exp->X_add_symbol); \
+ operands[1] = symbol_relc_make_sym (exp->X_op_symbol); \
+ operands[2] = symbol_relc_make_value (exp->X_add_number); \
+ } \
+ else \
+ { \
+ arity = 2; \
+ opstr = str_; \
+ operands[0] = symbol_relc_make_sym (exp->X_add_symbol); \
+ operands[1] = symbol_relc_make_sym (exp->X_op_symbol); \
+ } \
+ break
+
+ /* Nesting nodes. */
+
+ case O_uminus: HANDLE_XADD_OPT1 ("0-");
+ case O_bit_not: HANDLE_XADD_OPT1 ("~");
+ case O_logical_not: HANDLE_XADD_OPT1 ("!");
+ case O_multiply: HANDLE_XADD_OPT2 ("*");
+ case O_divide: HANDLE_XADD_OPT2 ("/");
+ case O_modulus: HANDLE_XADD_OPT2 ("%");
+ case O_left_shift: HANDLE_XADD_OPT2 ("<<");
+ case O_right_shift: HANDLE_XADD_OPT2 (">>");
+ case O_bit_inclusive_or: HANDLE_XADD_OPT2 ("|");
+ case O_bit_exclusive_or: HANDLE_XADD_OPT2 ("^");
+ case O_bit_and: HANDLE_XADD_OPT2 ("&");
+ case O_add: HANDLE_XADD_OPT2 ("+");
+ case O_subtract: HANDLE_XADD_OPT2 ("-");
+ case O_eq: HANDLE_XADD_OPT2 ("==");
+ case O_ne: HANDLE_XADD_OPT2 ("!=");
+ case O_lt: HANDLE_XADD_OPT2 ("<");
+ case O_le: HANDLE_XADD_OPT2 ("<=");
+ case O_ge: HANDLE_XADD_OPT2 (">=");
+ case O_gt: HANDLE_XADD_OPT2 (">");
+ case O_logical_and: HANDLE_XADD_OPT2 ("&&");
+ case O_logical_or: HANDLE_XADD_OPT2 ("||");
+ }
+
+ /* Validate & reject early. */
+ if (arity >= 1 && ((operands[0] == NULL) || (strlen (operands[0]) == 0)))
+ opstr = NULL;
+ if (arity >= 2 && ((operands[1] == NULL) || (strlen (operands[1]) == 0)))
+ opstr = NULL;
+ if (arity >= 3 && ((operands[2] == NULL) || (strlen (operands[2]) == 0)))
+ opstr = NULL;
+
+ if (opstr == NULL)
+ concat_string = NULL;
+ else
+ {
+ /* Allocate new string; include inter-operand padding gaps etc. */
+ concat_string = xmalloc (strlen (opstr)
+ + 1
+ + (arity >= 1 ? (strlen (operands[0]) + 1 ) : 0)
+ + (arity >= 2 ? (strlen (operands[1]) + 1 ) : 0)
+ + (arity >= 3 ? (strlen (operands[2]) + 0 ) : 0)
+ + 1);
+ assert (concat_string != NULL);
+
+ /* Format the thing. */
+ sprintf (concat_string,
+ (arity == 0 ? "%s" :
+ arity == 1 ? "%s:%s" :
+ arity == 2 ? "%s:%s:%s" :
+ /* arity == 3 */ "%s:%s:%s:%s"),
+ opstr, operands[0], operands[1], operands[2]);
+ }
+
+ /* Free operand strings (not opstr). */
+ if (arity >= 1) xfree (operands[0]);
+ if (arity >= 2) xfree (operands[1]);
+ if (arity >= 3) xfree (operands[2]);
+
+ return concat_string;
+}
+
+#endif
default. */
extern int symbols_case_sensitive;
+char * symbol_relc_make_expr (expressionS *);
+char * symbol_relc_make_sym (symbolS *);
+char * symbol_relc_make_value (offsetT);
char *decode_local_label_name (char *s);
symbolS *symbol_find (const char *name);
symbolS *symbol_find_noref (const char *name, int noref);
+2007-02-05 Dave Brolley <brolley@redhat.com>
+
+ * gas/mep/relocs-junk1.s: Add a .data section.
+ * gas/mep/relocs.d: Updated to match above.
+
2007-02-04 H.J. Lu <hongjiu.lu@intel.com>
PR gas/3961
# The ".space" directive is taken care of in the C54x-specific tests, so fail
# here
#
-if { [istarget hppa*-*-*] || [istarget *c54x*-*-*] } then {
+# The test also doesn't work on mep targets, since they use RELC, and it
+# will avoid simplifying the expression since it conservatively assumes
+# ugly expressions can be saved until link-time.
+if { [istarget hppa*-*-*] || [istarget *c54x*-*-*] || [istarget mep*-*-*]} then {
setup_xfail *-*-*
fail "simplifiable double subtraction"
} else {
--- /dev/null
+#as:
+#objdump: -dr
+#name: allinsn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <sb>:
+ 0: 07 88 sb \$7,\(\$8\)
+ 2: 05 98 sb \$5,\(\$9\)
+ 4: 07 e8 sb \$7,\(\$gp\)
+ 6: 0e 88 sb \$gp,\(\$8\)
+ 8: 0f e8 sb \$sp,\(\$gp\)
+
+0000000a <sh>:
+ a: 03 89 sh \$3,\(\$8\)
+ c: 0c 19 sh \$12,\(\$1\)
+ e: 0d 29 sh \$tp,\(\$2\)
+ 10: 02 89 sh \$2,\(\$8\)
+ 12: 0c a9 sh \$12,\(\$10\)
+
+00000014 <sw>:
+ 14: 0b 0a sw \$11,\(\$0\)
+ 16: 03 7a sw \$3,\(\$7\)
+ 18: 0d ea sw \$tp,\(\$gp\)
+ 1a: 08 9a sw \$8,\(\$9\)
+ 1c: 0e 8a sw \$gp,\(\$8\)
+
+0000001e <lb>:
+ 1e: 0c bc lb \$12,\(\$11\)
+ 20: 09 2c lb \$9,\(\$2\)
+ 22: 08 bc lb \$8,\(\$11\)
+ 24: 0e 2c lb \$gp,\(\$2\)
+ 26: 02 cc lb \$2,\(\$12\)
+
+00000028 <lh>:
+ 28: 0f 8d lh \$sp,\(\$8\)
+ 2a: 03 ad lh \$3,\(\$10\)
+ 2c: 09 fd lh \$9,\(\$sp\)
+ 2e: 06 fd lh \$6,\(\$sp\)
+ 30: 0f bd lh \$sp,\(\$11\)
+
+00000032 <lw>:
+ 32: 0c ae lw \$12,\(\$10\)
+ 34: 09 de lw \$9,\(\$tp\)
+ 36: 0c ee lw \$12,\(\$gp\)
+ 38: 0c be lw \$12,\(\$11\)
+ 3a: 0d ae lw \$tp,\(\$10\)
+
+0000003c <lbu>:
+ 3c: 0e eb lbu \$gp,\(\$gp\)
+ 3e: 0c 8b lbu \$12,\(\$8\)
+ 40: 0e 1b lbu \$gp,\(\$1\)
+ 42: 08 cb lbu \$8,\(\$12\)
+ 44: 0c 1b lbu \$12,\(\$1\)
+
+00000046 <lhu>:
+ 46: 0f 4f lhu \$sp,\(\$4\)
+ 48: 0e 4f lhu \$gp,\(\$4\)
+ 4a: 05 4f lhu \$5,\(\$4\)
+ 4c: 0f df lhu \$sp,\(\$tp\)
+ 4e: 04 ff lhu \$4,\(\$sp\)
+
+00000050 <sw_sp>:
+ 50: c9 8a 00 03 sw \$9,3\(\$8\)
+ 54: ca 5a 00 04 sw \$10,4\(\$5\)
+ 58: c0 ea 00 03 sw \$0,3\(\$gp\)
+ 5c: c0 8a 00 02 sw \$0,2\(\$8\)
+ 60: cf 8a 00 01 sw \$sp,1\(\$8\)
+
+00000064 <lw_sp>:
+ 64: cd 5e 00 01 lw \$tp,1\(\$5\)
+ 68: cf 0e 00 01 lw \$sp,1\(\$0\)
+ 6c: c0 ce 00 04 lw \$0,4\(\$12\)
+ 70: cb de 00 01 lw \$11,1\(\$tp\)
+ 74: c9 4e 00 03 lw \$9,3\(\$4\)
+
+00000078 <sb_tp>:
+ 78: c5 18 00 01 sb \$5,1\(\$1\)
+ 7c: ca 98 00 01 sb \$10,1\(\$9\)
+ 80: c5 38 00 03 sb \$5,3\(\$3\)
+ 84: c5 38 00 01 sb \$5,1\(\$3\)
+ 88: ca 48 00 04 sb \$10,4\(\$4\)
+
+0000008c <sh_tp>:
+ 8c: c3 09 00 01 sh \$3,1\(\$0\)
+ 90: cd 99 00 01 sh \$tp,1\(\$9\)
+ 94: c9 a9 00 04 sh \$9,4\(\$10\)
+ 98: cf e9 00 03 sh \$sp,3\(\$gp\)
+ 9c: ce 99 00 04 sh \$gp,4\(\$9\)
+
+000000a0 <sw_tp>:
+ a0: c6 da 00 02 sw \$6,2\(\$tp\)
+ a4: c6 fa 00 01 sw \$6,1\(\$sp\)
+ a8: c2 3a 00 02 sw \$2,2\(\$3\)
+ ac: c6 ca 00 02 sw \$6,2\(\$12\)
+ b0: c3 ba 00 01 sw \$3,1\(\$11\)
+
+000000b4 <lb_tp>:
+ b4: cd bc 00 04 lb \$tp,4\(\$11\)
+ b8: cd 8c 00 04 lb \$tp,4\(\$8\)
+ bc: c5 5c 00 04 lb \$5,4\(\$5\)
+ c0: cf ec 00 02 lb \$sp,2\(\$gp\)
+ c4: c3 3c 00 02 lb \$3,2\(\$3\)
+
+000000c8 <lh_tp>:
+ c8: c7 8d 00 02 lh \$7,2\(\$8\)
+ cc: c4 8d 00 03 lh \$4,3\(\$8\)
+ d0: ce fd 00 01 lh \$gp,1\(\$sp\)
+ d4: c9 0d 00 01 lh \$9,1\(\$0\)
+ d8: cd 0d 00 02 lh \$tp,2\(\$0\)
+
+000000dc <lw_tp>:
+ dc: 48 07 lw \$8,0x4\(\$sp\)
+ de: cb 9e 00 04 lw \$11,4\(\$9\)
+ e2: ce 2e 00 01 lw \$gp,1\(\$2\)
+ e6: c9 ee 00 02 lw \$9,2\(\$gp\)
+ ea: c8 ce 00 01 lw \$8,1\(\$12\)
+
+000000ee <lbu_tp>:
+ ee: cc 9b 00 01 lbu \$12,1\(\$9\)
+ f2: cb 9b 00 01 lbu \$11,1\(\$9\)
+ f6: ce 8b 00 03 lbu \$gp,3\(\$8\)
+ fa: c0 fb 00 02 lbu \$0,2\(\$sp\)
+ fe: cd bb 00 01 lbu \$tp,1\(\$11\)
+
+00000102 <lhu_tp>:
+ 102: ce af 00 02 lhu \$gp,2\(\$10\)
+ 106: cb 8f 00 01 lhu \$11,1\(\$8\)
+ 10a: c1 0f 00 01 lhu \$1,1\(\$0\)
+ 10e: c7 ff 00 02 lhu \$7,2\(\$sp\)
+ 112: 8b 83 lhu \$3,0x2\(\$tp\)
+
+00000114 <sb16>:
+ 114: c7 b8 ff ff sb \$7,-1\(\$11\)
+ 118: cd e8 00 01 sb \$tp,1\(\$gp\)
+ 11c: c3 e8 00 01 sb \$3,1\(\$gp\)
+ 120: ce 68 00 02 sb \$gp,2\(\$6\)
+ 124: ce 78 00 01 sb \$gp,1\(\$7\)
+
+00000128 <sh16>:
+ 128: cc 49 ff ff sh \$12,-1\(\$4\)
+ 12c: cf 19 00 01 sh \$sp,1\(\$1\)
+ 130: c2 c9 ff fe sh \$2,-2\(\$12\)
+ 134: c9 b9 00 02 sh \$9,2\(\$11\)
+ 138: c9 c9 ff fe sh \$9,-2\(\$12\)
+
+0000013c <sw16>:
+ 13c: cb ea ff ff sw \$11,-1\(\$gp\)
+ 140: 44 06 sw \$4,0x4\(\$sp\)
+ 142: c2 3a ff fe sw \$2,-2\(\$3\)
+ 146: c6 2a ff ff sw \$6,-1\(\$2\)
+ 14a: c8 da ff fe sw \$8,-2\(\$tp\)
+
+0000014e <lb16>:
+ 14e: ca 2c ff fe lb \$10,-2\(\$2\)
+ 152: c3 bc ff fe lb \$3,-2\(\$11\)
+ 156: cc 5c 00 01 lb \$12,1\(\$5\)
+ 15a: c5 5c 00 01 lb \$5,1\(\$5\)
+ 15e: cb dc 00 02 lb \$11,2\(\$tp\)
+
+00000162 <lh16>:
+ 162: cf bd ff ff lh \$sp,-1\(\$11\)
+ 166: cd bd ff fe lh \$tp,-2\(\$11\)
+ 16a: c2 ad 00 01 lh \$2,1\(\$10\)
+ 16e: c8 7d ff ff lh \$8,-1\(\$7\)
+ 172: ce bd ff ff lh \$gp,-1\(\$11\)
+
+00000176 <lw16>:
+ 176: c0 5e ff ff lw \$0,-1\(\$5\)
+ 17a: cc 7e ff fe lw \$12,-2\(\$7\)
+ 17e: c1 3e ff fe lw \$1,-2\(\$3\)
+ 182: c1 7e 00 02 lw \$1,2\(\$7\)
+ 186: c4 8e 00 01 lw \$4,1\(\$8\)
+
+0000018a <lbu16>:
+ 18a: cc 4b ff ff lbu \$12,-1\(\$4\)
+ 18e: ce bb 00 01 lbu \$gp,1\(\$11\)
+ 192: c1 db ff ff lbu \$1,-1\(\$tp\)
+ 196: c9 db ff ff lbu \$9,-1\(\$tp\)
+ 19a: c8 fb 00 01 lbu \$8,1\(\$sp\)
+
+0000019e <lhu16>:
+ 19e: cd ff ff ff lhu \$tp,-1\(\$sp\)
+ 1a2: ce 8f 00 02 lhu \$gp,2\(\$8\)
+ 1a6: cf cf ff ff lhu \$sp,-1\(\$12\)
+ 1aa: c3 0f ff ff lhu \$3,-1\(\$0\)
+ 1ae: c3 cf ff fe lhu \$3,-2\(\$12\)
+
+000001b2 <sw24>:
+ 1b2: eb 06 00 00 sw \$11,\(0x4\)
+ 1b6: ef 06 00 00 sw \$sp,\(0x4\)
+ 1ba: e7 0a 00 00 sw \$7,\(0x8\)
+ 1be: ea 12 00 00 sw \$10,\(0x10\)
+ 1c2: e8 a2 00 00 sw \$8,\(0xa0\)
+
+000001c6 <lw24>:
+ 1c6: e4 07 00 00 lw \$4,\(0x4\)
+ 1ca: ef 07 00 00 lw \$sp,\(0x4\)
+ 1ce: e4 13 00 00 lw \$4,\(0x10\)
+ 1d2: e8 03 00 00 lw \$8,\(0x0\)
+ 1d6: ed 0b 00 00 lw \$tp,\(0x8\)
+
+000001da <extb>:
+ 1da: 1d 0d extb \$tp
+ 1dc: 1d 0d extb \$tp
+ 1de: 16 0d extb \$6
+ 1e0: 1e 0d extb \$gp
+ 1e2: 1a 0d extb \$10
+
+000001e4 <exth>:
+ 1e4: 1f 2d exth \$sp
+ 1e6: 12 2d exth \$2
+ 1e8: 15 2d exth \$5
+ 1ea: 1a 2d exth \$10
+ 1ec: 14 2d exth \$4
+
+000001ee <extub>:
+ 1ee: 12 8d extub \$2
+ 1f0: 1d 8d extub \$tp
+ 1f2: 13 8d extub \$3
+ 1f4: 19 8d extub \$9
+ 1f6: 1e 8d extub \$gp
+
+000001f8 <extuh>:
+ 1f8: 18 ad extuh \$8
+ 1fa: 18 ad extuh \$8
+ 1fc: 14 ad extuh \$4
+ 1fe: 10 ad extuh \$0
+ 200: 10 ad extuh \$0
+
+00000202 <ssarb>:
+ 202: 12 8c ssarb 2\(\$8\)
+ 204: 12 dc ssarb 2\(\$tp\)
+ 206: 11 dc ssarb 1\(\$tp\)
+ 208: 12 5c ssarb 2\(\$5\)
+ 20a: 10 9c ssarb 0\(\$9\)
+
+0000020c <mov>:
+ 20c: 02 30 mov \$2,\$3
+ 20e: 03 b0 mov \$3,\$11
+ 210: 0f a0 mov \$sp,\$10
+ 212: 0f 00 mov \$sp,\$0
+ 214: 03 d0 mov \$3,\$tp
+
+00000216 <movi8>:
+ 216: 5b ff mov \$11,-1
+ 218: 56 02 mov \$6,2
+ 21a: 5f ff mov \$sp,-1
+ 21c: 5f 01 mov \$sp,1
+ 21e: 5e ff mov \$gp,-1
+
+00000220 <movi16>:
+ 220: 5f 00 mov \$sp,0
+ 222: 50 02 mov \$0,2
+ 224: 58 ff mov \$8,-1
+ 226: 5c 01 mov \$12,1
+ 228: 57 ff mov \$7,-1
+
+0000022a <movu24>:
+ 22a: d2 01 00 00 movu \$2,0x1
+ 22e: ca 11 00 04 movu \$10,0x4
+ 232: c9 11 00 00 movu \$9,0x0
+ 236: d4 03 00 00 movu \$4,0x3
+ 23a: ce 11 00 01 movu \$gp,0x1
+
+0000023e <movu16>:
+ 23e: cf 11 00 01 movu \$sp,0x1
+ 242: d6 03 00 00 movu \$6,0x3
+ 246: d0 03 00 00 movu \$0,0x3
+ 24a: ce 11 00 03 movu \$gp,0x3
+ 24e: ca 11 00 02 movu \$10,0x2
+
+00000252 <movh>:
+ 252: c8 21 00 02 movh \$8,0x2
+ 256: cd 21 00 01 movh \$tp,0x1
+ 25a: ce 21 00 02 movh \$gp,0x2
+ 25e: cc 21 00 00 movh \$12,0x0
+ 262: cb 21 00 02 movh \$11,0x2
+
+00000266 <add3>:
+ 266: 9b 36 add3 \$6,\$11,\$3
+ 268: 9d 5e add3 \$gp,\$tp,\$5
+ 26a: 9b 73 add3 \$3,\$11,\$7
+ 26c: 9e dd add3 \$tp,\$gp,\$tp
+ 26e: 9e 80 add3 \$0,\$gp,\$8
+
+00000270 <add>:
+ 270: 6c 08 add \$12,2
+ 272: 6c fc add \$12,-1
+ 274: 64 04 add \$4,1
+ 276: 66 04 add \$6,1
+ 278: 66 08 add \$6,2
+
+0000027a <add3i>:
+ 27a: 4b 04 add3 \$11,\$sp,0x4
+ 27c: c4 f0 00 01 add3 \$4,\$sp,1
+ 280: 40 00 add3 \$0,\$sp,0x0
+ 282: cd f0 00 03 add3 \$tp,\$sp,3
+ 286: 4b 00 add3 \$11,\$sp,0x0
+
+00000288 <advck3>:
+ 288: 0e a7 advck3 \$0,\$gp,\$10
+ 28a: 0d 07 advck3 \$0,\$tp,\$0
+ 28c: 0e d7 advck3 \$0,\$gp,\$tp
+ 28e: 07 87 advck3 \$0,\$7,\$8
+ 290: 01 27 advck3 \$0,\$1,\$2
+
+00000292 <sub>:
+ 292: 08 e4 sub \$8,\$gp
+ 294: 01 94 sub \$1,\$9
+ 296: 0d 74 sub \$tp,\$7
+ 298: 0f 34 sub \$sp,\$3
+ 29a: 02 74 sub \$2,\$7
+
+0000029c <sbvck3>:
+ 29c: 03 e5 sbvck3 \$0,\$3,\$gp
+ 29e: 03 75 sbvck3 \$0,\$3,\$7
+ 2a0: 0a a5 sbvck3 \$0,\$10,\$10
+ 2a2: 04 d5 sbvck3 \$0,\$4,\$tp
+ 2a4: 0a f5 sbvck3 \$0,\$10,\$sp
+
+000002a6 <neg>:
+ 2a6: 0e 71 neg \$gp,\$7
+ 2a8: 01 71 neg \$1,\$7
+ 2aa: 02 b1 neg \$2,\$11
+ 2ac: 0d 81 neg \$tp,\$8
+ 2ae: 0e d1 neg \$gp,\$tp
+
+000002b0 <slt3>:
+ 2b0: 0e 82 slt3 \$0,\$gp,\$8
+ 2b2: 04 d2 slt3 \$0,\$4,\$tp
+ 2b4: 0a e2 slt3 \$0,\$10,\$gp
+ 2b6: 0e 52 slt3 \$0,\$gp,\$5
+ 2b8: 03 c2 slt3 \$0,\$3,\$12
+
+000002ba <sltu3>:
+ 2ba: 02 83 sltu3 \$0,\$2,\$8
+ 2bc: 0e b3 sltu3 \$0,\$gp,\$11
+ 2be: 02 d3 sltu3 \$0,\$2,\$tp
+ 2c0: 09 83 sltu3 \$0,\$9,\$8
+ 2c2: 06 93 sltu3 \$0,\$6,\$9
+
+000002c4 <slt3i>:
+ 2c4: 66 11 slt3 \$0,\$6,0x2
+ 2c6: 6b 09 slt3 \$0,\$11,0x1
+ 2c8: 6f 01 slt3 \$0,\$sp,0x0
+ 2ca: 63 01 slt3 \$0,\$3,0x0
+ 2cc: 6d 01 slt3 \$0,\$tp,0x0
+
+000002ce <sltu3i>:
+ 2ce: 6e 25 sltu3 \$0,\$gp,0x4
+ 2d0: 6d 1d sltu3 \$0,\$tp,0x3
+ 2d2: 63 0d sltu3 \$0,\$3,0x1
+ 2d4: 6c 05 sltu3 \$0,\$12,0x0
+ 2d6: 61 1d sltu3 \$0,\$1,0x3
+
+000002d8 <sl1ad3>:
+ 2d8: 28 e6 sl1ad3 \$0,\$8,\$gp
+ 2da: 24 26 sl1ad3 \$0,\$4,\$2
+ 2dc: 2f c6 sl1ad3 \$0,\$sp,\$12
+ 2de: 29 16 sl1ad3 \$0,\$9,\$1
+ 2e0: 28 26 sl1ad3 \$0,\$8,\$2
+
+000002e2 <sl2ad3>:
+ 2e2: 28 d7 sl2ad3 \$0,\$8,\$tp
+ 2e4: 22 37 sl2ad3 \$0,\$2,\$3
+ 2e6: 28 97 sl2ad3 \$0,\$8,\$9
+ 2e8: 27 c7 sl2ad3 \$0,\$7,\$12
+ 2ea: 24 c7 sl2ad3 \$0,\$4,\$12
+
+000002ec <add3x>:
+ 2ec: cd b0 00 01 add3 \$tp,\$11,1
+ 2f0: cd 40 ff ff add3 \$tp,\$4,-1
+ 2f4: c2 d0 00 01 add3 \$2,\$tp,1
+ 2f8: c3 e0 00 01 add3 \$3,\$gp,1
+ 2fc: ca f0 00 02 add3 \$10,\$sp,2
+
+00000300 <slt3x>:
+ 300: c8 12 ff ff slt3 \$8,\$1,-1
+ 304: c0 32 ff fe slt3 \$0,\$3,-2
+ 308: c9 f2 ff ff slt3 \$9,\$sp,-1
+ 30c: c3 82 00 02 slt3 \$3,\$8,2
+ 310: cd e2 00 00 slt3 \$tp,\$gp,0
+
+00000314 <sltu3x>:
+ 314: cf b3 00 02 sltu3 \$sp,\$11,0x2
+ 318: c6 03 00 01 sltu3 \$6,\$0,0x1
+ 31c: c9 b3 00 03 sltu3 \$9,\$11,0x3
+ 320: 64 05 sltu3 \$0,\$4,0x0
+ 322: cd e3 00 04 sltu3 \$tp,\$gp,0x4
+
+00000326 <or>:
+ 326: 1f e0 or \$sp,\$gp
+ 328: 18 30 or \$8,\$3
+ 32a: 10 f0 or \$0,\$sp
+ 32c: 1d 00 or \$tp,\$0
+ 32e: 18 60 or \$8,\$6
+
+00000330 <and>:
+ 330: 1f f1 and \$sp,\$sp
+ 332: 16 e1 and \$6,\$gp
+ 334: 14 21 and \$4,\$2
+ 336: 15 81 and \$5,\$8
+ 338: 17 e1 and \$7,\$gp
+
+0000033a <xor>:
+ 33a: 11 c2 xor \$1,\$12
+ 33c: 1c d2 xor \$12,\$tp
+ 33e: 1a 82 xor \$10,\$8
+ 340: 1f b2 xor \$sp,\$11
+ 342: 1c 82 xor \$12,\$8
+
+00000344 <nor>:
+ 344: 19 53 nor \$9,\$5
+ 346: 18 23 nor \$8,\$2
+ 348: 1f 93 nor \$sp,\$9
+ 34a: 15 f3 nor \$5,\$sp
+ 34c: 1f e3 nor \$sp,\$gp
+
+0000034e <or3>:
+ 34e: cd f4 00 02 or3 \$tp,\$sp,0x2
+ 352: cf d4 00 03 or3 \$sp,\$tp,0x3
+ 356: c0 a4 00 04 or3 \$0,\$10,0x4
+ 35a: c9 f4 00 03 or3 \$9,\$sp,0x3
+ 35e: c9 f4 00 00 or3 \$9,\$sp,0x0
+
+00000362 <and3>:
+ 362: c5 85 00 01 and3 \$5,\$8,0x1
+ 366: cb e5 00 03 and3 \$11,\$gp,0x3
+ 36a: c6 05 00 00 and3 \$6,\$0,0x0
+ 36e: cf f5 00 00 and3 \$sp,\$sp,0x0
+ 372: c1 a5 00 03 and3 \$1,\$10,0x3
+
+00000376 <xor3>:
+ 376: c0 06 00 02 xor3 \$0,\$0,0x2
+ 37a: cf 66 00 00 xor3 \$sp,\$6,0x0
+ 37e: cd 56 00 00 xor3 \$tp,\$5,0x0
+ 382: cf 76 00 00 xor3 \$sp,\$7,0x0
+ 386: cf f6 00 02 xor3 \$sp,\$sp,0x2
+
+0000038a <sra>:
+ 38a: 24 1d sra \$4,\$1
+ 38c: 28 fd sra \$8,\$sp
+ 38e: 21 1d sra \$1,\$1
+ 390: 20 5d sra \$0,\$5
+ 392: 29 1d sra \$9,\$1
+
+00000394 <srl>:
+ 394: 22 bc srl \$2,\$11
+ 396: 2f 7c srl \$sp,\$7
+ 398: 21 7c srl \$1,\$7
+ 39a: 23 dc srl \$3,\$tp
+ 39c: 2e 1c srl \$gp,\$1
+
+0000039e <sll>:
+ 39e: 2b 0e sll \$11,\$0
+ 3a0: 2d 8e sll \$tp,\$8
+ 3a2: 28 9e sll \$8,\$9
+ 3a4: 2d fe sll \$tp,\$sp
+ 3a6: 2f fe sll \$sp,\$sp
+
+000003a8 <srai>:
+ 3a8: 61 13 sra \$1,0x2
+ 3aa: 6f 1b sra \$sp,0x3
+ 3ac: 6f 1b sra \$sp,0x3
+ 3ae: 66 23 sra \$6,0x4
+ 3b0: 6f 1b sra \$sp,0x3
+
+000003b2 <srli>:
+ 3b2: 6a 02 srl \$10,0x0
+ 3b4: 69 1a srl \$9,0x3
+ 3b6: 66 22 srl \$6,0x4
+ 3b8: 6a 12 srl \$10,0x2
+ 3ba: 68 1a srl \$8,0x3
+
+000003bc <slli>:
+ 3bc: 60 06 sll \$0,0x0
+ 3be: 64 06 sll \$4,0x0
+ 3c0: 6d 16 sll \$tp,0x2
+ 3c2: 6b 16 sll \$11,0x2
+ 3c4: 66 06 sll \$6,0x0
+
+000003c6 <sll3>:
+ 3c6: 6d 27 sll3 \$0,\$tp,0x4
+ 3c8: 6e 07 sll3 \$0,\$gp,0x0
+ 3ca: 68 17 sll3 \$0,\$8,0x2
+ 3cc: 63 17 sll3 \$0,\$3,0x2
+ 3ce: 68 07 sll3 \$0,\$8,0x0
+
+000003d0 <fsft>:
+ 3d0: 2e af fsft \$gp,\$10
+ 3d2: 2e 9f fsft \$gp,\$9
+ 3d4: 2f df fsft \$sp,\$tp
+ 3d6: 2b 3f fsft \$11,\$3
+ 3d8: 25 3f fsft \$5,\$3
+
+000003da <bra>:
+ 3da: b0 02 bra 3dc <bra\+0x2>
+ 3dc: bf fe bra 3da <bra>
+ 3de: b0 02 bra 3e0 <bra\+0x6>
+ 3e0: b0 00 bra 3e0 <bra\+0x6>
+ 3e2: b0 02 bra 3e4 <beqz>
+
+000003e4 <beqz>:
+ 3e4: a1 fe beqz \$1,3e2 <bra\+0x8>
+ 3e6: af 02 beqz \$sp,3e8 <beqz\+0x4>
+ 3e8: a4 04 beqz \$4,3ec <beqz\+0x8>
+ 3ea: a4 00 beqz \$4,3ea <beqz\+0x6>
+ 3ec: a9 fe beqz \$9,3ea <beqz\+0x6>
+
+000003ee <bnez>:
+ 3ee: a8 03 bnez \$8,3f0 <bnez\+0x2>
+ 3f0: ad 03 bnez \$tp,3f2 <bnez\+0x4>
+ 3f2: ae 01 bnez \$gp,3f2 <bnez\+0x4>
+ 3f4: a6 03 bnez \$6,3f6 <bnez\+0x8>
+ 3f6: a8 fd bnez \$8,3f2 <bnez\+0x4>
+
+000003f8 <beqi>:
+ 3f8: ed 30 00 00 beqi \$tp,0x3,3f8 <beqi>
+ 3fc: e0 40 ff ff beqi \$0,0x4,3fa <beqi\+0x2>
+ 400: ef 40 ff ff beqi \$sp,0x4,3fe <beqi\+0x6>
+ 404: ed 20 00 00 beqi \$tp,0x2,404 <beqi\+0xc>
+ 408: e4 20 ff fc beqi \$4,0x2,400 <beqi\+0x8>
+
+0000040c <bnei>:
+ 40c: e8 14 00 00 bnei \$8,0x1,40c <bnei>
+ 410: e5 14 00 01 bnei \$5,0x1,412 <bnei\+0x6>
+ 414: e5 04 00 04 bnei \$5,0x0,41c <bnei\+0x10>
+ 418: e9 44 ff ff bnei \$9,0x4,416 <bnei\+0xa>
+ 41c: e0 44 ff fc bnei \$0,0x4,414 <bnei\+0x8>
+
+00000420 <blti>:
+ 420: e7 3c 00 00 blti \$7,0x3,420 <blti>
+ 424: e1 1c 00 00 blti \$1,0x1,424 <blti\+0x4>
+ 428: e8 2c 00 01 blti \$8,0x2,42a <blti\+0xa>
+ 42c: eb 2c 00 01 blti \$11,0x2,42e <blti\+0xe>
+ 430: ef 3c ff ff blti \$sp,0x3,42e <blti\+0xe>
+
+00000434 <bgei>:
+ 434: e4 38 ff fc bgei \$4,0x3,42c <blti\+0xc>
+ 438: e7 08 00 01 bgei \$7,0x0,43a <bgei\+0x6>
+ 43c: ed 18 00 00 bgei \$tp,0x1,43c <bgei\+0x8>
+ 440: e5 28 ff ff bgei \$5,0x2,43e <bgei\+0xa>
+ 444: ec 48 ff fc bgei \$12,0x4,43c <bgei\+0x8>
+
+00000448 <beq>:
+ 448: e7 21 ff ff beq \$7,\$2,446 <bgei\+0x12>
+ 44c: e1 31 ff fc beq \$1,\$3,444 <bgei\+0x10>
+ 450: e2 01 00 01 beq \$2,\$0,452 <beq\+0xa>
+ 454: ef 81 00 01 beq \$sp,\$8,456 <beq\+0xe>
+ 458: e3 01 00 00 beq \$3,\$0,458 <beq\+0x10>
+
+0000045c <bne>:
+ 45c: e6 35 00 00 bne \$6,\$3,45c <bne>
+ 460: ef 35 ff fc bne \$sp,\$3,458 <beq\+0x10>
+ 464: e8 05 00 01 bne \$8,\$0,466 <bne\+0xa>
+ 468: ee f5 00 04 bne \$gp,\$sp,470 <bsr12>
+ 46c: ef 45 00 01 bne \$sp,\$4,46e <bne\+0x12>
+
+00000470 <bsr12>:
+ 470: b0 03 bsr 472 <bsr12\+0x2>
+ 472: bf f9 bsr 46a <bne\+0xe>
+ 474: bf f1 bsr 464 <bne\+0x8>
+ 476: bf ff bsr 474 <bsr12\+0x4>
+ 478: bf f9 bsr 470 <bsr12>
+
+0000047a <bsr24>:
+ 47a: b0 05 bsr 47e <bsr24\+0x4>
+ 47c: bf ff bsr 47a <bsr24>
+ 47e: bf fd bsr 47a <bsr24>
+ 480: b0 01 bsr 480 <bsr24\+0x6>
+ 482: b0 03 bsr 484 <jmp>
+
+00000484 <jmp>:
+ 484: 10 2e jmp \$2
+ 486: 10 de jmp \$tp
+ 488: 10 5e jmp \$5
+ 48a: 10 fe jmp \$sp
+ 48c: 10 8e jmp \$8
+
+0000048e <jmp24>:
+ 48e: d8 28 00 00 jmp 4 <sb\+0x4>
+ 492: d8 18 00 00 jmp 2 <sb\+0x2>
+ 496: d8 08 00 00 jmp 0 <sb>
+ 49a: d8 18 00 00 jmp 2 <sb\+0x2>
+ 49e: d8 28 00 00 jmp 4 <sb\+0x4>
+
+000004a2 <jsr>:
+ 4a2: 10 ff jsr \$sp
+ 4a4: 10 df jsr \$tp
+ 4a6: 10 df jsr \$tp
+ 4a8: 10 6f jsr \$6
+ 4aa: 10 6f jsr \$6
+
+000004ac <ret>:
+ 4ac: 70 02 ret
+
+000004ae <repeat>:
+ 4ae: e4 09 00 01 repeat \$4,4b0 <repeat\+0x2>
+ 4b2: e8 09 00 02 repeat \$8,4b6 <repeat\+0x8>
+ 4b6: e0 09 00 04 repeat \$0,4be <repeat\+0x10>
+ 4ba: e6 09 00 01 repeat \$6,4bc <repeat\+0xe>
+ 4be: e4 09 00 01 repeat \$4,4c0 <repeat\+0x12>
+
+000004c2 <erepeat>:
+ 4c2: e0 19 00 01 erepeat 4c4 <erepeat\+0x2>
+ 4c6: e0 19 00 00 erepeat 4c6 <erepeat\+0x4>
+ 4ca: e0 19 00 01 erepeat 4cc <erepeat\+0xa>
+ 4ce: e0 19 ff ff erepeat 4cc <erepeat\+0xa>
+ 4d2: e0 19 00 00 erepeat 4d2 <erepeat\+0x10>
+
+000004d6 <stc>:
+ 4d6: 7d e8 stc \$tp,\$mb1
+ 4d8: 7d c9 stc \$tp,\$ccfg
+ 4da: 7b 89 stc \$11,\$dbg
+ 4dc: 7a c9 stc \$10,\$ccfg
+ 4de: 79 39 stc \$9,\$epc
+
+000004e0 <ldc>:
+ 4e0: 7d 8a ldc \$tp,\$lo
+ 4e2: 78 7b ldc \$8,\$npc
+ 4e4: 79 ca ldc \$9,\$mb0
+ 4e6: 7f 2a ldc \$sp,\$sar
+ 4e8: 79 cb ldc \$9,\$ccfg
+
+000004ea <di>:
+ 4ea: 70 00 di
+
+000004ec <ei>:
+ 4ec: 70 10 ei
+
+000004ee <reti>:
+ 4ee: 70 12 reti
+
+000004f0 <halt>:
+ 4f0: 70 22 halt
+
+000004f2 <swi>:
+ 4f2: 70 26 swi 0x2
+ 4f4: 70 06 swi 0x0
+ 4f6: 70 26 swi 0x2
+ 4f8: 70 36 swi 0x3
+ 4fa: 70 16 swi 0x1
+
+000004fc <break>:
+ 4fc: 70 32 break
+
+000004fe <syncm>:
+ 4fe: 70 11 syncm
+
+00000500 <stcb>:
+ 500: f5 04 00 04 stcb \$5,0x4
+ 504: f5 04 00 01 stcb \$5,0x1
+ 508: fe 04 00 00 stcb \$gp,0x0
+ 50c: ff 04 00 04 stcb \$sp,0x4
+ 510: fb 04 00 02 stcb \$11,0x2
+
+00000514 <ldcb>:
+ 514: f2 14 00 03 ldcb \$2,0x3
+ 518: f2 14 00 04 ldcb \$2,0x4
+ 51c: f9 14 00 01 ldcb \$9,0x1
+ 520: fa 14 00 04 ldcb \$10,0x4
+ 524: f1 14 00 04 ldcb \$1,0x4
+
+00000528 <bsetm>:
+ 528: 20 a0 bsetm \(\$10\),0x0
+ 52a: 20 f0 bsetm \(\$sp\),0x0
+ 52c: 22 10 bsetm \(\$1\),0x2
+ 52e: 24 f0 bsetm \(\$sp\),0x4
+ 530: 24 80 bsetm \(\$8\),0x4
+
+00000532 <bclrm>:
+ 532: 20 51 bclrm \(\$5\),0x0
+ 534: 22 51 bclrm \(\$5\),0x2
+ 536: 20 81 bclrm \(\$8\),0x0
+ 538: 22 91 bclrm \(\$9\),0x2
+ 53a: 23 51 bclrm \(\$5\),0x3
+
+0000053c <bnotm>:
+ 53c: 24 e2 bnotm \(\$gp\),0x4
+ 53e: 24 b2 bnotm \(\$11\),0x4
+ 540: 20 a2 bnotm \(\$10\),0x0
+ 542: 24 d2 bnotm \(\$tp\),0x4
+ 544: 20 82 bnotm \(\$8\),0x0
+
+00000546 <btstm>:
+ 546: 20 e3 btstm \$0,\(\$gp\),0x0
+ 548: 21 e3 btstm \$0,\(\$gp\),0x1
+ 54a: 20 b3 btstm \$0,\(\$11\),0x0
+ 54c: 23 e3 btstm \$0,\(\$gp\),0x3
+ 54e: 22 83 btstm \$0,\(\$8\),0x2
+
+00000550 <tas>:
+ 550: 27 d4 tas \$7,\(\$tp\)
+ 552: 27 c4 tas \$7,\(\$12\)
+ 554: 23 84 tas \$3,\(\$8\)
+ 556: 22 54 tas \$2,\(\$5\)
+ 558: 26 a4 tas \$6,\(\$10\)
+
+0000055a <cache>:
+ 55a: 71 d4 cache 0x1,\(\$tp\)
+ 55c: 73 c4 cache 0x3,\(\$12\)
+ 55e: 73 94 cache 0x3,\(\$9\)
+ 560: 74 24 cache 0x4,\(\$2\)
+ 562: 74 74 cache 0x4,\(\$7\)
+
+00000564 <mul>:
+ 564: 18 e4 mul \$8,\$gp
+ 566: 12 94 mul \$2,\$9
+ 568: 1e f4 mul \$gp,\$sp
+ 56a: 19 74 mul \$9,\$7
+ 56c: 17 b4 mul \$7,\$11
+
+0000056e <mulu>:
+ 56e: 12 55 mulu \$2,\$5
+ 570: 16 e5 mulu \$6,\$gp
+ 572: 1e f5 mulu \$gp,\$sp
+ 574: 1b e5 mulu \$11,\$gp
+ 576: 13 95 mulu \$3,\$9
+
+00000578 <mulr>:
+ 578: 1c 66 mulr \$12,\$6
+ 57a: 1d 86 mulr \$tp,\$8
+ 57c: 17 a6 mulr \$7,\$10
+ 57e: 1e 16 mulr \$gp,\$1
+ 580: 10 f6 mulr \$0,\$sp
+
+00000582 <mulru>:
+ 582: 14 27 mulru \$4,\$2
+ 584: 1e 17 mulru \$gp,\$1
+ 586: 1f 47 mulru \$sp,\$4
+ 588: 1a 67 mulru \$10,\$6
+ 58a: 10 e7 mulru \$0,\$gp
+
+0000058c <madd>:
+ 58c: f4 b1 30 04 madd \$4,\$11
+ 590: ff e1 30 04 madd \$sp,\$gp
+ 594: fe f1 30 04 madd \$gp,\$sp
+ 598: f4 d1 30 04 madd \$4,\$tp
+ 59c: f1 e1 30 04 madd \$1,\$gp
+
+000005a0 <maddu>:
+ 5a0: f0 11 30 05 maddu \$0,\$1
+ 5a4: f7 61 30 05 maddu \$7,\$6
+ 5a8: f9 51 30 05 maddu \$9,\$5
+ 5ac: fe f1 30 05 maddu \$gp,\$sp
+ 5b0: f7 d1 30 05 maddu \$7,\$tp
+
+000005b4 <maddr>:
+ 5b4: f6 81 30 06 maddr \$6,\$8
+ 5b8: f9 e1 30 06 maddr \$9,\$gp
+ 5bc: f8 e1 30 06 maddr \$8,\$gp
+ 5c0: f3 21 30 06 maddr \$3,\$2
+ 5c4: f1 b1 30 06 maddr \$1,\$11
+
+000005c8 <maddru>:
+ 5c8: fa 31 30 07 maddru \$10,\$3
+ 5cc: ff c1 30 07 maddru \$sp,\$12
+ 5d0: f8 81 30 07 maddru \$8,\$8
+ 5d4: fe 31 30 07 maddru \$gp,\$3
+ 5d8: f8 f1 30 07 maddru \$8,\$sp
+
+000005dc <div>:
+ 5dc: 19 38 div \$9,\$3
+ 5de: 14 e8 div \$4,\$gp
+ 5e0: 12 c8 div \$2,\$12
+ 5e2: 18 d8 div \$8,\$tp
+ 5e4: 1d 68 div \$tp,\$6
+
+000005e6 <divu>:
+ 5e6: 19 59 divu \$9,\$5
+ 5e8: 18 d9 divu \$8,\$tp
+ 5ea: 10 e9 divu \$0,\$gp
+ 5ec: 19 59 divu \$9,\$5
+ 5ee: 10 59 divu \$0,\$5
+
+000005f0 <dret>:
+ 5f0: 70 13 dret
+
+000005f2 <dbreak>:
+ 5f2: 70 33 dbreak
+
+000005f4 <ldz>:
+ 5f4: fe 41 00 00 ldz \$gp,\$4
+ 5f8: fa b1 00 00 ldz \$10,\$11
+ 5fc: f9 91 00 00 ldz \$9,\$9
+ 600: ff d1 00 00 ldz \$sp,\$tp
+ 604: fe 31 00 00 ldz \$gp,\$3
+
+00000608 <abs>:
+ 608: ff 91 00 03 abs \$sp,\$9
+ 60c: f5 41 00 03 abs \$5,\$4
+ 610: fd d1 00 03 abs \$tp,\$tp
+ 614: f0 31 00 03 abs \$0,\$3
+ 618: f3 e1 00 03 abs \$3,\$gp
+
+0000061c <ave>:
+ 61c: fb a1 00 02 ave \$11,\$10
+ 620: f8 a1 00 02 ave \$8,\$10
+ 624: fe 21 00 02 ave \$gp,\$2
+ 628: fa c1 00 02 ave \$10,\$12
+ 62c: ff 81 00 02 ave \$sp,\$8
+
+00000630 <min>:
+ 630: f8 31 00 04 min \$8,\$3
+ 634: f7 01 00 04 min \$7,\$0
+ 638: f2 21 00 04 min \$2,\$2
+ 63c: f5 61 00 04 min \$5,\$6
+ 640: fb 51 00 04 min \$11,\$5
+
+00000644 <max>:
+ 644: fb f1 00 05 max \$11,\$sp
+ 648: fe 01 00 05 max \$gp,\$0
+ 64c: fc f1 00 05 max \$12,\$sp
+ 650: fe 21 00 05 max \$gp,\$2
+ 654: fe f1 00 05 max \$gp,\$sp
+
+00000658 <minu>:
+ 658: fb 81 00 06 minu \$11,\$8
+ 65c: f7 51 00 06 minu \$7,\$5
+ 660: f8 e1 00 06 minu \$8,\$gp
+ 664: fb 41 00 06 minu \$11,\$4
+ 668: f2 f1 00 06 minu \$2,\$sp
+
+0000066c <maxu>:
+ 66c: f3 31 00 07 maxu \$3,\$3
+ 670: fd 01 00 07 maxu \$tp,\$0
+ 674: f4 81 00 07 maxu \$4,\$8
+ 678: fe 21 00 07 maxu \$gp,\$2
+ 67c: fc 81 00 07 maxu \$12,\$8
+
+00000680 <clip>:
+ 680: fa 01 10 08 clip \$10,0x1
+ 684: ff 01 10 20 clip \$sp,0x4
+ 688: f4 01 10 18 clip \$4,0x3
+ 68c: ff 01 10 18 clip \$sp,0x3
+ 690: f1 01 10 00 clip \$1,0x0
+
+00000694 <clipu>:
+ 694: fa 01 10 21 clipu \$10,0x4
+ 698: fd 01 10 09 clipu \$tp,0x1
+ 69c: f5 01 10 21 clipu \$5,0x4
+ 6a0: fe 01 10 01 clipu \$gp,0x0
+ 6a4: f5 01 10 09 clipu \$5,0x1
+
+000006a8 <sadd>:
+ 6a8: f5 01 00 08 sadd \$5,\$0
+ 6ac: ff 31 00 08 sadd \$sp,\$3
+ 6b0: f0 a1 00 08 sadd \$0,\$10
+ 6b4: ff c1 00 08 sadd \$sp,\$12
+ 6b8: f4 21 00 08 sadd \$4,\$2
+
+000006bc <ssub>:
+ 6bc: f1 a1 00 0a ssub \$1,\$10
+ 6c0: f4 71 00 0a ssub \$4,\$7
+ 6c4: f8 31 00 0a ssub \$8,\$3
+ 6c8: f7 e1 00 0a ssub \$7,\$gp
+ 6cc: fd 41 00 0a ssub \$tp,\$4
+
+000006d0 <saddu>:
+ 6d0: f9 e1 00 09 saddu \$9,\$gp
+ 6d4: f0 a1 00 09 saddu \$0,\$10
+ 6d8: f7 c1 00 09 saddu \$7,\$12
+ 6dc: f5 f1 00 09 saddu \$5,\$sp
+ 6e0: fd 31 00 09 saddu \$tp,\$3
+
+000006e4 <ssubu>:
+ 6e4: ff e1 00 0b ssubu \$sp,\$gp
+ 6e8: f0 f1 00 0b ssubu \$0,\$sp
+ 6ec: f3 a1 00 0b ssubu \$3,\$10
+ 6f0: ff d1 00 0b ssubu \$sp,\$tp
+ 6f4: f2 91 00 0b ssubu \$2,\$9
+
+000006f8 <swcp>:
+ 6f8: 33 d8 swcp \$c3,\(\$tp\)
+ 6fa: 3f d8 swcp \$c15,\(\$tp\)
+ 6fc: 3d 08 swcp \$c13,\(\$0\)
+ 6fe: 3c c8 swcp \$c12,\(\$12\)
+ 700: 39 e8 swcp \$c9,\(\$gp\)
+
+00000702 <lwcp>:
+ 702: 37 39 lwcp \$c7,\(\$3\)
+ 704: 36 39 lwcp \$c6,\(\$3\)
+ 706: 30 29 lwcp \$c0,\(\$2\)
+ 708: 38 89 lwcp \$c8,\(\$8\)
+ 70a: 3b d9 lwcp \$c11,\(\$tp\)
+
+0000070c <smcp>:
+ 70c: 3e 9a smcp \$c14,\(\$9\)
+ 70e: 32 8a smcp \$c2,\(\$8\)
+ 710: 3e fa smcp \$c14,\(\$sp\)
+ 712: 3a 8a smcp \$c10,\(\$8\)
+ 714: 32 8a smcp \$c2,\(\$8\)
+
+00000716 <lmcp>:
+ 716: 3b 1b lmcp \$c11,\(\$1\)
+ 718: 38 8b lmcp \$c8,\(\$8\)
+ 71a: 3b db lmcp \$c11,\(\$tp\)
+ 71c: 38 0b lmcp \$c8,\(\$0\)
+ 71e: 38 eb lmcp \$c8,\(\$gp\)
+
+00000720 <swcpi>:
+ 720: 37 00 swcpi \$c7,\(\$0\+\)
+ 722: 36 e0 swcpi \$c6,\(\$gp\+\)
+ 724: 3c 80 swcpi \$c12,\(\$8\+\)
+ 726: 3e f0 swcpi \$c14,\(\$sp\+\)
+ 728: 36 00 swcpi \$c6,\(\$0\+\)
+
+0000072a <lwcpi>:
+ 72a: 38 21 lwcpi \$c8,\(\$2\+\)
+ 72c: 39 01 lwcpi \$c9,\(\$0\+\)
+ 72e: 33 e1 lwcpi \$c3,\(\$gp\+\)
+ 730: 3d 51 lwcpi \$c13,\(\$5\+\)
+ 732: 3b e1 lwcpi \$c11,\(\$gp\+\)
+
+00000734 <smcpi>:
+ 734: 38 22 smcpi \$c8,\(\$2\+\)
+ 736: 3b 92 smcpi \$c11,\(\$9\+\)
+ 738: 34 32 smcpi \$c4,\(\$3\+\)
+ 73a: 3e 22 smcpi \$c14,\(\$2\+\)
+ 73c: 39 32 smcpi \$c9,\(\$3\+\)
+
+0000073e <lmcpi>:
+ 73e: 36 e3 lmcpi \$c6,\(\$gp\+\)
+ 740: 39 53 lmcpi \$c9,\(\$5\+\)
+ 742: 3a 63 lmcpi \$c10,\(\$6\+\)
+ 744: 31 63 lmcpi \$c1,\(\$6\+\)
+ 746: 32 83 lmcpi \$c2,\(\$8\+\)
+
+00000748 <swcp16>:
+ 748: f0 2c ff ff swcp \$c0,-1\(\$2\)
+ 74c: f5 ac 00 01 swcp \$c5,1\(\$10\)
+ 750: f8 cc 00 02 swcp \$c8,2\(\$12\)
+ 754: fe 1c ff ff swcp \$c14,-1\(\$1\)
+ 758: fc 3c 00 02 swcp \$c12,2\(\$3\)
+
+0000075c <lwcp16>:
+ 75c: f8 5d ff ff lwcp \$c8,-1\(\$5\)
+ 760: fc fd 00 01 lwcp \$c12,1\(\$sp\)
+ 764: f1 0d 00 02 lwcp \$c1,2\(\$0\)
+ 768: f4 dd 00 01 lwcp \$c4,1\(\$tp\)
+ 76c: f6 bd 00 02 lwcp \$c6,2\(\$11\)
+
+00000770 <smcp16>:
+ 770: f9 ae ff ff smcp \$c9,-1\(\$10\)
+ 774: fe ee 00 01 smcp \$c14,1\(\$gp\)
+ 778: f3 fe 00 02 smcp \$c3,2\(\$sp\)
+ 77c: ff 8e ff fe smcp \$c15,-2\(\$8\)
+ 780: fd de 00 01 smcp \$c13,1\(\$tp\)
+
+00000784 <lmcp16>:
+ 784: f0 ff 00 01 lmcp \$c0,1\(\$sp\)
+ 788: ff 8f 00 01 lmcp \$c15,1\(\$8\)
+ 78c: f2 8f ff ff lmcp \$c2,-1\(\$8\)
+ 790: fe 8f 00 01 lmcp \$c14,1\(\$8\)
+ 794: f1 af ff ff lmcp \$c1,-1\(\$10\)
+
+00000798 <sbcpa>:
+ 798: fe f5 00 02 sbcpa \$c14,\(\$sp\+\),2
+ 79c: f2 45 00 fe sbcpa \$c2,\(\$4\+\),-2
+ 7a0: f8 15 00 00 sbcpa \$c8,\(\$1\+\),0
+ 7a4: fb 35 00 00 sbcpa \$c11,\(\$3\+\),0
+ 7a8: f9 e5 00 fe sbcpa \$c9,\(\$gp\+\),-2
+
+000007ac <lbcpa>:
+ 7ac: f7 25 40 fe lbcpa \$c7,\(\$2\+\),-2
+ 7b0: fc f5 40 02 lbcpa \$c12,\(\$sp\+\),2
+ 7b4: f5 45 40 fe lbcpa \$c5,\(\$4\+\),-2
+ 7b8: f7 45 40 fe lbcpa \$c7,\(\$4\+\),-2
+ 7bc: f8 f5 40 00 lbcpa \$c8,\(\$sp\+\),0
+
+000007c0 <shcpa>:
+ 7c0: f0 e5 10 00 shcpa \$c0,\(\$gp\+\),0
+ 7c4: fc f5 10 10 shcpa \$c12,\(\$sp\+\),16
+ 7c8: f1 45 10 04 shcpa \$c1,\(\$4\+\),4
+ 7cc: f5 45 10 e0 shcpa \$c5,\(\$4\+\),-32
+ 7d0: f1 f5 10 00 shcpa \$c1,\(\$sp\+\),0
+
+000007d4 <lhcpa>:
+ 7d4: f4 45 50 00 lhcpa \$c4,\(\$4\+\),0
+ 7d8: f6 55 50 30 lhcpa \$c6,\(\$5\+\),48
+ 7dc: f3 65 50 cc lhcpa \$c3,\(\$6\+\),-52
+ 7e0: f8 65 50 e8 lhcpa \$c8,\(\$6\+\),-24
+ 7e4: f0 95 50 00 lhcpa \$c0,\(\$9\+\),0
+
+000007e8 <swcpa>:
+ 7e8: f1 95 20 10 swcpa \$c1,\(\$9\+\),16
+ 7ec: f7 f5 20 20 swcpa \$c7,\(\$sp\+\),32
+ 7f0: f3 c5 20 30 swcpa \$c3,\(\$12\+\),48
+ 7f4: fa 95 20 08 swcpa \$c10,\(\$9\+\),8
+ 7f8: fe 85 20 04 swcpa \$c14,\(\$8\+\),4
+
+000007fc <lwcpa>:
+ 7fc: f6 e5 60 f8 lwcpa \$c6,\(\$gp\+\),-8
+ 800: f4 75 60 04 lwcpa \$c4,\(\$7\+\),4
+ 804: fb e5 60 f0 lwcpa \$c11,\(\$gp\+\),-16
+ 808: fa f5 60 e0 lwcpa \$c10,\(\$sp\+\),-32
+ 80c: f2 25 60 08 lwcpa \$c2,\(\$2\+\),8
+
+00000810 <smcpa>:
+ 810: fd f5 30 f8 smcpa \$c13,\(\$sp\+\),-8
+ 814: f6 75 30 f8 smcpa \$c6,\(\$7\+\),-8
+ 818: f5 35 30 10 smcpa \$c5,\(\$3\+\),16
+ 81c: fd f5 30 10 smcpa \$c13,\(\$sp\+\),16
+ 820: f3 c5 30 30 smcpa \$c3,\(\$12\+\),48
+
+00000824 <lmcpa>:
+ 824: f9 45 70 00 lmcpa \$c9,\(\$4\+\),0
+ 828: f3 f5 70 f0 lmcpa \$c3,\(\$sp\+\),-16
+ 82c: ff d5 70 08 lmcpa \$c15,\(\$tp\+\),8
+ 830: f8 85 70 f8 lmcpa \$c8,\(\$8\+\),-8
+ 834: fa 95 70 00 lmcpa \$c10,\(\$9\+\),0
+
+00000838 <sbcpm0>:
+ 838: fa d5 08 08 sbcpm0 \$c10,\(\$tp\+\),8
+ 83c: fd 55 08 f8 sbcpm0 \$c13,\(\$5\+\),-8
+ 840: f4 55 08 f8 sbcpm0 \$c4,\(\$5\+\),-8
+ 844: fa d5 08 10 sbcpm0 \$c10,\(\$tp\+\),16
+ 848: f4 55 08 e8 sbcpm0 \$c4,\(\$5\+\),-24
+
+0000084c <lbcpm0>:
+ 84c: f0 45 48 00 lbcpm0 \$c0,\(\$4\+\),0
+ 850: f9 75 48 f8 lbcpm0 \$c9,\(\$7\+\),-8
+ 854: fc 85 48 18 lbcpm0 \$c12,\(\$8\+\),24
+ 858: f8 c5 48 10 lbcpm0 \$c8,\(\$12\+\),16
+ 85c: f7 85 48 10 lbcpm0 \$c7,\(\$8\+\),16
+
+00000860 <shcpm0>:
+ 860: f2 d5 18 02 shcpm0 \$c2,\(\$tp\+\),2
+ 864: f7 f5 18 fe shcpm0 \$c7,\(\$sp\+\),-2
+ 868: f8 25 18 02 shcpm0 \$c8,\(\$2\+\),2
+ 86c: fd 55 18 00 shcpm0 \$c13,\(\$5\+\),0
+ 870: f3 e5 18 08 shcpm0 \$c3,\(\$gp\+\),8
+
+00000874 <lhcpm0>:
+ 874: f7 45 58 08 lhcpm0 \$c7,\(\$4\+\),8
+ 878: f3 35 58 fe lhcpm0 \$c3,\(\$3\+\),-2
+ 87c: f3 15 58 00 lhcpm0 \$c3,\(\$1\+\),0
+ 880: f2 e5 58 00 lhcpm0 \$c2,\(\$gp\+\),0
+ 884: fc 65 58 02 lhcpm0 \$c12,\(\$6\+\),2
+
+00000888 <swcpm0>:
+ 888: f8 85 28 20 swcpm0 \$c8,\(\$8\+\),32
+ 88c: f9 f5 28 00 swcpm0 \$c9,\(\$sp\+\),0
+ 890: f9 25 28 f0 swcpm0 \$c9,\(\$2\+\),-16
+ 894: f0 e5 28 30 swcpm0 \$c0,\(\$gp\+\),48
+ 898: ff 15 28 08 swcpm0 \$c15,\(\$1\+\),8
+
+0000089c <lwcpm0>:
+ 89c: fe a5 68 fc lwcpm0 \$c14,\(\$10\+\),-4
+ 8a0: fb f5 68 fc lwcpm0 \$c11,\(\$sp\+\),-4
+ 8a4: f5 75 68 f8 lwcpm0 \$c5,\(\$7\+\),-8
+ 8a8: f2 c5 68 20 lwcpm0 \$c2,\(\$12\+\),32
+ 8ac: f2 e5 68 10 lwcpm0 \$c2,\(\$gp\+\),16
+
+000008b0 <smcpm0>:
+ 8b0: f1 c5 38 08 smcpm0 \$c1,\(\$12\+\),8
+ 8b4: f8 45 38 f0 smcpm0 \$c8,\(\$4\+\),-16
+ 8b8: fa b5 38 00 smcpm0 \$c10,\(\$11\+\),0
+ 8bc: f1 35 38 f0 smcpm0 \$c1,\(\$3\+\),-16
+ 8c0: fb f5 38 f8 smcpm0 \$c11,\(\$sp\+\),-8
+
+000008c4 <lmcpm0>:
+ 8c4: fe a5 78 00 lmcpm0 \$c14,\(\$10\+\),0
+ 8c8: f6 f5 78 f0 lmcpm0 \$c6,\(\$sp\+\),-16
+ 8cc: fd 15 78 08 lmcpm0 \$c13,\(\$1\+\),8
+ 8d0: fa d5 78 e8 lmcpm0 \$c10,\(\$tp\+\),-24
+ 8d4: f7 e5 78 e8 lmcpm0 \$c7,\(\$gp\+\),-24
+
+000008d8 <sbcpm1>:
+ 8d8: f9 85 0c 00 sbcpm1 \$c9,\(\$8\+\),0
+ 8dc: f7 c5 0c e8 sbcpm1 \$c7,\(\$12\+\),-24
+ 8e0: ff 55 0c e8 sbcpm1 \$c15,\(\$5\+\),-24
+ 8e4: f5 d5 0c 10 sbcpm1 \$c5,\(\$tp\+\),16
+ 8e8: f6 15 0c 80 sbcpm1 \$c6,\(\$1\+\),-128
+
+000008ec <lbcpm1>:
+ 8ec: f6 e5 4c 02 lbcpm1 \$c6,\(\$gp\+\),2
+ 8f0: f7 d5 4c fe lbcpm1 \$c7,\(\$tp\+\),-2
+ 8f4: f4 d5 4c 01 lbcpm1 \$c4,\(\$tp\+\),1
+ 8f8: fc 25 4c fe lbcpm1 \$c12,\(\$2\+\),-2
+ 8fc: fb 75 4c 01 lbcpm1 \$c11,\(\$7\+\),1
+
+00000900 <shcpm1>:
+ 900: f4 85 1c 18 shcpm1 \$c4,\(\$8\+\),24
+ 904: fb 65 1c f0 shcpm1 \$c11,\(\$6\+\),-16
+ 908: f7 85 1c 08 shcpm1 \$c7,\(\$8\+\),8
+ 90c: f5 c5 1c 10 shcpm1 \$c5,\(\$12\+\),16
+ 910: f0 85 1c e0 shcpm1 \$c0,\(\$8\+\),-32
+
+00000914 <lhcpm1>:
+ 914: fb 05 5c 00 lhcpm1 \$c11,\(\$0\+\),0
+ 918: f7 d5 5c fe lhcpm1 \$c7,\(\$tp\+\),-2
+ 91c: fa 85 5c 08 lhcpm1 \$c10,\(\$8\+\),8
+ 920: f3 d5 5c 00 lhcpm1 \$c3,\(\$tp\+\),0
+ 924: f9 65 5c 02 lhcpm1 \$c9,\(\$6\+\),2
+
+00000928 <swcpm1>:
+ 928: f9 85 2c 18 swcpm1 \$c9,\(\$8\+\),24
+ 92c: f9 e5 2c 00 swcpm1 \$c9,\(\$gp\+\),0
+ 930: f9 85 2c 10 swcpm1 \$c9,\(\$8\+\),16
+ 934: fe 15 2c 00 swcpm1 \$c14,\(\$1\+\),0
+ 938: f2 f5 2c 08 swcpm1 \$c2,\(\$sp\+\),8
+
+0000093c <lwcpm1>:
+ 93c: f8 85 6c 00 lwcpm1 \$c8,\(\$8\+\),0
+ 940: f3 e5 6c f0 lwcpm1 \$c3,\(\$gp\+\),-16
+ 944: f7 65 6c f8 lwcpm1 \$c7,\(\$6\+\),-8
+ 948: fe 85 6c e8 lwcpm1 \$c14,\(\$8\+\),-24
+ 94c: f3 85 6c 18 lwcpm1 \$c3,\(\$8\+\),24
+
+00000950 <smcpm1>:
+ 950: fa 45 3c 00 smcpm1 \$c10,\(\$4\+\),0
+ 954: f6 f5 3c f0 smcpm1 \$c6,\(\$sp\+\),-16
+ 958: fd 75 3c e8 smcpm1 \$c13,\(\$7\+\),-24
+ 95c: f3 e5 3c f8 smcpm1 \$c3,\(\$gp\+\),-8
+ 960: f0 25 3c 08 smcpm1 \$c0,\(\$2\+\),8
+
+00000964 <lmcpm1>:
+ 964: fc 15 7c 00 lmcpm1 \$c12,\(\$1\+\),0
+ 968: f0 65 7c 08 lmcpm1 \$c0,\(\$6\+\),8
+ 96c: f6 25 7c f8 lmcpm1 \$c6,\(\$2\+\),-8
+ 970: fc e5 7c f0 lmcpm1 \$c12,\(\$gp\+\),-16
+ 974: fe f5 7c 30 lmcpm1 \$c14,\(\$sp\+\),48
+
+00000... <bcpeq>:
+ ...: d8 44 00 00 bcpeq 0x4,... <bcpeq>
+ ...: d8 04 ff ff bcpeq 0x0,... <bcpeq\+0x2>
+ ...: d8 44 ff ff bcpeq 0x4,... <bcpeq\+0x6>
+ ...: d8 14 00 01 bcpeq 0x1,... <bcpeq\+0xe>
+ ...: d8 24 00 01 bcpeq 0x2,... <bcpeq\+0x12>
+
+00000... <bcpne>:
+ ...: d8 25 00 00 bcpne 0x2,... <bcpne>
+ ...: d8 45 00 00 bcpne 0x4,... <bcpne\+0x4>
+ ...: d8 15 00 00 bcpne 0x1,... <bcpne\+0x8>
+ ...: d8 45 00 00 bcpne 0x4,... <bcpne\+0xc>
+ ...: d8 15 00 01 bcpne 0x1,... <bcpne\+0x12>
+
+00000... <bcpat>:
+ ...: d8 16 ff ff bcpat 0x1,... <bcpne\+0x12>
+ ...: d8 06 00 01 bcpat 0x0,... <bcpat\+0x6>
+ ...: d8 06 ff ff bcpat 0x0,... <bcpat\+0x6>
+ ...: d8 26 00 00 bcpat 0x2,... <bcpat\+0xc>
+ ...: d8 16 ff ff bcpat 0x1,... <bcpat\+0xe>
+
+00000... <bcpaf>:
+ ...: d8 47 00 00 bcpaf 0x4,... <bcpaf>
+ ...: d8 37 00 00 bcpaf 0x3,... <bcpaf\+0x4>
+ ...: d8 47 00 00 bcpaf 0x4,... <bcpaf\+0x8>
+ ...: d8 17 00 01 bcpaf 0x1,... <bcpaf\+0xe>
+ ...: d8 47 00 01 bcpaf 0x4,... <bcpaf\+0x12>
+
+00000... <synccp>:
+ ...: 70 21 synccp
+
+00000... <jsrv>:
+ ...: 18 bf jsrv \$11
+ ...: 18 5f jsrv \$5
+ ...: 18 af jsrv \$10
+ ...: 18 cf jsrv \$12
+ ...: 18 af jsrv \$10
+
+00000... <bsrv>:
+ ...: df fb ff ff bsrv ... <jsrv\+0x8>
+ ...: df fb ff ff bsrv ... <bsrv\+0x2>
+ ...: df fb ff ff bsrv ... <bsrv\+0x6>
+ ...: d8 1b 00 00 bsrv ... <bsrv\+0xe>
+ ...: d8 0b 00 00 bsrv ... <bsrv\+0x10>
+
+00000... <case106341>:
+ ...: 7a 78 stc \$10,\$hi
+ ...: 70 8a ldc \$0,\$lo
+
+00000... <case106821>:
+ ...: 00 08 sb \$0,\(\$0\)
+ ...: 00 09 sh \$0,\(\$0\)
+ ...: 00 0a sw \$0,\(\$0\)
+ ...: 00 0c lb \$0,\(\$0\)
+ ...: 00 0d lh \$0,\(\$0\)
+ ...: 00 0e lw \$0,\(\$0\)
+ ...: 00 0b lbu \$0,\(\$0\)
+ ...: 00 0f lhu \$0,\(\$0\)
+ ...: 00 08 sb \$0,\(\$0\)
+ ...: 00 08 sb \$0,\(\$0\)
+ ...: 00 08 sb \$0,\(\$0\)
+ ...: 00 08 sb \$0,\(\$0\)
+ ...: 00 08 sb \$0,\(\$0\)
+ ...: 00 08 sb \$0,\(\$0\)
+ ...: 00 09 sh \$0,\(\$0\)
+ ...: 00 09 sh \$0,\(\$0\)
+ ...: 00 09 sh \$0,\(\$0\)
+ ...: 00 09 sh \$0,\(\$0\)
+ ...: 00 09 sh \$0,\(\$0\)
+ ...: 00 09 sh \$0,\(\$0\)
+ ...: 00 0a sw \$0,\(\$0\)
+ ...: 00 0a sw \$0,\(\$0\)
+ ...: 00 0a sw \$0,\(\$0\)
+ ...: 00 0a sw \$0,\(\$0\)
+ ...: 00 0a sw \$0,\(\$0\)
+ ...: 00 0a sw \$0,\(\$0\)
+ ...: 00 0c lb \$0,\(\$0\)
+ ...: 00 0c lb \$0,\(\$0\)
+ ...: 00 0c lb \$0,\(\$0\)
+ ...: 00 0c lb \$0,\(\$0\)
+ ...: 00 0c lb \$0,\(\$0\)
+ ...: 00 0c lb \$0,\(\$0\)
+ ...: 00 0d lh \$0,\(\$0\)
+ ...: 00 0d lh \$0,\(\$0\)
+ ...: 00 0d lh \$0,\(\$0\)
+ ...: 00 0d lh \$0,\(\$0\)
+ ...: 00 0d lh \$0,\(\$0\)
+ ...: 00 0d lh \$0,\(\$0\)
+ ...: 00 0e lw \$0,\(\$0\)
+ ...: 00 0e lw \$0,\(\$0\)
+ ...: 00 0e lw \$0,\(\$0\)
+ ...: 00 0e lw \$0,\(\$0\)
+ ...: 00 0e lw \$0,\(\$0\)
+ ...: 00 0e lw \$0,\(\$0\)
+ ...: 00 0b lbu \$0,\(\$0\)
+ ...: 00 0b lbu \$0,\(\$0\)
+ ...: 00 0b lbu \$0,\(\$0\)
+ ...: 00 0b lbu \$0,\(\$0\)
+ ...: 00 0b lbu \$0,\(\$0\)
+ ...: 00 0b lbu \$0,\(\$0\)
+ ...: 00 0f lhu \$0,\(\$0\)
+ ...: 00 0f lhu \$0,\(\$0\)
+ ...: 00 0f lhu \$0,\(\$0\)
+ ...: 00 0f lhu \$0,\(\$0\)
+ ...: 00 0f lhu \$0,\(\$0\)
+ ...: 00 0f lhu \$0,\(\$0\)
+ ...: c0 08 00 01 sb \$0,1\(\$0\)
+ ...: c0 08 00 01 sb \$0,1\(\$0\)
+ ...: c0 08 00 00 sb \$0,0\(\$0\)
+ ...: c0 08 00 00 sb \$0,0\(\$0\)
+ ...: c0 08 00 01 sb \$0,1\(\$0\)
+ ...: c0 08 00 01 sb \$0,1\(\$0\)
+ ...: c0 09 00 01 sh \$0,1\(\$0\)
+ ...: c0 09 00 01 sh \$0,1\(\$0\)
+ ...: c0 09 00 00 sh \$0,0\(\$0\)
+ ...: c0 09 00 00 sh \$0,0\(\$0\)
+ ...: c0 09 00 01 sh \$0,1\(\$0\)
+ ...: c0 09 00 01 sh \$0,1\(\$0\)
+ ...: c0 0a 00 01 sw \$0,1\(\$0\)
+ ...: c0 0a 00 01 sw \$0,1\(\$0\)
+ ...: c0 0a 00 00 sw \$0,0\(\$0\)
+ ...: c0 0a 00 00 sw \$0,0\(\$0\)
+ ...: c0 0a 00 01 sw \$0,1\(\$0\)
+ ...: c0 0a 00 01 sw \$0,1\(\$0\)
+ ...: c0 0c 00 01 lb \$0,1\(\$0\)
+ ...: c0 0c 00 01 lb \$0,1\(\$0\)
+ ...: c0 0c 00 00 lb \$0,0\(\$0\)
+ ...: c0 0c 00 00 lb \$0,0\(\$0\)
+ ...: c0 0c 00 01 lb \$0,1\(\$0\)
+ ...: c0 0c 00 01 lb \$0,1\(\$0\)
+ ...: c0 0d 00 01 lh \$0,1\(\$0\)
+ ...: c0 0d 00 01 lh \$0,1\(\$0\)
+ ...: c0 0d 00 00 lh \$0,0\(\$0\)
+ ...: c0 0d 00 00 lh \$0,0\(\$0\)
+ ...: c0 0d 00 01 lh \$0,1\(\$0\)
+ ...: c0 0d 00 01 lh \$0,1\(\$0\)
+ ...: c0 0e 00 01 lw \$0,1\(\$0\)
+ ...: c0 0e 00 01 lw \$0,1\(\$0\)
+ ...: c0 0e 00 00 lw \$0,0\(\$0\)
+ ...: c0 0e 00 00 lw \$0,0\(\$0\)
+ ...: c0 0e 00 01 lw \$0,1\(\$0\)
+ ...: c0 0e 00 01 lw \$0,1\(\$0\)
+ ...: c0 0b 00 01 lbu \$0,1\(\$0\)
+ ...: c0 0b 00 01 lbu \$0,1\(\$0\)
+ ...: c0 0b 00 00 lbu \$0,0\(\$0\)
+ ...: c0 0b 00 00 lbu \$0,0\(\$0\)
+ ...: c0 0b 00 01 lbu \$0,1\(\$0\)
+ ...: c0 0b 00 01 lbu \$0,1\(\$0\)
+ ...: c0 0f 00 01 lhu \$0,1\(\$0\)
+ ...: c0 0f 00 01 lhu \$0,1\(\$0\)
+ ...: c0 0f 00 00 lhu \$0,0\(\$0\)
+ ...: c0 0f 00 00 lhu \$0,0\(\$0\)
+ ...: c0 0f 00 01 lhu \$0,1\(\$0\)
+ ...: c0 0f 00 01 lhu \$0,1\(\$0\)
+ ...: c0 08 00 00 sb \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: c0 08 00 00 sb \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: c0 08 00 00 sb \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: c0 08 00 00 sb \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: c0 09 00 00 sh \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: c0 09 00 00 sh \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: c0 09 00 00 sh \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: c0 09 00 00 sh \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: c0 0a 00 00 sw \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: c0 0a 00 00 sw \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: c0 0a 00 00 sw \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: c0 0a 00 00 sw \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: c0 0c 00 00 lb \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: c0 0c 00 00 lb \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: c0 0c 00 00 lb \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: c0 0c 00 00 lb \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: c0 0d 00 00 lh \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: c0 0d 00 00 lh \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: c0 0d 00 00 lh \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: c0 0d 00 00 lh \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: c0 0e 00 00 lw \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: c0 0e 00 00 lw \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: c0 0e 00 00 lw \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: c0 0e 00 00 lw \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: c0 0b 00 00 lbu \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: c0 0b 00 00 lbu \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: c0 0b 00 00 lbu \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: c0 0b 00 00 lbu \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: c0 0f 00 00 lhu \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: c0 0f 00 00 lhu \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: c0 0f 00 00 lhu \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: c0 0f 00 00 lhu \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
--- /dev/null
+# MEP assembler testsuite. -*- Tcl -*-
+
+if [istarget mep*-*-*] {
+ foreach test {allinsn dj1 dj2} {
+ run_dump_test $test
+ run_dump_test $test.le
+ }
+ run_dump_test branch1
+}
--- /dev/null
+#as: -EL
+#objdump: -dr
+#source: allinsn.s
+#name: allinsn.le
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <sb>:
+ 0: 88 07 sb \$7,\(\$8\)
+ 2: 98 05 sb \$5,\(\$9\)
+ 4: e8 07 sb \$7,\(\$gp\)
+ 6: 88 0e sb \$gp,\(\$8\)
+ 8: e8 0f sb \$sp,\(\$gp\)
+
+0000000a <sh>:
+ a: 89 03 sh \$3,\(\$8\)
+ c: 19 0c sh \$12,\(\$1\)
+ e: 29 0d sh \$tp,\(\$2\)
+ 10: 89 02 sh \$2,\(\$8\)
+ 12: a9 0c sh \$12,\(\$10\)
+
+00000014 <sw>:
+ 14: 0a 0b sw \$11,\(\$0\)
+ 16: 7a 03 sw \$3,\(\$7\)
+ 18: ea 0d sw \$tp,\(\$gp\)
+ 1a: 9a 08 sw \$8,\(\$9\)
+ 1c: 8a 0e sw \$gp,\(\$8\)
+
+0000001e <lb>:
+ 1e: bc 0c lb \$12,\(\$11\)
+ 20: 2c 09 lb \$9,\(\$2\)
+ 22: bc 08 lb \$8,\(\$11\)
+ 24: 2c 0e lb \$gp,\(\$2\)
+ 26: cc 02 lb \$2,\(\$12\)
+
+00000028 <lh>:
+ 28: 8d 0f lh \$sp,\(\$8\)
+ 2a: ad 03 lh \$3,\(\$10\)
+ 2c: fd 09 lh \$9,\(\$sp\)
+ 2e: fd 06 lh \$6,\(\$sp\)
+ 30: bd 0f lh \$sp,\(\$11\)
+
+00000032 <lw>:
+ 32: ae 0c lw \$12,\(\$10\)
+ 34: de 09 lw \$9,\(\$tp\)
+ 36: ee 0c lw \$12,\(\$gp\)
+ 38: be 0c lw \$12,\(\$11\)
+ 3a: ae 0d lw \$tp,\(\$10\)
+
+0000003c <lbu>:
+ 3c: eb 0e lbu \$gp,\(\$gp\)
+ 3e: 8b 0c lbu \$12,\(\$8\)
+ 40: 1b 0e lbu \$gp,\(\$1\)
+ 42: cb 08 lbu \$8,\(\$12\)
+ 44: 1b 0c lbu \$12,\(\$1\)
+
+00000046 <lhu>:
+ 46: 4f 0f lhu \$sp,\(\$4\)
+ 48: 4f 0e lhu \$gp,\(\$4\)
+ 4a: 4f 05 lhu \$5,\(\$4\)
+ 4c: df 0f lhu \$sp,\(\$tp\)
+ 4e: ff 04 lhu \$4,\(\$sp\)
+
+00000050 <sw_sp>:
+ 50: 8a c9 03 00 sw \$9,3\(\$8\)
+ 54: 5a ca 04 00 sw \$10,4\(\$5\)
+ 58: ea c0 03 00 sw \$0,3\(\$gp\)
+ 5c: 8a c0 02 00 sw \$0,2\(\$8\)
+ 60: 8a cf 01 00 sw \$sp,1\(\$8\)
+
+00000064 <lw_sp>:
+ 64: 5e cd 01 00 lw \$tp,1\(\$5\)
+ 68: 0e cf 01 00 lw \$sp,1\(\$0\)
+ 6c: ce c0 04 00 lw \$0,4\(\$12\)
+ 70: de cb 01 00 lw \$11,1\(\$tp\)
+ 74: 4e c9 03 00 lw \$9,3\(\$4\)
+
+00000078 <sb_tp>:
+ 78: 18 c5 01 00 sb \$5,1\(\$1\)
+ 7c: 98 ca 01 00 sb \$10,1\(\$9\)
+ 80: 38 c5 03 00 sb \$5,3\(\$3\)
+ 84: 38 c5 01 00 sb \$5,1\(\$3\)
+ 88: 48 ca 04 00 sb \$10,4\(\$4\)
+
+0000008c <sh_tp>:
+ 8c: 09 c3 01 00 sh \$3,1\(\$0\)
+ 90: 99 cd 01 00 sh \$tp,1\(\$9\)
+ 94: a9 c9 04 00 sh \$9,4\(\$10\)
+ 98: e9 cf 03 00 sh \$sp,3\(\$gp\)
+ 9c: 99 ce 04 00 sh \$gp,4\(\$9\)
+
+000000a0 <sw_tp>:
+ a0: da c6 02 00 sw \$6,2\(\$tp\)
+ a4: fa c6 01 00 sw \$6,1\(\$sp\)
+ a8: 3a c2 02 00 sw \$2,2\(\$3\)
+ ac: ca c6 02 00 sw \$6,2\(\$12\)
+ b0: ba c3 01 00 sw \$3,1\(\$11\)
+
+000000b4 <lb_tp>:
+ b4: bc cd 04 00 lb \$tp,4\(\$11\)
+ b8: 8c cd 04 00 lb \$tp,4\(\$8\)
+ bc: 5c c5 04 00 lb \$5,4\(\$5\)
+ c0: ec cf 02 00 lb \$sp,2\(\$gp\)
+ c4: 3c c3 02 00 lb \$3,2\(\$3\)
+
+000000c8 <lh_tp>:
+ c8: 8d c7 02 00 lh \$7,2\(\$8\)
+ cc: 8d c4 03 00 lh \$4,3\(\$8\)
+ d0: fd ce 01 00 lh \$gp,1\(\$sp\)
+ d4: 0d c9 01 00 lh \$9,1\(\$0\)
+ d8: 0d cd 02 00 lh \$tp,2\(\$0\)
+
+000000dc <lw_tp>:
+ dc: 07 48 lw \$8,0x4\(\$sp\)
+ de: 9e cb 04 00 lw \$11,4\(\$9\)
+ e2: 2e ce 01 00 lw \$gp,1\(\$2\)
+ e6: ee c9 02 00 lw \$9,2\(\$gp\)
+ ea: ce c8 01 00 lw \$8,1\(\$12\)
+
+000000ee <lbu_tp>:
+ ee: 9b cc 01 00 lbu \$12,1\(\$9\)
+ f2: 9b cb 01 00 lbu \$11,1\(\$9\)
+ f6: 8b ce 03 00 lbu \$gp,3\(\$8\)
+ fa: fb c0 02 00 lbu \$0,2\(\$sp\)
+ fe: bb cd 01 00 lbu \$tp,1\(\$11\)
+
+00000102 <lhu_tp>:
+ 102: af ce 02 00 lhu \$gp,2\(\$10\)
+ 106: 8f cb 01 00 lhu \$11,1\(\$8\)
+ 10a: 0f c1 01 00 lhu \$1,1\(\$0\)
+ 10e: ff c7 02 00 lhu \$7,2\(\$sp\)
+ 112: 83 8b lhu \$3,0x2\(\$tp\)
+
+00000114 <sb16>:
+ 114: b8 c7 ff ff sb \$7,-1\(\$11\)
+ 118: e8 cd 01 00 sb \$tp,1\(\$gp\)
+ 11c: e8 c3 01 00 sb \$3,1\(\$gp\)
+ 120: 68 ce 02 00 sb \$gp,2\(\$6\)
+ 124: 78 ce 01 00 sb \$gp,1\(\$7\)
+
+00000128 <sh16>:
+ 128: 49 cc ff ff sh \$12,-1\(\$4\)
+ 12c: 19 cf 01 00 sh \$sp,1\(\$1\)
+ 130: c9 c2 fe ff sh \$2,-2\(\$12\)
+ 134: b9 c9 02 00 sh \$9,2\(\$11\)
+ 138: c9 c9 fe ff sh \$9,-2\(\$12\)
+
+0000013c <sw16>:
+ 13c: ea cb ff ff sw \$11,-1\(\$gp\)
+ 140: 06 44 sw \$4,0x4\(\$sp\)
+ 142: 3a c2 fe ff sw \$2,-2\(\$3\)
+ 146: 2a c6 ff ff sw \$6,-1\(\$2\)
+ 14a: da c8 fe ff sw \$8,-2\(\$tp\)
+
+0000014e <lb16>:
+ 14e: 2c ca fe ff lb \$10,-2\(\$2\)
+ 152: bc c3 fe ff lb \$3,-2\(\$11\)
+ 156: 5c cc 01 00 lb \$12,1\(\$5\)
+ 15a: 5c c5 01 00 lb \$5,1\(\$5\)
+ 15e: dc cb 02 00 lb \$11,2\(\$tp\)
+
+00000162 <lh16>:
+ 162: bd cf ff ff lh \$sp,-1\(\$11\)
+ 166: bd cd fe ff lh \$tp,-2\(\$11\)
+ 16a: ad c2 01 00 lh \$2,1\(\$10\)
+ 16e: 7d c8 ff ff lh \$8,-1\(\$7\)
+ 172: bd ce ff ff lh \$gp,-1\(\$11\)
+
+00000176 <lw16>:
+ 176: 5e c0 ff ff lw \$0,-1\(\$5\)
+ 17a: 7e cc fe ff lw \$12,-2\(\$7\)
+ 17e: 3e c1 fe ff lw \$1,-2\(\$3\)
+ 182: 7e c1 02 00 lw \$1,2\(\$7\)
+ 186: 8e c4 01 00 lw \$4,1\(\$8\)
+
+0000018a <lbu16>:
+ 18a: 4b cc ff ff lbu \$12,-1\(\$4\)
+ 18e: bb ce 01 00 lbu \$gp,1\(\$11\)
+ 192: db c1 ff ff lbu \$1,-1\(\$tp\)
+ 196: db c9 ff ff lbu \$9,-1\(\$tp\)
+ 19a: fb c8 01 00 lbu \$8,1\(\$sp\)
+
+0000019e <lhu16>:
+ 19e: ff cd ff ff lhu \$tp,-1\(\$sp\)
+ 1a2: 8f ce 02 00 lhu \$gp,2\(\$8\)
+ 1a6: cf cf ff ff lhu \$sp,-1\(\$12\)
+ 1aa: 0f c3 ff ff lhu \$3,-1\(\$0\)
+ 1ae: cf c3 fe ff lhu \$3,-2\(\$12\)
+
+000001b2 <sw24>:
+ 1b2: 06 eb 00 00 sw \$11,\(0x4\)
+ 1b6: 06 ef 00 00 sw \$sp,\(0x4\)
+ 1ba: 0a e7 00 00 sw \$7,\(0x8\)
+ 1be: 12 ea 00 00 sw \$10,\(0x10\)
+ 1c2: a2 e8 00 00 sw \$8,\(0xa0\)
+
+000001c6 <lw24>:
+ 1c6: 07 e4 00 00 lw \$4,\(0x4\)
+ 1ca: 07 ef 00 00 lw \$sp,\(0x4\)
+ 1ce: 13 e4 00 00 lw \$4,\(0x10\)
+ 1d2: 03 e8 00 00 lw \$8,\(0x0\)
+ 1d6: 0b ed 00 00 lw \$tp,\(0x8\)
+
+000001da <extb>:
+ 1da: 0d 1d extb \$tp
+ 1dc: 0d 1d extb \$tp
+ 1de: 0d 16 extb \$6
+ 1e0: 0d 1e extb \$gp
+ 1e2: 0d 1a extb \$10
+
+000001e4 <exth>:
+ 1e4: 2d 1f exth \$sp
+ 1e6: 2d 12 exth \$2
+ 1e8: 2d 15 exth \$5
+ 1ea: 2d 1a exth \$10
+ 1ec: 2d 14 exth \$4
+
+000001ee <extub>:
+ 1ee: 8d 12 extub \$2
+ 1f0: 8d 1d extub \$tp
+ 1f2: 8d 13 extub \$3
+ 1f4: 8d 19 extub \$9
+ 1f6: 8d 1e extub \$gp
+
+000001f8 <extuh>:
+ 1f8: ad 18 extuh \$8
+ 1fa: ad 18 extuh \$8
+ 1fc: ad 14 extuh \$4
+ 1fe: ad 10 extuh \$0
+ 200: ad 10 extuh \$0
+
+00000202 <ssarb>:
+ 202: 8c 12 ssarb 2\(\$8\)
+ 204: dc 12 ssarb 2\(\$tp\)
+ 206: dc 11 ssarb 1\(\$tp\)
+ 208: 5c 12 ssarb 2\(\$5\)
+ 20a: 9c 10 ssarb 0\(\$9\)
+
+0000020c <mov>:
+ 20c: 30 02 mov \$2,\$3
+ 20e: b0 03 mov \$3,\$11
+ 210: a0 0f mov \$sp,\$10
+ 212: 00 0f mov \$sp,\$0
+ 214: d0 03 mov \$3,\$tp
+
+00000216 <movi8>:
+ 216: ff 5b mov \$11,-1
+ 218: 02 56 mov \$6,2
+ 21a: ff 5f mov \$sp,-1
+ 21c: 01 5f mov \$sp,1
+ 21e: ff 5e mov \$gp,-1
+
+00000220 <movi16>:
+ 220: 00 5f mov \$sp,0
+ 222: 02 50 mov \$0,2
+ 224: ff 58 mov \$8,-1
+ 226: 01 5c mov \$12,1
+ 228: ff 57 mov \$7,-1
+
+0000022a <movu24>:
+ 22a: 01 d2 00 00 movu \$2,0x1
+ 22e: 11 ca 04 00 movu \$10,0x4
+ 232: 11 c9 00 00 movu \$9,0x0
+ 236: 03 d4 00 00 movu \$4,0x3
+ 23a: 11 ce 01 00 movu \$gp,0x1
+
+0000023e <movu16>:
+ 23e: 11 cf 01 00 movu \$sp,0x1
+ 242: 03 d6 00 00 movu \$6,0x3
+ 246: 03 d0 00 00 movu \$0,0x3
+ 24a: 11 ce 03 00 movu \$gp,0x3
+ 24e: 11 ca 02 00 movu \$10,0x2
+
+00000252 <movh>:
+ 252: 21 c8 02 00 movh \$8,0x2
+ 256: 21 cd 01 00 movh \$tp,0x1
+ 25a: 21 ce 02 00 movh \$gp,0x2
+ 25e: 21 cc 00 00 movh \$12,0x0
+ 262: 21 cb 02 00 movh \$11,0x2
+
+00000266 <add3>:
+ 266: 36 9b add3 \$6,\$11,\$3
+ 268: 5e 9d add3 \$gp,\$tp,\$5
+ 26a: 73 9b add3 \$3,\$11,\$7
+ 26c: dd 9e add3 \$tp,\$gp,\$tp
+ 26e: 80 9e add3 \$0,\$gp,\$8
+
+00000270 <add>:
+ 270: 08 6c add \$12,2
+ 272: fc 6c add \$12,-1
+ 274: 04 64 add \$4,1
+ 276: 04 66 add \$6,1
+ 278: 08 66 add \$6,2
+
+0000027a <add3i>:
+ 27a: 04 4b add3 \$11,\$sp,0x4
+ 27c: f0 c4 01 00 add3 \$4,\$sp,1
+ 280: 00 40 add3 \$0,\$sp,0x0
+ 282: f0 cd 03 00 add3 \$tp,\$sp,3
+ 286: 00 4b add3 \$11,\$sp,0x0
+
+00000288 <advck3>:
+ 288: a7 0e advck3 \$0,\$gp,\$10
+ 28a: 07 0d advck3 \$0,\$tp,\$0
+ 28c: d7 0e advck3 \$0,\$gp,\$tp
+ 28e: 87 07 advck3 \$0,\$7,\$8
+ 290: 27 01 advck3 \$0,\$1,\$2
+
+00000292 <sub>:
+ 292: e4 08 sub \$8,\$gp
+ 294: 94 01 sub \$1,\$9
+ 296: 74 0d sub \$tp,\$7
+ 298: 34 0f sub \$sp,\$3
+ 29a: 74 02 sub \$2,\$7
+
+0000029c <sbvck3>:
+ 29c: e5 03 sbvck3 \$0,\$3,\$gp
+ 29e: 75 03 sbvck3 \$0,\$3,\$7
+ 2a0: a5 0a sbvck3 \$0,\$10,\$10
+ 2a2: d5 04 sbvck3 \$0,\$4,\$tp
+ 2a4: f5 0a sbvck3 \$0,\$10,\$sp
+
+000002a6 <neg>:
+ 2a6: 71 0e neg \$gp,\$7
+ 2a8: 71 01 neg \$1,\$7
+ 2aa: b1 02 neg \$2,\$11
+ 2ac: 81 0d neg \$tp,\$8
+ 2ae: d1 0e neg \$gp,\$tp
+
+000002b0 <slt3>:
+ 2b0: 82 0e slt3 \$0,\$gp,\$8
+ 2b2: d2 04 slt3 \$0,\$4,\$tp
+ 2b4: e2 0a slt3 \$0,\$10,\$gp
+ 2b6: 52 0e slt3 \$0,\$gp,\$5
+ 2b8: c2 03 slt3 \$0,\$3,\$12
+
+000002ba <sltu3>:
+ 2ba: 83 02 sltu3 \$0,\$2,\$8
+ 2bc: b3 0e sltu3 \$0,\$gp,\$11
+ 2be: d3 02 sltu3 \$0,\$2,\$tp
+ 2c0: 83 09 sltu3 \$0,\$9,\$8
+ 2c2: 93 06 sltu3 \$0,\$6,\$9
+
+000002c4 <slt3i>:
+ 2c4: 11 66 slt3 \$0,\$6,0x2
+ 2c6: 09 6b slt3 \$0,\$11,0x1
+ 2c8: 01 6f slt3 \$0,\$sp,0x0
+ 2ca: 01 63 slt3 \$0,\$3,0x0
+ 2cc: 01 6d slt3 \$0,\$tp,0x0
+
+000002ce <sltu3i>:
+ 2ce: 25 6e sltu3 \$0,\$gp,0x4
+ 2d0: 1d 6d sltu3 \$0,\$tp,0x3
+ 2d2: 0d 63 sltu3 \$0,\$3,0x1
+ 2d4: 05 6c sltu3 \$0,\$12,0x0
+ 2d6: 1d 61 sltu3 \$0,\$1,0x3
+
+000002d8 <sl1ad3>:
+ 2d8: e6 28 sl1ad3 \$0,\$8,\$gp
+ 2da: 26 24 sl1ad3 \$0,\$4,\$2
+ 2dc: c6 2f sl1ad3 \$0,\$sp,\$12
+ 2de: 16 29 sl1ad3 \$0,\$9,\$1
+ 2e0: 26 28 sl1ad3 \$0,\$8,\$2
+
+000002e2 <sl2ad3>:
+ 2e2: d7 28 sl2ad3 \$0,\$8,\$tp
+ 2e4: 37 22 sl2ad3 \$0,\$2,\$3
+ 2e6: 97 28 sl2ad3 \$0,\$8,\$9
+ 2e8: c7 27 sl2ad3 \$0,\$7,\$12
+ 2ea: c7 24 sl2ad3 \$0,\$4,\$12
+
+000002ec <add3x>:
+ 2ec: b0 cd 01 00 add3 \$tp,\$11,1
+ 2f0: 40 cd ff ff add3 \$tp,\$4,-1
+ 2f4: d0 c2 01 00 add3 \$2,\$tp,1
+ 2f8: e0 c3 01 00 add3 \$3,\$gp,1
+ 2fc: f0 ca 02 00 add3 \$10,\$sp,2
+
+00000300 <slt3x>:
+ 300: 12 c8 ff ff slt3 \$8,\$1,-1
+ 304: 32 c0 fe ff slt3 \$0,\$3,-2
+ 308: f2 c9 ff ff slt3 \$9,\$sp,-1
+ 30c: 82 c3 02 00 slt3 \$3,\$8,2
+ 310: e2 cd 00 00 slt3 \$tp,\$gp,0
+
+00000314 <sltu3x>:
+ 314: b3 cf 02 00 sltu3 \$sp,\$11,0x2
+ 318: 03 c6 01 00 sltu3 \$6,\$0,0x1
+ 31c: b3 c9 03 00 sltu3 \$9,\$11,0x3
+ 320: 05 64 sltu3 \$0,\$4,0x0
+ 322: e3 cd 04 00 sltu3 \$tp,\$gp,0x4
+
+00000326 <or>:
+ 326: e0 1f or \$sp,\$gp
+ 328: 30 18 or \$8,\$3
+ 32a: f0 10 or \$0,\$sp
+ 32c: 00 1d or \$tp,\$0
+ 32e: 60 18 or \$8,\$6
+
+00000330 <and>:
+ 330: f1 1f and \$sp,\$sp
+ 332: e1 16 and \$6,\$gp
+ 334: 21 14 and \$4,\$2
+ 336: 81 15 and \$5,\$8
+ 338: e1 17 and \$7,\$gp
+
+0000033a <xor>:
+ 33a: c2 11 xor \$1,\$12
+ 33c: d2 1c xor \$12,\$tp
+ 33e: 82 1a xor \$10,\$8
+ 340: b2 1f xor \$sp,\$11
+ 342: 82 1c xor \$12,\$8
+
+00000344 <nor>:
+ 344: 53 19 nor \$9,\$5
+ 346: 23 18 nor \$8,\$2
+ 348: 93 1f nor \$sp,\$9
+ 34a: f3 15 nor \$5,\$sp
+ 34c: e3 1f nor \$sp,\$gp
+
+0000034e <or3>:
+ 34e: f4 cd 02 00 or3 \$tp,\$sp,0x2
+ 352: d4 cf 03 00 or3 \$sp,\$tp,0x3
+ 356: a4 c0 04 00 or3 \$0,\$10,0x4
+ 35a: f4 c9 03 00 or3 \$9,\$sp,0x3
+ 35e: f4 c9 00 00 or3 \$9,\$sp,0x0
+
+00000362 <and3>:
+ 362: 85 c5 01 00 and3 \$5,\$8,0x1
+ 366: e5 cb 03 00 and3 \$11,\$gp,0x3
+ 36a: 05 c6 00 00 and3 \$6,\$0,0x0
+ 36e: f5 cf 00 00 and3 \$sp,\$sp,0x0
+ 372: a5 c1 03 00 and3 \$1,\$10,0x3
+
+00000376 <xor3>:
+ 376: 06 c0 02 00 xor3 \$0,\$0,0x2
+ 37a: 66 cf 00 00 xor3 \$sp,\$6,0x0
+ 37e: 56 cd 00 00 xor3 \$tp,\$5,0x0
+ 382: 76 cf 00 00 xor3 \$sp,\$7,0x0
+ 386: f6 cf 02 00 xor3 \$sp,\$sp,0x2
+
+0000038a <sra>:
+ 38a: 1d 24 sra \$4,\$1
+ 38c: fd 28 sra \$8,\$sp
+ 38e: 1d 21 sra \$1,\$1
+ 390: 5d 20 sra \$0,\$5
+ 392: 1d 29 sra \$9,\$1
+
+00000394 <srl>:
+ 394: bc 22 srl \$2,\$11
+ 396: 7c 2f srl \$sp,\$7
+ 398: 7c 21 srl \$1,\$7
+ 39a: dc 23 srl \$3,\$tp
+ 39c: 1c 2e srl \$gp,\$1
+
+0000039e <sll>:
+ 39e: 0e 2b sll \$11,\$0
+ 3a0: 8e 2d sll \$tp,\$8
+ 3a2: 9e 28 sll \$8,\$9
+ 3a4: fe 2d sll \$tp,\$sp
+ 3a6: fe 2f sll \$sp,\$sp
+
+000003a8 <srai>:
+ 3a8: 13 61 sra \$1,0x2
+ 3aa: 1b 6f sra \$sp,0x3
+ 3ac: 1b 6f sra \$sp,0x3
+ 3ae: 23 66 sra \$6,0x4
+ 3b0: 1b 6f sra \$sp,0x3
+
+000003b2 <srli>:
+ 3b2: 02 6a srl \$10,0x0
+ 3b4: 1a 69 srl \$9,0x3
+ 3b6: 22 66 srl \$6,0x4
+ 3b8: 12 6a srl \$10,0x2
+ 3ba: 1a 68 srl \$8,0x3
+
+000003bc <slli>:
+ 3bc: 06 60 sll \$0,0x0
+ 3be: 06 64 sll \$4,0x0
+ 3c0: 16 6d sll \$tp,0x2
+ 3c2: 16 6b sll \$11,0x2
+ 3c4: 06 66 sll \$6,0x0
+
+000003c6 <sll3>:
+ 3c6: 27 6d sll3 \$0,\$tp,0x4
+ 3c8: 07 6e sll3 \$0,\$gp,0x0
+ 3ca: 17 68 sll3 \$0,\$8,0x2
+ 3cc: 17 63 sll3 \$0,\$3,0x2
+ 3ce: 07 68 sll3 \$0,\$8,0x0
+
+000003d0 <fsft>:
+ 3d0: af 2e fsft \$gp,\$10
+ 3d2: 9f 2e fsft \$gp,\$9
+ 3d4: df 2f fsft \$sp,\$tp
+ 3d6: 3f 2b fsft \$11,\$3
+ 3d8: 3f 25 fsft \$5,\$3
+
+000003da <bra>:
+ 3da: 02 b0 bra 3dc <bra\+0x2>
+ 3dc: fe bf bra 3da <bra>
+ 3de: 02 b0 bra 3e0 <bra\+0x6>
+ 3e0: 00 b0 bra 3e0 <bra\+0x6>
+ 3e2: 02 b0 bra 3e4 <beqz>
+
+000003e4 <beqz>:
+ 3e4: fe a1 beqz \$1,3e2 <bra\+0x8>
+ 3e6: 02 af beqz \$sp,3e8 <beqz\+0x4>
+ 3e8: 04 a4 beqz \$4,3ec <beqz\+0x8>
+ 3ea: 00 a4 beqz \$4,3ea <beqz\+0x6>
+ 3ec: fe a9 beqz \$9,3ea <beqz\+0x6>
+
+000003ee <bnez>:
+ 3ee: 03 a8 bnez \$8,3f0 <bnez\+0x2>
+ 3f0: 03 ad bnez \$tp,3f2 <bnez\+0x4>
+ 3f2: 01 ae bnez \$gp,3f2 <bnez\+0x4>
+ 3f4: 03 a6 bnez \$6,3f6 <bnez\+0x8>
+ 3f6: fd a8 bnez \$8,3f2 <bnez\+0x4>
+
+000003f8 <beqi>:
+ 3f8: 30 ed 00 00 beqi \$tp,0x3,3f8 <beqi>
+ 3fc: 40 e0 ff ff beqi \$0,0x4,3fa <beqi\+0x2>
+ 400: 40 ef ff ff beqi \$sp,0x4,3fe <beqi\+0x6>
+ 404: 20 ed 00 00 beqi \$tp,0x2,404 <beqi\+0xc>
+ 408: 20 e4 fc ff beqi \$4,0x2,400 <beqi\+0x8>
+
+0000040c <bnei>:
+ 40c: 14 e8 00 00 bnei \$8,0x1,40c <bnei>
+ 410: 14 e5 01 00 bnei \$5,0x1,412 <bnei\+0x6>
+ 414: 04 e5 04 00 bnei \$5,0x0,41c <bnei\+0x10>
+ 418: 44 e9 ff ff bnei \$9,0x4,416 <bnei\+0xa>
+ 41c: 44 e0 fc ff bnei \$0,0x4,414 <bnei\+0x8>
+
+00000420 <blti>:
+ 420: 3c e7 00 00 blti \$7,0x3,420 <blti>
+ 424: 1c e1 00 00 blti \$1,0x1,424 <blti\+0x4>
+ 428: 2c e8 01 00 blti \$8,0x2,42a <blti\+0xa>
+ 42c: 2c eb 01 00 blti \$11,0x2,42e <blti\+0xe>
+ 430: 3c ef ff ff blti \$sp,0x3,42e <blti\+0xe>
+
+00000434 <bgei>:
+ 434: 38 e4 fc ff bgei \$4,0x3,42c <blti\+0xc>
+ 438: 08 e7 01 00 bgei \$7,0x0,43a <bgei\+0x6>
+ 43c: 18 ed 00 00 bgei \$tp,0x1,43c <bgei\+0x8>
+ 440: 28 e5 ff ff bgei \$5,0x2,43e <bgei\+0xa>
+ 444: 48 ec fc ff bgei \$12,0x4,43c <bgei\+0x8>
+
+00000448 <beq>:
+ 448: 21 e7 ff ff beq \$7,\$2,446 <bgei\+0x12>
+ 44c: 31 e1 fc ff beq \$1,\$3,444 <bgei\+0x10>
+ 450: 01 e2 01 00 beq \$2,\$0,452 <beq\+0xa>
+ 454: 81 ef 01 00 beq \$sp,\$8,456 <beq\+0xe>
+ 458: 01 e3 00 00 beq \$3,\$0,458 <beq\+0x10>
+
+0000045c <bne>:
+ 45c: 35 e6 00 00 bne \$6,\$3,45c <bne>
+ 460: 35 ef fc ff bne \$sp,\$3,458 <beq\+0x10>
+ 464: 05 e8 01 00 bne \$8,\$0,466 <bne\+0xa>
+ 468: f5 ee 04 00 bne \$gp,\$sp,470 <bsr12>
+ 46c: 45 ef 01 00 bne \$sp,\$4,46e <bne\+0x12>
+
+00000470 <bsr12>:
+ 470: 03 b0 bsr 472 <bsr12\+0x2>
+ 472: f9 bf bsr 46a <bne\+0xe>
+ 474: f1 bf bsr 464 <bne\+0x8>
+ 476: ff bf bsr 474 <bsr12\+0x4>
+ 478: f9 bf bsr 470 <bsr12>
+
+0000047a <bsr24>:
+ 47a: 05 b0 bsr 47e <bsr24\+0x4>
+ 47c: ff bf bsr 47a <bsr24>
+ 47e: fd bf bsr 47a <bsr24>
+ 480: 01 b0 bsr 480 <bsr24\+0x6>
+ 482: 03 b0 bsr 484 <jmp>
+
+00000484 <jmp>:
+ 484: 2e 10 jmp \$2
+ 486: de 10 jmp \$tp
+ 488: 5e 10 jmp \$5
+ 48a: fe 10 jmp \$sp
+ 48c: 8e 10 jmp \$8
+
+0000048e <jmp24>:
+ 48e: 28 d8 00 00 jmp 4 <sb\+0x4>
+ 492: 18 d8 00 00 jmp 2 <sb\+0x2>
+ 496: 08 d8 00 00 jmp 0 <sb>
+ 49a: 18 d8 00 00 jmp 2 <sb\+0x2>
+ 49e: 28 d8 00 00 jmp 4 <sb\+0x4>
+
+000004a2 <jsr>:
+ 4a2: ff 10 jsr \$sp
+ 4a4: df 10 jsr \$tp
+ 4a6: df 10 jsr \$tp
+ 4a8: 6f 10 jsr \$6
+ 4aa: 6f 10 jsr \$6
+
+000004ac <ret>:
+ 4ac: 02 70 ret
+
+000004ae <repeat>:
+ 4ae: 09 e4 01 00 repeat \$4,4b0 <repeat\+0x2>
+ 4b2: 09 e8 02 00 repeat \$8,4b6 <repeat\+0x8>
+ 4b6: 09 e0 04 00 repeat \$0,4be <repeat\+0x10>
+ 4ba: 09 e6 01 00 repeat \$6,4bc <repeat\+0xe>
+ 4be: 09 e4 01 00 repeat \$4,4c0 <repeat\+0x12>
+
+000004c2 <erepeat>:
+ 4c2: 19 e0 01 00 erepeat 4c4 <erepeat\+0x2>
+ 4c6: 19 e0 00 00 erepeat 4c6 <erepeat\+0x4>
+ 4ca: 19 e0 01 00 erepeat 4cc <erepeat\+0xa>
+ 4ce: 19 e0 ff ff erepeat 4cc <erepeat\+0xa>
+ 4d2: 19 e0 00 00 erepeat 4d2 <erepeat\+0x10>
+
+000004d6 <stc>:
+ 4d6: e8 7d stc \$tp,\$mb1
+ 4d8: c9 7d stc \$tp,\$ccfg
+ 4da: 89 7b stc \$11,\$dbg
+ 4dc: c9 7a stc \$10,\$ccfg
+ 4de: 39 79 stc \$9,\$epc
+
+000004e0 <ldc>:
+ 4e0: 8a 7d ldc \$tp,\$lo
+ 4e2: 7b 78 ldc \$8,\$npc
+ 4e4: ca 79 ldc \$9,\$mb0
+ 4e6: 2a 7f ldc \$sp,\$sar
+ 4e8: cb 79 ldc \$9,\$ccfg
+
+000004ea <di>:
+ 4ea: 00 70 di
+
+000004ec <ei>:
+ 4ec: 10 70 ei
+
+000004ee <reti>:
+ 4ee: 12 70 reti
+
+000004f0 <halt>:
+ 4f0: 22 70 halt
+
+000004f2 <swi>:
+ 4f2: 26 70 swi 0x2
+ 4f4: 06 70 swi 0x0
+ 4f6: 26 70 swi 0x2
+ 4f8: 36 70 swi 0x3
+ 4fa: 16 70 swi 0x1
+
+000004fc <break>:
+ 4fc: 32 70 break
+
+000004fe <syncm>:
+ 4fe: 11 70 syncm
+
+00000500 <stcb>:
+ 500: 04 f5 04 00 stcb \$5,0x4
+ 504: 04 f5 01 00 stcb \$5,0x1
+ 508: 04 fe 00 00 stcb \$gp,0x0
+ 50c: 04 ff 04 00 stcb \$sp,0x4
+ 510: 04 fb 02 00 stcb \$11,0x2
+
+00000514 <ldcb>:
+ 514: 14 f2 03 00 ldcb \$2,0x3
+ 518: 14 f2 04 00 ldcb \$2,0x4
+ 51c: 14 f9 01 00 ldcb \$9,0x1
+ 520: 14 fa 04 00 ldcb \$10,0x4
+ 524: 14 f1 04 00 ldcb \$1,0x4
+
+00000528 <bsetm>:
+ 528: a0 20 bsetm \(\$10\),0x0
+ 52a: f0 20 bsetm \(\$sp\),0x0
+ 52c: 10 22 bsetm \(\$1\),0x2
+ 52e: f0 24 bsetm \(\$sp\),0x4
+ 530: 80 24 bsetm \(\$8\),0x4
+
+00000532 <bclrm>:
+ 532: 51 20 bclrm \(\$5\),0x0
+ 534: 51 22 bclrm \(\$5\),0x2
+ 536: 81 20 bclrm \(\$8\),0x0
+ 538: 91 22 bclrm \(\$9\),0x2
+ 53a: 51 23 bclrm \(\$5\),0x3
+
+0000053c <bnotm>:
+ 53c: e2 24 bnotm \(\$gp\),0x4
+ 53e: b2 24 bnotm \(\$11\),0x4
+ 540: a2 20 bnotm \(\$10\),0x0
+ 542: d2 24 bnotm \(\$tp\),0x4
+ 544: 82 20 bnotm \(\$8\),0x0
+
+00000546 <btstm>:
+ 546: e3 20 btstm \$0,\(\$gp\),0x0
+ 548: e3 21 btstm \$0,\(\$gp\),0x1
+ 54a: b3 20 btstm \$0,\(\$11\),0x0
+ 54c: e3 23 btstm \$0,\(\$gp\),0x3
+ 54e: 83 22 btstm \$0,\(\$8\),0x2
+
+00000550 <tas>:
+ 550: d4 27 tas \$7,\(\$tp\)
+ 552: c4 27 tas \$7,\(\$12\)
+ 554: 84 23 tas \$3,\(\$8\)
+ 556: 54 22 tas \$2,\(\$5\)
+ 558: a4 26 tas \$6,\(\$10\)
+
+0000055a <cache>:
+ 55a: d4 71 cache 0x1,\(\$tp\)
+ 55c: c4 73 cache 0x3,\(\$12\)
+ 55e: 94 73 cache 0x3,\(\$9\)
+ 560: 24 74 cache 0x4,\(\$2\)
+ 562: 74 74 cache 0x4,\(\$7\)
+
+00000564 <mul>:
+ 564: e4 18 mul \$8,\$gp
+ 566: 94 12 mul \$2,\$9
+ 568: f4 1e mul \$gp,\$sp
+ 56a: 74 19 mul \$9,\$7
+ 56c: b4 17 mul \$7,\$11
+
+0000056e <mulu>:
+ 56e: 55 12 mulu \$2,\$5
+ 570: e5 16 mulu \$6,\$gp
+ 572: f5 1e mulu \$gp,\$sp
+ 574: e5 1b mulu \$11,\$gp
+ 576: 95 13 mulu \$3,\$9
+
+00000578 <mulr>:
+ 578: 66 1c mulr \$12,\$6
+ 57a: 86 1d mulr \$tp,\$8
+ 57c: a6 17 mulr \$7,\$10
+ 57e: 16 1e mulr \$gp,\$1
+ 580: f6 10 mulr \$0,\$sp
+
+00000582 <mulru>:
+ 582: 27 14 mulru \$4,\$2
+ 584: 17 1e mulru \$gp,\$1
+ 586: 47 1f mulru \$sp,\$4
+ 588: 67 1a mulru \$10,\$6
+ 58a: e7 10 mulru \$0,\$gp
+
+0000058c <madd>:
+ 58c: b1 f4 04 30 madd \$4,\$11
+ 590: e1 ff 04 30 madd \$sp,\$gp
+ 594: f1 fe 04 30 madd \$gp,\$sp
+ 598: d1 f4 04 30 madd \$4,\$tp
+ 59c: e1 f1 04 30 madd \$1,\$gp
+
+000005a0 <maddu>:
+ 5a0: 11 f0 05 30 maddu \$0,\$1
+ 5a4: 61 f7 05 30 maddu \$7,\$6
+ 5a8: 51 f9 05 30 maddu \$9,\$5
+ 5ac: f1 fe 05 30 maddu \$gp,\$sp
+ 5b0: d1 f7 05 30 maddu \$7,\$tp
+
+000005b4 <maddr>:
+ 5b4: 81 f6 06 30 maddr \$6,\$8
+ 5b8: e1 f9 06 30 maddr \$9,\$gp
+ 5bc: e1 f8 06 30 maddr \$8,\$gp
+ 5c0: 21 f3 06 30 maddr \$3,\$2
+ 5c4: b1 f1 06 30 maddr \$1,\$11
+
+000005c8 <maddru>:
+ 5c8: 31 fa 07 30 maddru \$10,\$3
+ 5cc: c1 ff 07 30 maddru \$sp,\$12
+ 5d0: 81 f8 07 30 maddru \$8,\$8
+ 5d4: 31 fe 07 30 maddru \$gp,\$3
+ 5d8: f1 f8 07 30 maddru \$8,\$sp
+
+000005dc <div>:
+ 5dc: 38 19 div \$9,\$3
+ 5de: e8 14 div \$4,\$gp
+ 5e0: c8 12 div \$2,\$12
+ 5e2: d8 18 div \$8,\$tp
+ 5e4: 68 1d div \$tp,\$6
+
+000005e6 <divu>:
+ 5e6: 59 19 divu \$9,\$5
+ 5e8: d9 18 divu \$8,\$tp
+ 5ea: e9 10 divu \$0,\$gp
+ 5ec: 59 19 divu \$9,\$5
+ 5ee: 59 10 divu \$0,\$5
+
+000005f0 <dret>:
+ 5f0: 13 70 dret
+
+000005f2 <dbreak>:
+ 5f2: 33 70 dbreak
+
+000005f4 <ldz>:
+ 5f4: 41 fe 00 00 ldz \$gp,\$4
+ 5f8: b1 fa 00 00 ldz \$10,\$11
+ 5fc: 91 f9 00 00 ldz \$9,\$9
+ 600: d1 ff 00 00 ldz \$sp,\$tp
+ 604: 31 fe 00 00 ldz \$gp,\$3
+
+00000608 <abs>:
+ 608: 91 ff 03 00 abs \$sp,\$9
+ 60c: 41 f5 03 00 abs \$5,\$4
+ 610: d1 fd 03 00 abs \$tp,\$tp
+ 614: 31 f0 03 00 abs \$0,\$3
+ 618: e1 f3 03 00 abs \$3,\$gp
+
+0000061c <ave>:
+ 61c: a1 fb 02 00 ave \$11,\$10
+ 620: a1 f8 02 00 ave \$8,\$10
+ 624: 21 fe 02 00 ave \$gp,\$2
+ 628: c1 fa 02 00 ave \$10,\$12
+ 62c: 81 ff 02 00 ave \$sp,\$8
+
+00000630 <min>:
+ 630: 31 f8 04 00 min \$8,\$3
+ 634: 01 f7 04 00 min \$7,\$0
+ 638: 21 f2 04 00 min \$2,\$2
+ 63c: 61 f5 04 00 min \$5,\$6
+ 640: 51 fb 04 00 min \$11,\$5
+
+00000644 <max>:
+ 644: f1 fb 05 00 max \$11,\$sp
+ 648: 01 fe 05 00 max \$gp,\$0
+ 64c: f1 fc 05 00 max \$12,\$sp
+ 650: 21 fe 05 00 max \$gp,\$2
+ 654: f1 fe 05 00 max \$gp,\$sp
+
+00000658 <minu>:
+ 658: 81 fb 06 00 minu \$11,\$8
+ 65c: 51 f7 06 00 minu \$7,\$5
+ 660: e1 f8 06 00 minu \$8,\$gp
+ 664: 41 fb 06 00 minu \$11,\$4
+ 668: f1 f2 06 00 minu \$2,\$sp
+
+0000066c <maxu>:
+ 66c: 31 f3 07 00 maxu \$3,\$3
+ 670: 01 fd 07 00 maxu \$tp,\$0
+ 674: 81 f4 07 00 maxu \$4,\$8
+ 678: 21 fe 07 00 maxu \$gp,\$2
+ 67c: 81 fc 07 00 maxu \$12,\$8
+
+00000680 <clip>:
+ 680: 01 fa 08 10 clip \$10,0x1
+ 684: 01 ff 20 10 clip \$sp,0x4
+ 688: 01 f4 18 10 clip \$4,0x3
+ 68c: 01 ff 18 10 clip \$sp,0x3
+ 690: 01 f1 00 10 clip \$1,0x0
+
+00000694 <clipu>:
+ 694: 01 fa 21 10 clipu \$10,0x4
+ 698: 01 fd 09 10 clipu \$tp,0x1
+ 69c: 01 f5 21 10 clipu \$5,0x4
+ 6a0: 01 fe 01 10 clipu \$gp,0x0
+ 6a4: 01 f5 09 10 clipu \$5,0x1
+
+000006a8 <sadd>:
+ 6a8: 01 f5 08 00 sadd \$5,\$0
+ 6ac: 31 ff 08 00 sadd \$sp,\$3
+ 6b0: a1 f0 08 00 sadd \$0,\$10
+ 6b4: c1 ff 08 00 sadd \$sp,\$12
+ 6b8: 21 f4 08 00 sadd \$4,\$2
+
+000006bc <ssub>:
+ 6bc: a1 f1 0a 00 ssub \$1,\$10
+ 6c0: 71 f4 0a 00 ssub \$4,\$7
+ 6c4: 31 f8 0a 00 ssub \$8,\$3
+ 6c8: e1 f7 0a 00 ssub \$7,\$gp
+ 6cc: 41 fd 0a 00 ssub \$tp,\$4
+
+000006d0 <saddu>:
+ 6d0: e1 f9 09 00 saddu \$9,\$gp
+ 6d4: a1 f0 09 00 saddu \$0,\$10
+ 6d8: c1 f7 09 00 saddu \$7,\$12
+ 6dc: f1 f5 09 00 saddu \$5,\$sp
+ 6e0: 31 fd 09 00 saddu \$tp,\$3
+
+000006e4 <ssubu>:
+ 6e4: e1 ff 0b 00 ssubu \$sp,\$gp
+ 6e8: f1 f0 0b 00 ssubu \$0,\$sp
+ 6ec: a1 f3 0b 00 ssubu \$3,\$10
+ 6f0: d1 ff 0b 00 ssubu \$sp,\$tp
+ 6f4: 91 f2 0b 00 ssubu \$2,\$9
+
+000006f8 <swcp>:
+ 6f8: d8 33 swcp \$c3,\(\$tp\)
+ 6fa: d8 3f swcp \$c15,\(\$tp\)
+ 6fc: 08 3d swcp \$c13,\(\$0\)
+ 6fe: c8 3c swcp \$c12,\(\$12\)
+ 700: e8 39 swcp \$c9,\(\$gp\)
+
+00000702 <lwcp>:
+ 702: 39 37 lwcp \$c7,\(\$3\)
+ 704: 39 36 lwcp \$c6,\(\$3\)
+ 706: 29 30 lwcp \$c0,\(\$2\)
+ 708: 89 38 lwcp \$c8,\(\$8\)
+ 70a: d9 3b lwcp \$c11,\(\$tp\)
+
+0000070c <smcp>:
+ 70c: 9a 3e smcp \$c14,\(\$9\)
+ 70e: 8a 32 smcp \$c2,\(\$8\)
+ 710: fa 3e smcp \$c14,\(\$sp\)
+ 712: 8a 3a smcp \$c10,\(\$8\)
+ 714: 8a 32 smcp \$c2,\(\$8\)
+
+00000716 <lmcp>:
+ 716: 1b 3b lmcp \$c11,\(\$1\)
+ 718: 8b 38 lmcp \$c8,\(\$8\)
+ 71a: db 3b lmcp \$c11,\(\$tp\)
+ 71c: 0b 38 lmcp \$c8,\(\$0\)
+ 71e: eb 38 lmcp \$c8,\(\$gp\)
+
+00000720 <swcpi>:
+ 720: 00 37 swcpi \$c7,\(\$0\+\)
+ 722: e0 36 swcpi \$c6,\(\$gp\+\)
+ 724: 80 3c swcpi \$c12,\(\$8\+\)
+ 726: f0 3e swcpi \$c14,\(\$sp\+\)
+ 728: 00 36 swcpi \$c6,\(\$0\+\)
+
+0000072a <lwcpi>:
+ 72a: 21 38 lwcpi \$c8,\(\$2\+\)
+ 72c: 01 39 lwcpi \$c9,\(\$0\+\)
+ 72e: e1 33 lwcpi \$c3,\(\$gp\+\)
+ 730: 51 3d lwcpi \$c13,\(\$5\+\)
+ 732: e1 3b lwcpi \$c11,\(\$gp\+\)
+
+00000734 <smcpi>:
+ 734: 22 38 smcpi \$c8,\(\$2\+\)
+ 736: 92 3b smcpi \$c11,\(\$9\+\)
+ 738: 32 34 smcpi \$c4,\(\$3\+\)
+ 73a: 22 3e smcpi \$c14,\(\$2\+\)
+ 73c: 32 39 smcpi \$c9,\(\$3\+\)
+
+0000073e <lmcpi>:
+ 73e: e3 36 lmcpi \$c6,\(\$gp\+\)
+ 740: 53 39 lmcpi \$c9,\(\$5\+\)
+ 742: 63 3a lmcpi \$c10,\(\$6\+\)
+ 744: 63 31 lmcpi \$c1,\(\$6\+\)
+ 746: 83 32 lmcpi \$c2,\(\$8\+\)
+
+00000748 <swcp16>:
+ 748: 2c f0 ff ff swcp \$c0,-1\(\$2\)
+ 74c: ac f5 01 00 swcp \$c5,1\(\$10\)
+ 750: cc f8 02 00 swcp \$c8,2\(\$12\)
+ 754: 1c fe ff ff swcp \$c14,-1\(\$1\)
+ 758: 3c fc 02 00 swcp \$c12,2\(\$3\)
+
+0000075c <lwcp16>:
+ 75c: 5d f8 ff ff lwcp \$c8,-1\(\$5\)
+ 760: fd fc 01 00 lwcp \$c12,1\(\$sp\)
+ 764: 0d f1 02 00 lwcp \$c1,2\(\$0\)
+ 768: dd f4 01 00 lwcp \$c4,1\(\$tp\)
+ 76c: bd f6 02 00 lwcp \$c6,2\(\$11\)
+
+00000770 <smcp16>:
+ 770: ae f9 ff ff smcp \$c9,-1\(\$10\)
+ 774: ee fe 01 00 smcp \$c14,1\(\$gp\)
+ 778: fe f3 02 00 smcp \$c3,2\(\$sp\)
+ 77c: 8e ff fe ff smcp \$c15,-2\(\$8\)
+ 780: de fd 01 00 smcp \$c13,1\(\$tp\)
+
+00000784 <lmcp16>:
+ 784: ff f0 01 00 lmcp \$c0,1\(\$sp\)
+ 788: 8f ff 01 00 lmcp \$c15,1\(\$8\)
+ 78c: 8f f2 ff ff lmcp \$c2,-1\(\$8\)
+ 790: 8f fe 01 00 lmcp \$c14,1\(\$8\)
+ 794: af f1 ff ff lmcp \$c1,-1\(\$10\)
+
+00000798 <sbcpa>:
+ 798: f5 fe 02 00 sbcpa \$c14,\(\$sp\+\),2
+ 79c: 45 f2 fe 00 sbcpa \$c2,\(\$4\+\),-2
+ 7a0: 15 f8 00 00 sbcpa \$c8,\(\$1\+\),0
+ 7a4: 35 fb 00 00 sbcpa \$c11,\(\$3\+\),0
+ 7a8: e5 f9 fe 00 sbcpa \$c9,\(\$gp\+\),-2
+
+000007ac <lbcpa>:
+ 7ac: 25 f7 fe 40 lbcpa \$c7,\(\$2\+\),-2
+ 7b0: f5 fc 02 40 lbcpa \$c12,\(\$sp\+\),2
+ 7b4: 45 f5 fe 40 lbcpa \$c5,\(\$4\+\),-2
+ 7b8: 45 f7 fe 40 lbcpa \$c7,\(\$4\+\),-2
+ 7bc: f5 f8 00 40 lbcpa \$c8,\(\$sp\+\),0
+
+000007c0 <shcpa>:
+ 7c0: e5 f0 00 10 shcpa \$c0,\(\$gp\+\),0
+ 7c4: f5 fc 10 10 shcpa \$c12,\(\$sp\+\),16
+ 7c8: 45 f1 04 10 shcpa \$c1,\(\$4\+\),4
+ 7cc: 45 f5 e0 10 shcpa \$c5,\(\$4\+\),-32
+ 7d0: f5 f1 00 10 shcpa \$c1,\(\$sp\+\),0
+
+000007d4 <lhcpa>:
+ 7d4: 45 f4 00 50 lhcpa \$c4,\(\$4\+\),0
+ 7d8: 55 f6 30 50 lhcpa \$c6,\(\$5\+\),48
+ 7dc: 65 f3 cc 50 lhcpa \$c3,\(\$6\+\),-52
+ 7e0: 65 f8 e8 50 lhcpa \$c8,\(\$6\+\),-24
+ 7e4: 95 f0 00 50 lhcpa \$c0,\(\$9\+\),0
+
+000007e8 <swcpa>:
+ 7e8: 95 f1 10 20 swcpa \$c1,\(\$9\+\),16
+ 7ec: f5 f7 20 20 swcpa \$c7,\(\$sp\+\),32
+ 7f0: c5 f3 30 20 swcpa \$c3,\(\$12\+\),48
+ 7f4: 95 fa 08 20 swcpa \$c10,\(\$9\+\),8
+ 7f8: 85 fe 04 20 swcpa \$c14,\(\$8\+\),4
+
+000007fc <lwcpa>:
+ 7fc: e5 f6 f8 60 lwcpa \$c6,\(\$gp\+\),-8
+ 800: 75 f4 04 60 lwcpa \$c4,\(\$7\+\),4
+ 804: e5 fb f0 60 lwcpa \$c11,\(\$gp\+\),-16
+ 808: f5 fa e0 60 lwcpa \$c10,\(\$sp\+\),-32
+ 80c: 25 f2 08 60 lwcpa \$c2,\(\$2\+\),8
+
+00000810 <smcpa>:
+ 810: f5 fd f8 30 smcpa \$c13,\(\$sp\+\),-8
+ 814: 75 f6 f8 30 smcpa \$c6,\(\$7\+\),-8
+ 818: 35 f5 10 30 smcpa \$c5,\(\$3\+\),16
+ 81c: f5 fd 10 30 smcpa \$c13,\(\$sp\+\),16
+ 820: c5 f3 30 30 smcpa \$c3,\(\$12\+\),48
+
+00000824 <lmcpa>:
+ 824: 45 f9 00 70 lmcpa \$c9,\(\$4\+\),0
+ 828: f5 f3 f0 70 lmcpa \$c3,\(\$sp\+\),-16
+ 82c: d5 ff 08 70 lmcpa \$c15,\(\$tp\+\),8
+ 830: 85 f8 f8 70 lmcpa \$c8,\(\$8\+\),-8
+ 834: 95 fa 00 70 lmcpa \$c10,\(\$9\+\),0
+
+00000838 <sbcpm0>:
+ 838: d5 fa 08 08 sbcpm0 \$c10,\(\$tp\+\),8
+ 83c: 55 fd f8 08 sbcpm0 \$c13,\(\$5\+\),-8
+ 840: 55 f4 f8 08 sbcpm0 \$c4,\(\$5\+\),-8
+ 844: d5 fa 10 08 sbcpm0 \$c10,\(\$tp\+\),16
+ 848: 55 f4 e8 08 sbcpm0 \$c4,\(\$5\+\),-24
+
+0000084c <lbcpm0>:
+ 84c: 45 f0 00 48 lbcpm0 \$c0,\(\$4\+\),0
+ 850: 75 f9 f8 48 lbcpm0 \$c9,\(\$7\+\),-8
+ 854: 85 fc 18 48 lbcpm0 \$c12,\(\$8\+\),24
+ 858: c5 f8 10 48 lbcpm0 \$c8,\(\$12\+\),16
+ 85c: 85 f7 10 48 lbcpm0 \$c7,\(\$8\+\),16
+
+00000860 <shcpm0>:
+ 860: d5 f2 02 18 shcpm0 \$c2,\(\$tp\+\),2
+ 864: f5 f7 fe 18 shcpm0 \$c7,\(\$sp\+\),-2
+ 868: 25 f8 02 18 shcpm0 \$c8,\(\$2\+\),2
+ 86c: 55 fd 00 18 shcpm0 \$c13,\(\$5\+\),0
+ 870: e5 f3 08 18 shcpm0 \$c3,\(\$gp\+\),8
+
+00000874 <lhcpm0>:
+ 874: 45 f7 08 58 lhcpm0 \$c7,\(\$4\+\),8
+ 878: 35 f3 fe 58 lhcpm0 \$c3,\(\$3\+\),-2
+ 87c: 15 f3 00 58 lhcpm0 \$c3,\(\$1\+\),0
+ 880: e5 f2 00 58 lhcpm0 \$c2,\(\$gp\+\),0
+ 884: 65 fc 02 58 lhcpm0 \$c12,\(\$6\+\),2
+
+00000888 <swcpm0>:
+ 888: 85 f8 20 28 swcpm0 \$c8,\(\$8\+\),32
+ 88c: f5 f9 00 28 swcpm0 \$c9,\(\$sp\+\),0
+ 890: 25 f9 f0 28 swcpm0 \$c9,\(\$2\+\),-16
+ 894: e5 f0 30 28 swcpm0 \$c0,\(\$gp\+\),48
+ 898: 15 ff 08 28 swcpm0 \$c15,\(\$1\+\),8
+
+0000089c <lwcpm0>:
+ 89c: a5 fe fc 68 lwcpm0 \$c14,\(\$10\+\),-4
+ 8a0: f5 fb fc 68 lwcpm0 \$c11,\(\$sp\+\),-4
+ 8a4: 75 f5 f8 68 lwcpm0 \$c5,\(\$7\+\),-8
+ 8a8: c5 f2 20 68 lwcpm0 \$c2,\(\$12\+\),32
+ 8ac: e5 f2 10 68 lwcpm0 \$c2,\(\$gp\+\),16
+
+000008b0 <smcpm0>:
+ 8b0: c5 f1 08 38 smcpm0 \$c1,\(\$12\+\),8
+ 8b4: 45 f8 f0 38 smcpm0 \$c8,\(\$4\+\),-16
+ 8b8: b5 fa 00 38 smcpm0 \$c10,\(\$11\+\),0
+ 8bc: 35 f1 f0 38 smcpm0 \$c1,\(\$3\+\),-16
+ 8c0: f5 fb f8 38 smcpm0 \$c11,\(\$sp\+\),-8
+
+000008c4 <lmcpm0>:
+ 8c4: a5 fe 00 78 lmcpm0 \$c14,\(\$10\+\),0
+ 8c8: f5 f6 f0 78 lmcpm0 \$c6,\(\$sp\+\),-16
+ 8cc: 15 fd 08 78 lmcpm0 \$c13,\(\$1\+\),8
+ 8d0: d5 fa e8 78 lmcpm0 \$c10,\(\$tp\+\),-24
+ 8d4: e5 f7 e8 78 lmcpm0 \$c7,\(\$gp\+\),-24
+
+000008d8 <sbcpm1>:
+ 8d8: 85 f9 00 0c sbcpm1 \$c9,\(\$8\+\),0
+ 8dc: c5 f7 e8 0c sbcpm1 \$c7,\(\$12\+\),-24
+ 8e0: 55 ff e8 0c sbcpm1 \$c15,\(\$5\+\),-24
+ 8e4: d5 f5 10 0c sbcpm1 \$c5,\(\$tp\+\),16
+ 8e8: 15 f6 80 0c sbcpm1 \$c6,\(\$1\+\),-128
+
+000008ec <lbcpm1>:
+ 8ec: e5 f6 02 4c lbcpm1 \$c6,\(\$gp\+\),2
+ 8f0: d5 f7 fe 4c lbcpm1 \$c7,\(\$tp\+\),-2
+ 8f4: d5 f4 01 4c lbcpm1 \$c4,\(\$tp\+\),1
+ 8f8: 25 fc fe 4c lbcpm1 \$c12,\(\$2\+\),-2
+ 8fc: 75 fb 01 4c lbcpm1 \$c11,\(\$7\+\),1
+
+00000900 <shcpm1>:
+ 900: 85 f4 18 1c shcpm1 \$c4,\(\$8\+\),24
+ 904: 65 fb f0 1c shcpm1 \$c11,\(\$6\+\),-16
+ 908: 85 f7 08 1c shcpm1 \$c7,\(\$8\+\),8
+ 90c: c5 f5 10 1c shcpm1 \$c5,\(\$12\+\),16
+ 910: 85 f0 e0 1c shcpm1 \$c0,\(\$8\+\),-32
+
+00000914 <lhcpm1>:
+ 914: 05 fb 00 5c lhcpm1 \$c11,\(\$0\+\),0
+ 918: d5 f7 fe 5c lhcpm1 \$c7,\(\$tp\+\),-2
+ 91c: 85 fa 08 5c lhcpm1 \$c10,\(\$8\+\),8
+ 920: d5 f3 00 5c lhcpm1 \$c3,\(\$tp\+\),0
+ 924: 65 f9 02 5c lhcpm1 \$c9,\(\$6\+\),2
+
+00000928 <swcpm1>:
+ 928: 85 f9 18 2c swcpm1 \$c9,\(\$8\+\),24
+ 92c: e5 f9 00 2c swcpm1 \$c9,\(\$gp\+\),0
+ 930: 85 f9 10 2c swcpm1 \$c9,\(\$8\+\),16
+ 934: 15 fe 00 2c swcpm1 \$c14,\(\$1\+\),0
+ 938: f5 f2 08 2c swcpm1 \$c2,\(\$sp\+\),8
+
+0000093c <lwcpm1>:
+ 93c: 85 f8 00 6c lwcpm1 \$c8,\(\$8\+\),0
+ 940: e5 f3 f0 6c lwcpm1 \$c3,\(\$gp\+\),-16
+ 944: 65 f7 f8 6c lwcpm1 \$c7,\(\$6\+\),-8
+ 948: 85 fe e8 6c lwcpm1 \$c14,\(\$8\+\),-24
+ 94c: 85 f3 18 6c lwcpm1 \$c3,\(\$8\+\),24
+
+00000950 <smcpm1>:
+ 950: 45 fa 00 3c smcpm1 \$c10,\(\$4\+\),0
+ 954: f5 f6 f0 3c smcpm1 \$c6,\(\$sp\+\),-16
+ 958: 75 fd e8 3c smcpm1 \$c13,\(\$7\+\),-24
+ 95c: e5 f3 f8 3c smcpm1 \$c3,\(\$gp\+\),-8
+ 960: 25 f0 08 3c smcpm1 \$c0,\(\$2\+\),8
+
+00000964 <lmcpm1>:
+ 964: 15 fc 00 7c lmcpm1 \$c12,\(\$1\+\),0
+ 968: 65 f0 08 7c lmcpm1 \$c0,\(\$6\+\),8
+ 96c: 25 f6 f8 7c lmcpm1 \$c6,\(\$2\+\),-8
+ 970: e5 fc f0 7c lmcpm1 \$c12,\(\$gp\+\),-16
+ 974: f5 fe 30 7c lmcpm1 \$c14,\(\$sp\+\),48
+
+00000... <bcpeq>:
+ ...: 44 d8 00 00 bcpeq 0x4,... <bcpeq>
+ ...: 04 d8 ff ff bcpeq 0x0,... <bcpeq\+0x2>
+ ...: 44 d8 ff ff bcpeq 0x4,... <bcpeq\+0x6>
+ ...: 14 d8 01 00 bcpeq 0x1,... <bcpeq\+0xe>
+ ...: 24 d8 01 00 bcpeq 0x2,... <bcpeq\+0x12>
+
+00000... <bcpne>:
+ ...: 25 d8 00 00 bcpne 0x2,... <bcpne>
+ ...: 45 d8 00 00 bcpne 0x4,... <bcpne\+0x4>
+ ...: 15 d8 00 00 bcpne 0x1,... <bcpne\+0x8>
+ ...: 45 d8 00 00 bcpne 0x4,... <bcpne\+0xc>
+ ...: 15 d8 01 00 bcpne 0x1,... <bcpne\+0x12>
+
+00000... <bcpat>:
+ ...: 16 d8 ff ff bcpat 0x1,... <bcpne\+0x12>
+ ...: 06 d8 01 00 bcpat 0x0,... <bcpat\+0x6>
+ ...: 06 d8 ff ff bcpat 0x0,... <bcpat\+0x6>
+ ...: 26 d8 00 00 bcpat 0x2,... <bcpat\+0xc>
+ ...: 16 d8 ff ff bcpat 0x1,... <bcpat\+0xe>
+
+00000... <bcpaf>:
+ ...: 47 d8 00 00 bcpaf 0x4,... <bcpaf>
+ ...: 37 d8 00 00 bcpaf 0x3,... <bcpaf\+0x4>
+ ...: 47 d8 00 00 bcpaf 0x4,... <bcpaf\+0x8>
+ ...: 17 d8 01 00 bcpaf 0x1,... <bcpaf\+0xe>
+ ...: 47 d8 01 00 bcpaf 0x4,... <bcpaf\+0x12>
+
+00000... <synccp>:
+ ...: 21 70 synccp
+
+00000... <jsrv>:
+ ...: bf 18 jsrv \$11
+ ...: 5f 18 jsrv \$5
+ ...: af 18 jsrv \$10
+ ...: cf 18 jsrv \$12
+ ...: af 18 jsrv \$10
+
+00000... <bsrv>:
+ ...: fb df ff ff bsrv ... <jsrv\+0x8>
+ ...: fb df ff ff bsrv ... <bsrv\+0x2>
+ ...: fb df ff ff bsrv ... <bsrv\+0x6>
+ ...: 1b d8 00 00 bsrv ... <bsrv\+0xe>
+ ...: 0b d8 00 00 bsrv ... <bsrv\+0x10>
+
+00000... <case106341>:
+ ...: 78 7a stc \$10,\$hi
+ ...: 8a 70 ldc \$0,\$lo
+
+00000... <case106821>:
+ ...: 08 00 sb \$0,\(\$0\)
+ ...: 09 00 sh \$0,\(\$0\)
+ ...: 0a 00 sw \$0,\(\$0\)
+ ...: 0c 00 lb \$0,\(\$0\)
+ ...: 0d 00 lh \$0,\(\$0\)
+ ...: 0e 00 lw \$0,\(\$0\)
+ ...: 0b 00 lbu \$0,\(\$0\)
+ ...: 0f 00 lhu \$0,\(\$0\)
+ ...: 08 00 sb \$0,\(\$0\)
+ ...: 08 00 sb \$0,\(\$0\)
+ ...: 08 00 sb \$0,\(\$0\)
+ ...: 08 00 sb \$0,\(\$0\)
+ ...: 08 00 sb \$0,\(\$0\)
+ ...: 08 00 sb \$0,\(\$0\)
+ ...: 09 00 sh \$0,\(\$0\)
+ ...: 09 00 sh \$0,\(\$0\)
+ ...: 09 00 sh \$0,\(\$0\)
+ ...: 09 00 sh \$0,\(\$0\)
+ ...: 09 00 sh \$0,\(\$0\)
+ ...: 09 00 sh \$0,\(\$0\)
+ ...: 0a 00 sw \$0,\(\$0\)
+ ...: 0a 00 sw \$0,\(\$0\)
+ ...: 0a 00 sw \$0,\(\$0\)
+ ...: 0a 00 sw \$0,\(\$0\)
+ ...: 0a 00 sw \$0,\(\$0\)
+ ...: 0a 00 sw \$0,\(\$0\)
+ ...: 0c 00 lb \$0,\(\$0\)
+ ...: 0c 00 lb \$0,\(\$0\)
+ ...: 0c 00 lb \$0,\(\$0\)
+ ...: 0c 00 lb \$0,\(\$0\)
+ ...: 0c 00 lb \$0,\(\$0\)
+ ...: 0c 00 lb \$0,\(\$0\)
+ ...: 0d 00 lh \$0,\(\$0\)
+ ...: 0d 00 lh \$0,\(\$0\)
+ ...: 0d 00 lh \$0,\(\$0\)
+ ...: 0d 00 lh \$0,\(\$0\)
+ ...: 0d 00 lh \$0,\(\$0\)
+ ...: 0d 00 lh \$0,\(\$0\)
+ ...: 0e 00 lw \$0,\(\$0\)
+ ...: 0e 00 lw \$0,\(\$0\)
+ ...: 0e 00 lw \$0,\(\$0\)
+ ...: 0e 00 lw \$0,\(\$0\)
+ ...: 0e 00 lw \$0,\(\$0\)
+ ...: 0e 00 lw \$0,\(\$0\)
+ ...: 0b 00 lbu \$0,\(\$0\)
+ ...: 0b 00 lbu \$0,\(\$0\)
+ ...: 0b 00 lbu \$0,\(\$0\)
+ ...: 0b 00 lbu \$0,\(\$0\)
+ ...: 0b 00 lbu \$0,\(\$0\)
+ ...: 0b 00 lbu \$0,\(\$0\)
+ ...: 0f 00 lhu \$0,\(\$0\)
+ ...: 0f 00 lhu \$0,\(\$0\)
+ ...: 0f 00 lhu \$0,\(\$0\)
+ ...: 0f 00 lhu \$0,\(\$0\)
+ ...: 0f 00 lhu \$0,\(\$0\)
+ ...: 0f 00 lhu \$0,\(\$0\)
+ ...: 08 c0 01 00 sb \$0,1\(\$0\)
+ ...: 08 c0 01 00 sb \$0,1\(\$0\)
+ ...: 08 c0 00 00 sb \$0,0\(\$0\)
+ ...: 08 c0 00 00 sb \$0,0\(\$0\)
+ ...: 08 c0 01 00 sb \$0,1\(\$0\)
+ ...: 08 c0 01 00 sb \$0,1\(\$0\)
+ ...: 09 c0 01 00 sh \$0,1\(\$0\)
+ ...: 09 c0 01 00 sh \$0,1\(\$0\)
+ ...: 09 c0 00 00 sh \$0,0\(\$0\)
+ ...: 09 c0 00 00 sh \$0,0\(\$0\)
+ ...: 09 c0 01 00 sh \$0,1\(\$0\)
+ ...: 09 c0 01 00 sh \$0,1\(\$0\)
+ ...: 0a c0 01 00 sw \$0,1\(\$0\)
+ ...: 0a c0 01 00 sw \$0,1\(\$0\)
+ ...: 0a c0 00 00 sw \$0,0\(\$0\)
+ ...: 0a c0 00 00 sw \$0,0\(\$0\)
+ ...: 0a c0 01 00 sw \$0,1\(\$0\)
+ ...: 0a c0 01 00 sw \$0,1\(\$0\)
+ ...: 0c c0 01 00 lb \$0,1\(\$0\)
+ ...: 0c c0 01 00 lb \$0,1\(\$0\)
+ ...: 0c c0 00 00 lb \$0,0\(\$0\)
+ ...: 0c c0 00 00 lb \$0,0\(\$0\)
+ ...: 0c c0 01 00 lb \$0,1\(\$0\)
+ ...: 0c c0 01 00 lb \$0,1\(\$0\)
+ ...: 0d c0 01 00 lh \$0,1\(\$0\)
+ ...: 0d c0 01 00 lh \$0,1\(\$0\)
+ ...: 0d c0 00 00 lh \$0,0\(\$0\)
+ ...: 0d c0 00 00 lh \$0,0\(\$0\)
+ ...: 0d c0 01 00 lh \$0,1\(\$0\)
+ ...: 0d c0 01 00 lh \$0,1\(\$0\)
+ ...: 0e c0 01 00 lw \$0,1\(\$0\)
+ ...: 0e c0 01 00 lw \$0,1\(\$0\)
+ ...: 0e c0 00 00 lw \$0,0\(\$0\)
+ ...: 0e c0 00 00 lw \$0,0\(\$0\)
+ ...: 0e c0 01 00 lw \$0,1\(\$0\)
+ ...: 0e c0 01 00 lw \$0,1\(\$0\)
+ ...: 0b c0 01 00 lbu \$0,1\(\$0\)
+ ...: 0b c0 01 00 lbu \$0,1\(\$0\)
+ ...: 0b c0 00 00 lbu \$0,0\(\$0\)
+ ...: 0b c0 00 00 lbu \$0,0\(\$0\)
+ ...: 0b c0 01 00 lbu \$0,1\(\$0\)
+ ...: 0b c0 01 00 lbu \$0,1\(\$0\)
+ ...: 0f c0 01 00 lhu \$0,1\(\$0\)
+ ...: 0f c0 01 00 lhu \$0,1\(\$0\)
+ ...: 0f c0 00 00 lhu \$0,0\(\$0\)
+ ...: 0f c0 00 00 lhu \$0,0\(\$0\)
+ ...: 0f c0 01 00 lhu \$0,1\(\$0\)
+ ...: 0f c0 01 00 lhu \$0,1\(\$0\)
+ ...: 08 c0 00 00 sb \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: 08 c0 00 00 sb \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: 08 c0 00 00 sb \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: 08 c0 00 00 sb \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: 09 c0 00 00 sh \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: 09 c0 00 00 sh \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: 09 c0 00 00 sh \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: 09 c0 00 00 sh \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: 0a c0 00 00 sw \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: 0a c0 00 00 sw \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: 0a c0 00 00 sw \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: 0a c0 00 00 sw \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: 0c c0 00 00 lb \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: 0c c0 00 00 lb \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: 0c c0 00 00 lb \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: 0c c0 00 00 lb \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: 0d c0 00 00 lh \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: 0d c0 00 00 lh \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: 0d c0 00 00 lh \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: 0d c0 00 00 lh \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: 0e c0 00 00 lw \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: 0e c0 00 00 lw \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: 0e c0 00 00 lw \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: 0e c0 00 00 lw \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: 0b c0 00 00 lbu \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: 0b c0 00 00 lbu \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: 0b c0 00 00 lbu \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: 0b c0 00 00 lbu \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
+ ...: 0f c0 00 00 lhu \$0,0\(\$0\)
+ ...: R_MEP_16 .text\+0x...
+ ...: 0f c0 00 00 lhu \$0,0\(\$0\)
+ ...: R_MEP_LOW16 .text\+0x...
+ ...: 0f c0 00 00 lhu \$0,0\(\$0\)
+ ...: R_MEP_HI16S .text\+0x...
+ ...: 0f c0 00 00 lhu \$0,0\(\$0\)
+ ...: R_MEP_HI16U .text\+0x...
--- /dev/null
+ .data
+foodata: .word 42
+ .text
+footext:
+ .text
+ .global sb
+sb:
+ sb $7,($fp)
+ sb $5,($9)
+ sb $7,($14)
+ sb $14,($fp)
+ sb $15,($14)
+ .text
+ .global sh
+sh:
+ sh $3,($fp)
+ sh $12,($1)
+ sh $13,($2)
+ sh $2,($8)
+ sh $12,($10)
+ .text
+ .global sw
+sw:
+ sw $11,($0)
+ sw $3,($7)
+ sw $13,($14)
+ sw $8,($9)
+ sw $gp,($fp)
+ .text
+ .global lb
+lb:
+ lb $12,($11)
+ lb $9,($2)
+ lb $fp,($11)
+ lb $gp,($2)
+ lb $2,($12)
+ .text
+ .global lh
+lh:
+ lh $15,($8)
+ lh $3,($10)
+ lh $9,($sp)
+ lh $6,($sp)
+ lh $15,($11)
+ .text
+ .global lw
+lw:
+ lw $12,($10)
+ lw $9,($13)
+ lw $12,($gp)
+ lw $12,($11)
+ lw $13,($10)
+ .text
+ .global lbu
+lbu:
+ lbu $14,($14)
+ lbu $12,($fp)
+ lbu $gp,($1)
+ lbu $fp,($12)
+ lbu $12,($1)
+ .text
+ .global lhu
+lhu:
+ lhu $15,($4)
+ lhu $14,($4)
+ lhu $5,($4)
+ lhu $sp,($tp)
+ lhu $4,($15)
+ .text
+ .global sw_sp
+sw_sp:
+ sw $9,3($8)
+ sw $10,4($5)
+ sw $0,3($gp)
+ sw $0,2($8)
+ sw $15,1($8)
+ .text
+ .global lw_sp
+lw_sp:
+ lw $tp,1($5)
+ lw $15,1($0)
+ lw $0,4($12)
+ lw $11,1($tp)
+ lw $9,3($4)
+ .text
+ .global sb_tp
+sb_tp:
+ sb $5,1($1)
+ sb $10,1($9)
+ sb $5,3($3)
+ sb $5,1($3)
+ sb $10,4($4)
+ .text
+ .global sh_tp
+sh_tp:
+ sh $3,1($0)
+ sh $tp,1($9)
+ sh $9,4($10)
+ sh $15,3($14)
+ sh $14,4($9)
+ .text
+ .global sw_tp
+sw_tp:
+ sw $6,2($13)
+ sw $6,1($15)
+ sw $2,2($3)
+ sw $6,2($12)
+ sw $3,1($11)
+ .text
+ .global lb_tp
+lb_tp:
+ lb $tp,4($11)
+ lb $13,4($8)
+ lb $5,4($5)
+ lb $sp,2($gp)
+ lb $3,2($3)
+ .text
+ .global lh_tp
+lh_tp:
+ lh $7,2($fp)
+ lh $4,3($8)
+ lh $14,1($sp)
+ lh $9,1($0)
+ lh $13,2($0)
+ .text
+ .global lw_tp
+lw_tp:
+ lw $8,4($15)
+ lw $11,4($9)
+ lw $gp,1($2)
+ lw $9,2($14)
+ lw $8,1($12)
+ .text
+ .global lbu_tp
+lbu_tp:
+ lbu $12,1($9)
+ lbu $11,1($9)
+ lbu $14,3($8)
+ lbu $0,2($sp)
+ lbu $13,1($11)
+ .text
+ .global lhu_tp
+lhu_tp:
+ lhu $14,2($10)
+ lhu $11,1($8)
+ lhu $1,1($0)
+ lhu $7,2($15)
+ lhu $3,2($tp)
+ .text
+ .global sb16
+sb16:
+ sb $7,-1($11)
+ sb $tp,1($gp)
+ sb $3,1($gp)
+ sb $14,2($6)
+ sb $14,1($7)
+ .text
+ .global sh16
+sh16:
+ sh $12,-1($4)
+ sh $sp,1($1)
+ sh $2,-2($12)
+ sh $9,2($11)
+ sh $9,-2($12)
+ .text
+ .global sw16
+sw16:
+ sw $11,-1($gp)
+ sw $4,4($15)
+ sw $2,-2($3)
+ sw $6,-1($2)
+ sw $fp,-2($tp)
+ .text
+ .global lb16
+lb16:
+ lb $10,-2($2)
+ lb $3,-2($11)
+ lb $12,1($5)
+ lb $5,1($5)
+ lb $11,2($13)
+ .text
+ .global lh16
+lh16:
+ lh $sp,-1($11)
+ lh $tp,-2($11)
+ lh $2,1($10)
+ lh $8,-1($7)
+ lh $14,-1($11)
+ .text
+ .global lw16
+lw16:
+ lw $0,-1($5)
+ lw $12,-2($7)
+ lw $1,-2($3)
+ lw $1,2($7)
+ lw $4,1($fp)
+ .text
+ .global lbu16
+lbu16:
+ lbu $12,-1($4)
+ lbu $14,1($11)
+ lbu $1,-1($13)
+ lbu $9,-1($tp)
+ lbu $8,1($15)
+ .text
+ .global lhu16
+lhu16:
+ lhu $tp,-1($15)
+ lhu $gp,2($fp)
+ lhu $15,-1($12)
+ lhu $3,-1($0)
+ lhu $3,-2($12)
+ .text
+ .global sw24
+sw24:
+ sw $11,(4)
+ sw $sp,(4)
+ sw $7,(8)
+ sw $10,(16)
+ sw $8,(160)
+ .text
+ .global lw24
+lw24:
+ lw $4,(4)
+ lw $sp,(4)
+ lw $4,(16)
+ lw $fp,(0)
+ lw $tp,(8)
+ .text
+ .global extb
+extb:
+ extb $13
+ extb $tp
+ extb $6
+ extb $14
+ extb $10
+ .text
+ .global exth
+exth:
+ exth $15
+ exth $2
+ exth $5
+ exth $10
+ exth $4
+ .text
+ .global extub
+extub:
+ extub $2
+ extub $tp
+ extub $3
+ extub $9
+ extub $gp
+ .text
+ .global extuh
+extuh:
+ extuh $8
+ extuh $8
+ extuh $4
+ extuh $0
+ extuh $0
+ .text
+ .global ssarb
+ssarb:
+ ssarb 2($fp)
+ ssarb 2($13)
+ ssarb 1($13)
+ ssarb 2($5)
+ ssarb 0($9)
+ .text
+ .global mov
+mov:
+ mov $2,$3
+ mov $3,$11
+ mov $15,$10
+ mov $15,$0
+ mov $3,$tp
+ .text
+ .global movi8
+movi8:
+ mov $11,-1
+ mov $6,2
+ mov $sp,-1
+ mov $sp,1
+ mov $gp,-1
+ .text
+ .global movi16
+movi16:
+ mov $15,0
+ mov $0,2
+ mov $8,-1
+ mov $12,1
+ mov $7,-1
+ .text
+ .global movu24
+movu24:
+ movu $2,1
+ movu $10,4
+ movu $9,0
+ movu $4,3
+ movu $14,1
+ .text
+ .global movu16
+movu16:
+ movu $sp,1
+ movu $6,3
+ movu $0,3
+ movu $gp,3
+ movu $10,2
+ .text
+ .global movh
+movh:
+ movh $8,2
+ movh $13,1
+ movh $gp,2
+ movh $12,0
+ movh $11,2
+ .text
+ .global add3
+add3:
+ add3 $6,$11,$3
+ add3 $14,$13,$5
+ add3 $3,$11,$7
+ add3 $13,$14,$13
+ add3 $0,$14,$8
+ .text
+ .global add
+add:
+ add $12,2
+ add $12,-1
+ add $4,1
+ add $6,1
+ add $6,2
+ .text
+ .global add3i
+add3i:
+ add3 $11,$sp,4
+ add3 $4,$sp,1
+ add3 $0,$sp,0
+ add3 $13,$sp,3
+ add3 $11,$sp,0
+ .text
+ .global advck3
+advck3:
+ advck3 $0,$gp,$10
+ advck3 $0,$tp,$0
+ advck3 $0,$gp,$13
+ advck3 $0,$7,$fp
+ advck3 $0,$1,$2
+ .text
+ .global sub
+sub:
+ sub $8,$14
+ sub $1,$9
+ sub $13,$7
+ sub $15,$3
+ sub $2,$7
+ .text
+ .global sbvck3
+sbvck3:
+ sbvck3 $0,$3,$gp
+ sbvck3 $0,$3,$7
+ sbvck3 $0,$10,$10
+ sbvck3 $0,$4,$tp
+ sbvck3 $0,$10,$15
+ .text
+ .global neg
+neg:
+ neg $14,$7
+ neg $1,$7
+ neg $2,$11
+ neg $13,$fp
+ neg $14,$13
+ .text
+ .global slt3
+slt3:
+ slt3 $0,$14,$8
+ slt3 $0,$4,$13
+ slt3 $0,$10,$14
+ slt3 $0,$14,$5
+ slt3 $0,$3,$12
+ .text
+ .global sltu3
+sltu3:
+ sltu3 $0,$2,$8
+ sltu3 $0,$gp,$11
+ sltu3 $0,$2,$tp
+ sltu3 $0,$9,$fp
+ sltu3 $0,$6,$9
+ .text
+ .global slt3i
+slt3i:
+ slt3 $0,$6,2
+ slt3 $0,$11,1
+ slt3 $0,$15,0
+ slt3 $0,$3,0
+ slt3 $0,$tp,0
+ .text
+ .global sltu3i
+sltu3i:
+ sltu3 $0,$14,4
+ sltu3 $0,$tp,3
+ sltu3 $0,$3,1
+ sltu3 $0,$12,0
+ sltu3 $0,$1,3
+ .text
+ .global sl1ad3
+sl1ad3:
+ sl1ad3 $0,$fp,$gp
+ sl1ad3 $0,$4,$2
+ sl1ad3 $0,$sp,$12
+ sl1ad3 $0,$9,$1
+ sl1ad3 $0,$fp,$2
+ .text
+ .global sl2ad3
+sl2ad3:
+ sl2ad3 $0,$8,$13
+ sl2ad3 $0,$2,$3
+ sl2ad3 $0,$8,$9
+ sl2ad3 $0,$7,$12
+ sl2ad3 $0,$4,$12
+ .text
+ .global add3x
+add3x:
+ add3 $tp,$11,1
+ add3 $tp,$4,-1
+ add3 $2,$13,1
+ add3 $3,$gp,1
+ add3 $10,$15,2
+ .text
+ .global slt3x
+slt3x:
+ slt3 $fp,$1,-1
+ slt3 $0,$3,-2
+ slt3 $9,$15,-1
+ slt3 $3,$fp,2
+ slt3 $tp,$14,0
+ .text
+ .global sltu3x
+sltu3x:
+ sltu3 $15,$11,2
+ sltu3 $6,$0,1
+ sltu3 $9,$11,3
+ sltu3 $0,$4,0
+ sltu3 $13,$gp,4
+ .text
+ .global or
+or:
+ or $sp,$gp
+ or $fp,$3
+ or $0,$sp
+ or $tp,$0
+ or $8,$6
+ .text
+ .global and
+and:
+ and $15,$sp
+ and $6,$14
+ and $4,$2
+ and $5,$fp
+ and $7,$14
+ .text
+ .global xor
+xor:
+ xor $1,$12
+ xor $12,$tp
+ xor $10,$8
+ xor $sp,$11
+ xor $12,$8
+ .text
+ .global nor
+nor:
+ nor $9,$5
+ nor $8,$2
+ nor $15,$9
+ nor $5,$sp
+ nor $sp,$14
+ .text
+ .global or3
+or3:
+ or3 $13,$sp,2
+ or3 $sp,$tp,3
+ or3 $0,$10,4
+ or3 $9,$15,3
+ or3 $9,$sp,0
+ .text
+ .global and3
+and3:
+ and3 $5,$8,1
+ and3 $11,$gp,3
+ and3 $6,$0,0
+ and3 $sp,$sp,0
+ and3 $1,$10,3
+ .text
+ .global xor3
+xor3:
+ xor3 $0,$0,2
+ xor3 $15,$6,0
+ xor3 $13,$5,0
+ xor3 $15,$7,0
+ xor3 $15,$sp,2
+ .text
+ .global sra
+sra:
+ sra $4,$1
+ sra $fp,$15
+ sra $1,$1
+ sra $0,$5
+ sra $9,$1
+ .text
+ .global srl
+srl:
+ srl $2,$11
+ srl $15,$7
+ srl $1,$7
+ srl $3,$13
+ srl $14,$1
+ .text
+ .global sll
+sll:
+ sll $11,$0
+ sll $tp,$fp
+ sll $8,$9
+ sll $13,$15
+ sll $sp,$sp
+ .text
+ .global srai
+srai:
+ sra $1,2
+ sra $15,3
+ sra $sp,3
+ sra $6,4
+ sra $sp,3
+ .text
+ .global srli
+srli:
+ srl $10,0
+ srl $9,3
+ srl $6,4
+ srl $10,2
+ srl $8,3
+ .text
+ .global slli
+slli:
+ sll $0,0
+ sll $4,0
+ sll $13,2
+ sll $11,2
+ sll $6,0
+ .text
+ .global sll3
+sll3:
+ sll3 $0,$tp,4
+ sll3 $0,$14,0
+ sll3 $0,$8,2
+ sll3 $0,$3,2
+ sll3 $0,$fp,0
+ .text
+ .global fsft
+fsft:
+ fsft $gp,$10
+ fsft $gp,$9
+ fsft $15,$13
+ fsft $11,$3
+ fsft $5,$3
+ .text
+ .global bra
+bra:
+ bra 2
+ bra -2
+ bra 2
+ bra 0
+ bra 2
+ .text
+ .global beqz
+beqz:
+ beqz $1,-2
+ beqz $sp,2
+ beqz $4,4
+ beqz $4,0
+ beqz $9,-2
+ .text
+ .global bnez
+bnez:
+ bnez $8,2
+ bnez $13,2
+ bnez $gp,0
+ bnez $6,2
+ bnez $8,-4
+ .text
+ .global beqi
+beqi:
+ beqi $tp,3,0
+ beqi $0,4,-2
+ beqi $sp,4,-2
+ beqi $13,2,0
+ beqi $4,2,-8
+ .text
+ .global bnei
+bnei:
+ bnei $8,1,0
+ bnei $5,1,2
+ bnei $5,0,8
+ bnei $9,4,-2
+ bnei $0,4,-8
+ .text
+ .global blti
+blti:
+ blti $7,3,0
+ blti $1,1,0
+ blti $8,2,2
+ blti $11,2,2
+ blti $15,3,-2
+ .text
+ .global bgei
+bgei:
+ bgei $4,3,-8
+ bgei $7,0,2
+ bgei $13,1,0
+ bgei $5,2,-2
+ bgei $12,4,-8
+ .text
+ .global beq
+beq:
+ beq $7,$2,-2
+ beq $1,$3,-8
+ beq $2,$0,2
+ beq $sp,$fp,2
+ beq $3,$0,0
+ .text
+ .global bne
+bne:
+ bne $6,$3,0
+ bne $sp,$3,-8
+ bne $8,$0,2
+ bne $gp,$sp,8
+ bne $sp,$4,2
+ .text
+ .global bsr12
+bsr12:
+ bsr 2
+ bsr -8
+ bsr -16
+ bsr -2
+ bsr -8
+ .text
+ .global bsr24
+bsr24:
+ bsr 4
+ bsr -2
+ bsr -4
+ bsr 0
+ bsr 2
+ .text
+ .global jmp
+jmp:
+ jmp $2
+ jmp $tp
+ jmp $5
+ jmp $sp
+ jmp $fp
+ .text
+ .global jmp24
+jmp24:
+ jmp 4
+ jmp 2
+ jmp 0
+ jmp 2
+ jmp 4
+ .text
+ .global jsr
+jsr:
+ jsr $15
+ jsr $13
+ jsr $13
+ jsr $6
+ jsr $6
+ .text
+ .global ret
+ret:
+ ret
+ .text
+ .global repeat
+repeat:
+ repeat $4,2
+ repeat $fp,4
+ repeat $0,8
+ repeat $6,2
+ repeat $4,2
+ .text
+ .global erepeat
+erepeat:
+ erepeat 2
+ erepeat 0
+ erepeat 2
+ erepeat -2
+ erepeat 0
+ .text
+ .global stc
+stc:
+ stc $13,$mb1
+ stc $tp,$ccfg
+ stc $11,$dbg
+ stc $10,$ccfg
+ stc $9,$epc
+ .text
+ .global ldc
+ldc:
+ ldc $tp,$lo
+ ldc $8,$npc
+ ldc $9,$mb0
+ ldc $15,$sar
+ ldc $9,$ccfg
+ .text
+ .global di
+di:
+ di
+ .text
+ .global ei
+ei:
+ ei
+ .text
+ .global reti
+reti:
+ reti
+ .text
+ .global halt
+halt:
+ halt
+ .text
+ .global swi
+swi:
+ swi 2
+ swi 0
+ swi 2
+ swi 3
+ swi 1
+ .text
+ .global break
+break:
+ break
+ .text
+ .global sycnm
+syncm:
+ syncm
+ .text
+ .global stcb
+stcb:
+ stcb $5,4
+ stcb $5,1
+ stcb $gp,0
+ stcb $15,4
+ stcb $11,2
+ .text
+ .global ldcb
+ldcb:
+ ldcb $2,3
+ ldcb $2,4
+ ldcb $9,1
+ ldcb $10,4
+ ldcb $1,4
+ .text
+ .global bsetm
+bsetm:
+ bsetm ($10),0
+ bsetm ($sp),0
+ bsetm ($1),2
+ bsetm ($sp),4
+ bsetm ($8),4
+ .text
+ .global bclrm
+bclrm:
+ bclrm ($5),0
+ bclrm ($5),2
+ bclrm ($8),0
+ bclrm ($9),2
+ bclrm ($5),3
+ .text
+ .global bnotm
+bnotm:
+ bnotm ($14),4
+ bnotm ($11),4
+ bnotm ($10),0
+ bnotm ($tp),4
+ bnotm ($fp),0
+ .text
+ .global btstm
+btstm:
+ btstm $0,($14),0
+ btstm $0,($14),1
+ btstm $0,($11),0
+ btstm $0,($14),3
+ btstm $0,($fp),2
+ .text
+ .global tas
+tas:
+ tas $7,($tp)
+ tas $7,($12)
+ tas $3,($fp)
+ tas $2,($5)
+ tas $6,($10)
+ .text
+ .global cache
+cache:
+ cache 1,($13)
+ cache 3,($12)
+ cache 3,($9)
+ cache 4,($2)
+ cache 4,($7)
+ .text
+ .global mul
+mul:
+ mul $8,$14
+ mul $2,$9
+ mul $14,$15
+ mul $9,$7
+ mul $7,$11
+ .text
+ .global mulu
+mulu:
+ mulu $2,$5
+ mulu $6,$gp
+ mulu $gp,$sp
+ mulu $11,$14
+ mulu $3,$9
+ .text
+ .global mulr
+mulr:
+ mulr $12,$6
+ mulr $13,$8
+ mulr $7,$10
+ mulr $gp,$1
+ mulr $0,$15
+ .text
+ .global mulru
+mulru:
+ mulru $4,$2
+ mulru $14,$1
+ mulru $15,$4
+ mulru $10,$6
+ mulru $0,$gp
+ .text
+ .global madd
+madd:
+ madd $4,$11
+ madd $15,$14
+ madd $14,$sp
+ madd $4,$tp
+ madd $1,$gp
+ .text
+ .global maddu
+maddu:
+ maddu $0,$1
+ maddu $7,$6
+ maddu $9,$5
+ maddu $gp,$15
+ maddu $7,$13
+ .text
+ .global maddr
+maddr:
+ maddr $6,$fp
+ maddr $9,$14
+ maddr $8,$gp
+ maddr $3,$2
+ maddr $1,$11
+ .text
+ .global maddru
+maddru:
+ maddru $10,$3
+ maddru $15,$12
+ maddru $8,$fp
+ maddru $14,$3
+ maddru $fp,$15
+ .text
+ .global div
+div:
+ div $9,$3
+ div $4,$14
+ div $2,$12
+ div $fp,$tp
+ div $tp,$6
+ .text
+ .global divu
+divu:
+ divu $9,$5
+ divu $8,$13
+ divu $0,$14
+ divu $9,$5
+ divu $0,$5
+ .text
+ .global dret
+dret:
+ dret
+ .text
+ .global dbreak
+dbreak:
+ dbreak
+ .text
+ .global ldz
+ldz:
+ ldz $gp,$4
+ ldz $10,$11
+ ldz $9,$9
+ ldz $15,$tp
+ ldz $gp,$3
+ .text
+ .global abs
+abs:
+ abs $sp,$9
+ abs $5,$4
+ abs $tp,$13
+ abs $0,$3
+ abs $3,$14
+ .text
+ .global ave
+ave:
+ ave $11,$10
+ ave $fp,$10
+ ave $14,$2
+ ave $10,$12
+ ave $15,$8
+ .text
+ .global min
+min:
+ min $8,$3
+ min $7,$0
+ min $2,$2
+ min $5,$6
+ min $11,$5
+ .text
+ .global max
+max:
+ max $11,$sp
+ max $gp,$0
+ max $12,$sp
+ max $gp,$2
+ max $14,$sp
+ .text
+ .global minu
+minu:
+ minu $11,$8
+ minu $7,$5
+ minu $fp,$14
+ minu $11,$4
+ minu $2,$sp
+ .text
+ .global maxu
+maxu:
+ maxu $3,$3
+ maxu $13,$0
+ maxu $4,$fp
+ maxu $gp,$2
+ maxu $12,$fp
+ .text
+ .global clip
+clip:
+ clip $10,1
+ clip $15,4
+ clip $4,3
+ clip $15,3
+ clip $1,0
+ .text
+ .global clipu
+clipu:
+ clipu $10,4
+ clipu $13,1
+ clipu $5,4
+ clipu $14,0
+ clipu $5,1
+ .text
+ .global sadd
+sadd:
+ sadd $5,$0
+ sadd $15,$3
+ sadd $0,$10
+ sadd $sp,$12
+ sadd $4,$2
+ .text
+ .global ssub
+ssub:
+ ssub $1,$10
+ ssub $4,$7
+ ssub $fp,$3
+ ssub $7,$gp
+ ssub $13,$4
+ .text
+ .global saddu
+saddu:
+ saddu $9,$14
+ saddu $0,$10
+ saddu $7,$12
+ saddu $5,$15
+ saddu $13,$3
+ .text
+ .global ssubu
+ssubu:
+ ssubu $15,$gp
+ ssubu $0,$15
+ ssubu $3,$10
+ ssubu $sp,$13
+ ssubu $2,$9
+ .text
+ .global swcp
+swcp:
+ swcp $c3,($13)
+ swcp $c15,($13)
+ swcp $c13,($0)
+ swcp $c12,($12)
+ swcp $c9,($gp)
+ .text
+ .global lwcp
+lwcp:
+ lwcp $c7,($3)
+ lwcp $c6,($3)
+ lwcp $c0,($2)
+ lwcp $c8,($fp)
+ lwcp $c11,($13)
+ .text
+ .global smcp
+smcp:
+ smcp $c14,($9)
+ smcp $c2,($fp)
+ smcp $c14,($15)
+ smcp $c10,($8)
+ smcp $c2,($8)
+ .text
+ .global lmcp
+lmcp:
+ lmcp $c11,($1)
+ lmcp $c8,($8)
+ lmcp $c11,($13)
+ lmcp $c8,($0)
+ lmcp $c8,($14)
+ .text
+ .global swcpi
+swcpi:
+ swcpi $c7,($0+)
+ swcpi $c6,($gp+)
+ swcpi $c12,($8+)
+ swcpi $c14,($15+)
+ swcpi $c6,($0+)
+ .text
+ .global lwcpi
+lwcpi:
+ lwcpi $c8,($2+)
+ lwcpi $c9,($0+)
+ lwcpi $c3,($14+)
+ lwcpi $c13,($5+)
+ lwcpi $c11,($gp+)
+ .text
+ .global smcpi
+smcpi:
+ smcpi $c8,($2+)
+ smcpi $c11,($9+)
+ smcpi $c4,($3+)
+ smcpi $c14,($2+)
+ smcpi $c9,($3+)
+ .text
+ .global lmcpi
+lmcpi:
+ lmcpi $c6,($14+)
+ lmcpi $c9,($5+)
+ lmcpi $c10,($6+)
+ lmcpi $c1,($6+)
+ lmcpi $c2,($8+)
+ .text
+ .global swcp16
+swcp16:
+ swcp $c0,-1($2)
+ swcp $c5,1($10)
+ swcp $c8,2($12)
+ swcp $c14,-1($1)
+ swcp $c12,2($3)
+ .text
+ .global lwcp16
+lwcp16:
+ lwcp $c8,-1($5)
+ lwcp $c12,1($15)
+ lwcp $c1,2($0)
+ lwcp $c4,1($13)
+ lwcp $c6,2($11)
+ .text
+ .global smcp16
+smcp16:
+ smcp $c9,-1($10)
+ smcp $c14,1($gp)
+ smcp $c3,2($sp)
+ smcp $c15,-2($8)
+ smcp $c13,1($13)
+ .text
+ .global lmcp16
+lmcp16:
+ lmcp $c0,1($15)
+ lmcp $c15,1($fp)
+ lmcp $c2,-1($8)
+ lmcp $c14,1($fp)
+ lmcp $c1,-1($10)
+ .text
+ .global sbcpa
+sbcpa:
+ sbcpa $c14,($sp+),2
+ sbcpa $c2,($4+),-2
+ sbcpa $c8,($1+),0
+ sbcpa $c11,($3+),0
+ sbcpa $c9,($14+),-2
+ .text
+ .global lbcpa
+lbcpa:
+ lbcpa $c7,($2+),-2
+ lbcpa $c12,($sp+),2
+ lbcpa $c5,($4+),-2
+ lbcpa $c7,($4+),-2
+ lbcpa $c8,($15+),0
+ .text
+ .global shcpa
+shcpa:
+ shcpa $c0,($14+),0
+ shcpa $c12,($sp+),16
+ shcpa $c1,($4+),4
+ shcpa $c5,($4+),-32
+ shcpa $c1,($15+),0
+ .text
+ .global lhcpa
+lhcpa:
+ lhcpa $c4,($4+),0
+ lhcpa $c6,($5+),48
+ lhcpa $c3,($6+),-52
+ lhcpa $c8,($6+),-24
+ lhcpa $c0,($9+),0
+ .text
+ .global swcpa
+swcpa:
+ swcpa $c1,($9+),16
+ swcpa $c7,($sp+),32
+ swcpa $c3,($12+),48
+ swcpa $c10,($9+),8
+ swcpa $c14,($8+),4
+ .text
+ .global lwcpa
+lwcpa:
+ lwcpa $c6,($gp+),-8
+ lwcpa $c4,($7+),4
+ lwcpa $c11,($gp+),-16
+ lwcpa $c10,($sp+),-32
+ lwcpa $c2,($2+),8
+ .text
+ .global smcpa
+smcpa:
+ smcpa $c13,($15+),-8
+ smcpa $c6,($7+),-8
+ smcpa $c5,($3+),16
+ smcpa $c13,($15+),16
+ smcpa $c3,($12+),48
+ .text
+ .global lmcpa
+lmcpa:
+ lmcpa $c9,($4+),0
+ lmcpa $c3,($sp+),-16
+ lmcpa $c15,($13+),8
+ lmcpa $c8,($8+),-8
+ lmcpa $c10,($9+),0
+ .text
+ .global sbcpm0
+sbcpm0:
+ sbcpm0 $c10,($13+),8
+ sbcpm0 $c13,($5+),-8
+ sbcpm0 $c4,($5+),-8
+ sbcpm0 $c10,($tp+),16
+ sbcpm0 $c4,($5+),-24
+ .text
+ .global lbcpm0
+lbcpm0:
+ lbcpm0 $c0,($4+),0
+ lbcpm0 $c9,($7+),-8
+ lbcpm0 $c12,($fp+),24
+ lbcpm0 $c8,($12+),16
+ lbcpm0 $c7,($fp+),16
+ .text
+ .global shcpm0
+shcpm0:
+ shcpm0 $c2,($13+),2
+ shcpm0 $c7,($15+),-2
+ shcpm0 $c8,($2+),2
+ shcpm0 $c13,($5+),0
+ shcpm0 $c3,($14+),8
+ .text
+ .global lhcpm0
+lhcpm0:
+ lhcpm0 $c7,($4+),8
+ lhcpm0 $c3,($3+),-2
+ lhcpm0 $c3,($1+),0
+ lhcpm0 $c2,($gp+),0
+ lhcpm0 $c12,($6+),2
+ .text
+ .global swcpm0
+swcpm0:
+ swcpm0 $c8,($fp+),32
+ swcpm0 $c9,($sp+),0
+ swcpm0 $c9,($2+),-16
+ swcpm0 $c0,($14+),48
+ swcpm0 $c15,($1+),8
+ .text
+ .global lwcpm0
+lwcpm0:
+ lwcpm0 $c14,($10+),-4
+ lwcpm0 $c11,($sp+),-4
+ lwcpm0 $c5,($7+),-8
+ lwcpm0 $c2,($12+),32
+ lwcpm0 $c2,($gp+),16
+ .text
+ .global smcpm0
+smcpm0:
+ smcpm0 $c1,($12+),8
+ smcpm0 $c8,($4+),-16
+ smcpm0 $c10,($11+),0
+ smcpm0 $c1,($3+),-16
+ smcpm0 $c11,($sp+),-8
+ .text
+ .global lmcpm0
+lmcpm0:
+ lmcpm0 $c14,($10+),0
+ lmcpm0 $c6,($15+),-16
+ lmcpm0 $c13,($1+),8
+ lmcpm0 $c10,($tp+),-24
+ lmcpm0 $c7,($14+),-24
+ .text
+ .global sbcpm1
+sbcpm1:
+ sbcpm1 $c9,($fp+),0
+ sbcpm1 $c7,($12+),-24
+ sbcpm1 $c15,($5+),-24
+ sbcpm1 $c5,($tp+),16
+ sbcpm1 $c6,($1+),-128
+ .text
+ .global lbcpm1
+lbcpm1:
+ lbcpm1 $c6,($gp+),2
+ lbcpm1 $c7,($tp+),-2
+ lbcpm1 $c4,($13+),1
+ lbcpm1 $c12,($2+),-2
+ lbcpm1 $c11,($7+),1
+ .text
+ .global shcpm1
+shcpm1:
+ shcpm1 $c4,($fp+),24
+ shcpm1 $c11,($6+),-16
+ shcpm1 $c7,($8+),8
+ shcpm1 $c5,($12+),16
+ shcpm1 $c0,($8+),-32
+ .text
+ .global lhcpm1
+lhcpm1:
+ lhcpm1 $c11,($0+),0
+ lhcpm1 $c7,($tp+),-2
+ lhcpm1 $c10,($8+),8
+ lhcpm1 $c3,($tp+),0
+ lhcpm1 $c9,($6+),2
+ .text
+ .global swcpm1
+swcpm1:
+ swcpm1 $c9,($8+),24
+ swcpm1 $c9,($14+),0
+ swcpm1 $c9,($fp+),16
+ swcpm1 $c14,($1+),0
+ swcpm1 $c2,($sp+),8
+ .text
+ .global lwcpm1
+lwcpm1:
+ lwcpm1 $c8,($fp+),0
+ lwcpm1 $c3,($14+),-16
+ lwcpm1 $c7,($6+),-8
+ lwcpm1 $c14,($fp+),-24
+ lwcpm1 $c3,($fp+),24
+ .text
+ .global smcpm1
+smcpm1:
+ smcpm1 $c10,($4+),0
+ smcpm1 $c6,($sp+),-16
+ smcpm1 $c13,($7+),-24
+ smcpm1 $c3,($gp+),-8
+ smcpm1 $c0,($2+),8
+ .text
+ .global lmcpm1
+lmcpm1:
+ lmcpm1 $c12,($1+),0
+ lmcpm1 $c0,($6+),8
+ lmcpm1 $c6,($2+),-8
+ lmcpm1 $c12,($gp+),-16
+ lmcpm1 $c14,($15+),48
+/*
+ .text
+ .global cmov1
+cmov1:
+ cmov $c11,$10
+ cmov $c14,$3
+ cmov $c3,$15
+ cmov $c6,$5
+ cmov $c6,$10
+ .text
+ .global cmov2
+cmov2:
+ cmov $11,$c2
+ cmov $10,$c2
+ cmov $tp,$c10
+ cmov $12,$c9
+ cmov $15,$c3
+ .text
+ .global cmovc1
+cmovc1:
+ cmovc $ccr9,$sp
+ cmovc $ccr12,$fp
+ cmovc $ccr1,$4
+ cmovc $ccr11,$sp
+ cmovc $ccr14,$7
+ .text
+ .global cmovc2
+cmovc2:
+ cmovc $fp,$ccr6
+ cmovc $fp,$ccr6
+ cmovc $7,$ccr8
+ cmovc $sp,$ccr12
+ cmovc $sp,$ccr5
+ .text
+ .global cmovh1
+cmovh1:
+ cmovh $c8,$1
+ cmovh $c12,$sp
+ cmovh $c11,$5
+ cmovh $c4,$4
+ cmovh $c3,$gp
+ .text
+ .global cmovh2
+cmovh2:
+ cmovh $4,$c7
+ cmovh $gp,$c8
+ cmovh $6,$c10
+ cmovh $2,$c8
+ cmovh $10,$c4
+*/
+ .text
+ .global bcpeq
+bcpeq:
+ bcpeq 4,0
+ bcpeq 0,-2
+ bcpeq 4,-2
+ bcpeq 1,2
+ bcpeq 2,2
+ .text
+ .global bcpne
+bcpne:
+ bcpne 2,0
+ bcpne 4,0
+ bcpne 1,0
+ bcpne 4,0
+ bcpne 1,2
+ .text
+ .global bcpat
+bcpat:
+ bcpat 1,-2
+ bcpat 0,2
+ bcpat 0,-2
+ bcpat 2,0
+ bcpat 1,-2
+ .text
+ .global bcpaf
+bcpaf:
+ bcpaf 4,0
+ bcpaf 3,0
+ bcpaf 4,0
+ bcpaf 1,2
+ bcpaf 4,2
+ .text
+ .global synccp
+synccp:
+ synccp
+ .text
+ .global jsrv
+jsrv:
+ jsrv $11
+ jsrv $5
+ jsrv $10
+ jsrv $12
+ jsrv $10
+ .text
+ .global bsrv
+bsrv:
+ bsrv -2
+ bsrv -2
+ bsrv -2
+ bsrv 2
+ bsrv 0
+ .text
+ .global case106341
+case106341:
+ stc $10,7
+ ldc $0, (4 + 4)
+case106821:
+ /* Actual 16 bit form */
+ sb $0,($0)
+ sh $0,($0)
+ sw $0,($0)
+ lb $0,($0)
+ lh $0,($0)
+ lw $0,($0)
+ lbu $0,($0)
+ lhu $0,($0)
+ /* Should use 16 bit form */
+ sb $0,0($0)
+ sb $0,%lo(0)($0)
+ sb $0,%hi(0)($0)
+ sb $0,%uhi(0)($0)
+ sb $0,%sdaoff(0)($0)
+ sb $0,%tpoff(0)($0)
+ sh $0,0($0)
+ sh $0,%lo(0)($0)
+ sh $0,%hi(0)($0)
+ sh $0,%uhi(0)($0)
+ sh $0,%sdaoff(0)($0)
+ sh $0,%tpoff(0)($0)
+ sw $0,0($0)
+ sw $0,%lo(0)($0)
+ sw $0,%hi(0)($0)
+ sw $0,%uhi(0)($0)
+ sw $0,%sdaoff(0)($0)
+ sw $0,%tpoff(0)($0)
+ lb $0,0($0)
+ lb $0,%lo(0)($0)
+ lb $0,%hi(0)($0)
+ lb $0,%uhi(0)($0)
+ lb $0,%sdaoff(0)($0)
+ lb $0,%tpoff(0)($0)
+ lh $0,0($0)
+ lh $0,%lo(0)($0)
+ lh $0,%hi(0)($0)
+ lh $0,%uhi(0)($0)
+ lh $0,%sdaoff(0)($0)
+ lh $0,%tpoff(0)($0)
+ lw $0,0($0)
+ lw $0,%lo(0)($0)
+ lw $0,%hi(0)($0)
+ lw $0,%uhi(0)($0)
+ lw $0,%sdaoff(0)($0)
+ lw $0,%tpoff(0)($0)
+ lbu $0,0($0)
+ lbu $0,%lo(0)($0)
+ lbu $0,%hi(0)($0)
+ lbu $0,%uhi(0)($0)
+ lbu $0,%sdaoff(0)($0)
+ lbu $0,%tpoff(0)($0)
+ lhu $0,0($0)
+ lhu $0,%lo(0)($0)
+ lhu $0,%hi(0)($0)
+ lhu $0,%uhi(0)($0)
+ lhu $0,%sdaoff(0)($0)
+ lhu $0,%tpoff(0)($0)
+ /* Should use 32 bit form */
+ sb $0,1($0)
+ sb $0,%lo(1)($0)
+ sb $0,%hi(1)($0)
+ sb $0,%uhi(1)($0)
+ sb $0,%sdaoff(1)($0)
+ sb $0,%tpoff(1)($0)
+ sh $0,1($0)
+ sh $0,%lo(1)($0)
+ sh $0,%hi(1)($0)
+ sh $0,%uhi(1)($0)
+ sh $0,%sdaoff(1)($0)
+ sh $0,%tpoff(1)($0)
+ sw $0,1($0)
+ sw $0,%lo(1)($0)
+ sw $0,%hi(1)($0)
+ sw $0,%uhi(1)($0)
+ sw $0,%sdaoff(1)($0)
+ sw $0,%tpoff(1)($0)
+ lb $0,1($0)
+ lb $0,%lo(1)($0)
+ lb $0,%hi(1)($0)
+ lb $0,%uhi(1)($0)
+ lb $0,%sdaoff(1)($0)
+ lb $0,%tpoff(1)($0)
+ lh $0,1($0)
+ lh $0,%lo(1)($0)
+ lh $0,%hi(1)($0)
+ lh $0,%uhi(1)($0)
+ lh $0,%sdaoff(1)($0)
+ lh $0,%tpoff(1)($0)
+ lw $0,1($0)
+ lw $0,%lo(1)($0)
+ lw $0,%hi(1)($0)
+ lw $0,%uhi(1)($0)
+ lw $0,%sdaoff(1)($0)
+ lw $0,%tpoff(1)($0)
+ lbu $0,1($0)
+ lbu $0,%lo(1)($0)
+ lbu $0,%hi(1)($0)
+ lbu $0,%uhi(1)($0)
+ lbu $0,%sdaoff(1)($0)
+ lbu $0,%tpoff(1)($0)
+ lhu $0,1($0)
+ lhu $0,%lo(1)($0)
+ lhu $0,%hi(1)($0)
+ lhu $0,%uhi(1)($0)
+ lhu $0,%sdaoff(1)($0)
+ lhu $0,%tpoff(1)($0)
+ /* Should use 32 bit form */
+ sb $0,case106821($0)
+ sb $0,%lo(case106821)($0)
+ sb $0,%hi(case106821)($0)
+ sb $0,%uhi(case106821)($0)
+ sh $0,case106821($0)
+ sh $0,%lo(case106821)($0)
+ sh $0,%hi(case106821)($0)
+ sh $0,%uhi(case106821)($0)
+ sw $0,case106821($0)
+ sw $0,%lo(case106821)($0)
+ sw $0,%hi(case106821)($0)
+ sw $0,%uhi(case106821)($0)
+ lb $0,case106821($0)
+ lb $0,%lo(case106821)($0)
+ lb $0,%hi(case106821)($0)
+ lb $0,%uhi(case106821)($0)
+ lh $0,case106821($0)
+ lh $0,%lo(case106821)($0)
+ lh $0,%hi(case106821)($0)
+ lh $0,%uhi(case106821)($0)
+ lw $0,case106821($0)
+ lw $0,%lo(case106821)($0)
+ lw $0,%hi(case106821)($0)
+ lw $0,%uhi(case106821)($0)
+ lbu $0,case106821($0)
+ lbu $0,%lo(case106821)($0)
+ lbu $0,%hi(case106821)($0)
+ lbu $0,%uhi(case106821)($0)
+ lhu $0,case106821($0)
+ lhu $0,%lo(case106821)($0)
+ lhu $0,%hi(case106821)($0)
+ lhu $0,%uhi(case106821)($0)
--- /dev/null
+#objdump: -dzr
+
+.*: *file format elf32-mep
+
+Disassembly of section \.text:
+
+.* <.*>:
+ .*: 00 00 * nop
+ .*: e4 51 00 04 * beq \$4,\$5,.* <foo>
+ .*: 00 00 * nop
+ .*: 00 00 * nop
+
+.* <foo>:
+ .*: 00 00 * nop
--- /dev/null
+ .globl foo
+ nop
+ beq $4,$5,foo
+ nop
+ nop
+foo:
+ nop
--- /dev/null
+# complex relocations testsuite
+
+proc ld_test { objects ldflags dest test } {
+ set ld_output [target_link $objects $dest $ldflags]
+ if [string match "" $ld_output] then { pass $test } else { fail $test }
+}
+
+proc ld_test_error { objects ldflags dest test } {
+ set ld_output [target_link $objects $dest $ldflags]
+ if [string match "" $ld_output] then { fail $test } else { pass $test }
+}
+
+proc objdump_test { exec flags dest test } {
+ set objdump [find_binutils_prog objdump]
+ verbose -log "$objdump $flags $exec > $dest"
+ catch "exec $objdump $flags $exec > $dest" objdump_output
+ if [string match "" $objdump_output] then { pass $test } else { fail $test }
+}
+
+proc regexp_test { file1 file2 test } {
+ if [regexp_diff $file1 $file2] then { fail $test } else { pass $test }
+}
+
+
+global srcdir subdir
+if [istarget mep*-*-*] {
+
+ # test that complex relocs between files work, generally
+ gas_test relocs-junk1.s {-mconfig=fmax -o relocs-junk1.o} {} {assembling relocs-junk1}
+ gas_test relocs-syms.s {-mconfig=fmax -o relocs-syms.o} {} {assembling relocs-syms}
+ gas_test relocs-junk2.s {-mconfig=fmax -o relocs-junk2.o} {} {assembling relocs-junk2}
+ gas_test relocs-refs.s {-mconfig=fmax -o relocs-refs.o} {} {assembling relocs-refs}
+ ld_test {relocs-junk1.o relocs-syms.o relocs-junk2.o relocs-refs.o} {--defsym __stack=0x1ffff0 --defsym __sbss_end=0x1000 -e 1233} {relocs.x} {linking relocs.x}
+ objdump_test {relocs.x} {-dzs} {relocs.dump} {disassembling relocs.x}
+ regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly for relocs.x}
+
+ foreach test {3} {
+ # perform specific negative boundary tests
+ gas_test "relocs-bad$test.s" [list -mconfig=fmax -o "relocs-bad$test.o"] {} [list assembling "relocs-bad$test"]
+ ld_test_error "relocs-bad$test.o" {-e 1233} "relocs-bad$test.x" [list linking "relocs-bad$test"]
+ }
+}
--- /dev/null
+#as:
+#objdump: -dr
+#name: dj1
+
+dump.o: file format elf32-mep
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 00 00 nop
+ 2: 01 00 mov \$1,\$0
+ 4: 02 00 mov \$2,\$0
+ 6: 03 00 mov \$3,\$0
+ 8: 04 00 mov \$4,\$0
+ a: 05 00 mov \$5,\$0
+ c: 06 00 mov \$6,\$0
+ e: 07 00 mov \$7,\$0
+ 10: 08 00 mov \$8,\$0
+ 12: 09 00 mov \$9,\$0
+ 14: 0a 00 mov \$10,\$0
+ 16: 0b 00 mov \$11,\$0
+ 18: 0c 00 mov \$12,\$0
+ 1a: 0d 00 mov \$tp,\$0
+ 1c: 0e 00 mov \$gp,\$0
+ 1e: 0f 00 mov \$sp,\$0
+ 20: 08 00 mov \$8,\$0
+ 22: 0d 00 mov \$tp,\$0
+ 24: 0e 00 mov \$gp,\$0
+ 26: 0f 00 mov \$sp,\$0
+ 28: 00 08 sb \$0,\(\$0\)
+ 2a: 00 09 sh \$0,\(\$0\)
+ 2c: 00 0a sw \$0,\(\$0\)
+ 2e: 00 0c lb \$0,\(\$0\)
+ 30: 00 0d lh \$0,\(\$0\)
+ 32: 00 0e lw \$0,\(\$0\)
+ 34: 00 0b lbu \$0,\(\$0\)
+ 36: 00 0f lhu \$0,\(\$0\)
+ 38: 0f 08 sb \$sp,\(\$0\)
+ 3a: 0f 09 sh \$sp,\(\$0\)
+ 3c: 0f 0a sw \$sp,\(\$0\)
+ 3e: 0f 0c lb \$sp,\(\$0\)
+ 40: 0f 0d lh \$sp,\(\$0\)
+ 42: 0f 0e lw \$sp,\(\$0\)
+ 44: 0f 0b lbu \$sp,\(\$0\)
+ 46: 0f 0f lhu \$sp,\(\$0\)
+ 48: 00 f8 sb \$0,\(\$sp\)
+ 4a: 00 f9 sh \$0,\(\$sp\)
+ 4c: 00 fa sw \$0,\(\$sp\)
+ 4e: 00 fc lb \$0,\(\$sp\)
+ 50: 00 fd lh \$0,\(\$sp\)
+ 52: 00 fe lw \$0,\(\$sp\)
+ 54: 00 fb lbu \$0,\(\$sp\)
+ 56: 00 ff lhu \$0,\(\$sp\)
+ 58: 0f f8 sb \$sp,\(\$sp\)
+ 5a: 0f f9 sh \$sp,\(\$sp\)
+ 5c: 0f fa sw \$sp,\(\$sp\)
+ 5e: 0f fc lb \$sp,\(\$sp\)
+ 60: 0f fd lh \$sp,\(\$sp\)
+ 62: 0f fe lw \$sp,\(\$sp\)
+ 64: 0f fb lbu \$sp,\(\$sp\)
+ 66: 0f ff lhu \$sp,\(\$sp\)
+ 68: 00 fa sw \$0,\(\$sp\)
+ 6a: 00 fe lw \$0,\(\$sp\)
+ 6c: 0f fa sw \$sp,\(\$sp\)
+ 6e: 0f fe lw \$sp,\(\$sp\)
+ 70: 40 7e sw \$0,0x7c\(\$sp\)
+ 72: 40 7f lw \$0,0x7c\(\$sp\)
+ 74: 4f 7e sw \$sp,0x7c\(\$sp\)
+ 76: 4f 7f lw \$sp,0x7c\(\$sp\)
+ 78: 00 fa sw \$0,\(\$sp\)
+ 7a: 00 fe lw \$0,\(\$sp\)
+ 7c: 0f fa sw \$sp,\(\$sp\)
+ 7e: 0f fe lw \$sp,\(\$sp\)
+ 80: 40 7e sw \$0,0x7c\(\$sp\)
+ 82: 40 7f lw \$0,0x7c\(\$sp\)
+ 84: 4f 7e sw \$sp,0x7c\(\$sp\)
+ 86: 4f 7f lw \$sp,0x7c\(\$sp\)
+ 88: 00 d8 sb \$0,\(\$tp\)
+ 8a: 00 dc lb \$0,\(\$tp\)
+ 8c: 00 db lbu \$0,\(\$tp\)
+ 8e: 07 d8 sb \$7,\(\$tp\)
+ 90: 07 dc lb \$7,\(\$tp\)
+ 92: 07 db lbu \$7,\(\$tp\)
+ 94: 80 7f sb \$0,0x7f\(\$tp\)
+ 96: 88 7f lb \$0,0x7f\(\$tp\)
+ 98: 48 ff lbu \$0,0x7f\(\$tp\)
+ 9a: 87 7f sb \$7,0x7f\(\$tp\)
+ 9c: 8f 7f lb \$7,0x7f\(\$tp\)
+ 9e: 4f ff lbu \$7,0x7f\(\$tp\)
+ a0: 80 00 sb \$0,0x0\(\$tp\)
+ a0: R_MEP_TPREL7 symbol
+ a2: 88 00 lb \$0,0x0\(\$tp\)
+ a2: R_MEP_TPREL7 symbol
+ a4: 48 80 lbu \$0,0x0\(\$tp\)
+ a4: R_MEP_TPREL7 symbol
+ a6: 87 00 sb \$7,0x0\(\$tp\)
+ a6: R_MEP_TPREL7 symbol
+ a8: 8f 00 lb \$7,0x0\(\$tp\)
+ a8: R_MEP_TPREL7 symbol
+ aa: 4f 80 lbu \$7,0x0\(\$tp\)
+ aa: R_MEP_TPREL7 symbol
+ ac: 00 d8 sb \$0,\(\$tp\)
+ ae: 00 dc lb \$0,\(\$tp\)
+ b0: 00 db lbu \$0,\(\$tp\)
+ b2: 07 d8 sb \$7,\(\$tp\)
+ b4: 07 dc lb \$7,\(\$tp\)
+ b6: 07 db lbu \$7,\(\$tp\)
+ b8: 80 7f sb \$0,0x7f\(\$tp\)
+ ba: 88 7f lb \$0,0x7f\(\$tp\)
+ bc: 48 ff lbu \$0,0x7f\(\$tp\)
+ be: 87 7f sb \$7,0x7f\(\$tp\)
+ c0: 8f 7f lb \$7,0x7f\(\$tp\)
+ c2: 4f ff lbu \$7,0x7f\(\$tp\)
+ c4: 80 00 sb \$0,0x0\(\$tp\)
+ c4: R_MEP_TPREL7 symbol
+ c6: 88 00 lb \$0,0x0\(\$tp\)
+ c6: R_MEP_TPREL7 symbol
+ c8: 48 80 lbu \$0,0x0\(\$tp\)
+ c8: R_MEP_TPREL7 symbol
+ ca: 87 00 sb \$7,0x0\(\$tp\)
+ ca: R_MEP_TPREL7 symbol
+ cc: 8f 00 lb \$7,0x0\(\$tp\)
+ cc: R_MEP_TPREL7 symbol
+ ce: 4f 80 lbu \$7,0x0\(\$tp\)
+ ce: R_MEP_TPREL7 symbol
+ d0: 00 d9 sh \$0,\(\$tp\)
+ d2: 00 dd lh \$0,\(\$tp\)
+ d4: 00 df lhu \$0,\(\$tp\)
+ d6: 07 d9 sh \$7,\(\$tp\)
+ d8: 07 dd lh \$7,\(\$tp\)
+ da: 07 df lhu \$7,\(\$tp\)
+ dc: 80 fe sh \$0,0x7e\(\$tp\)
+ de: 88 fe lh \$0,0x7e\(\$tp\)
+ e0: 88 ff lhu \$0,0x7e\(\$tp\)
+ e2: 87 fe sh \$7,0x7e\(\$tp\)
+ e4: 8f fe lh \$7,0x7e\(\$tp\)
+ e6: 8f ff lhu \$7,0x7e\(\$tp\)
+ e8: 80 80 sh \$0,0x0\(\$tp\)
+ e8: R_MEP_TPREL7A2 symbol
+ ea: 88 80 lh \$0,0x0\(\$tp\)
+ ea: R_MEP_TPREL7A2 symbol
+ ec: 88 81 lhu \$0,0x0\(\$tp\)
+ ec: R_MEP_TPREL7A2 symbol
+ ee: 87 80 sh \$7,0x0\(\$tp\)
+ ee: R_MEP_TPREL7A2 symbol
+ f0: 8f 80 lh \$7,0x0\(\$tp\)
+ f0: R_MEP_TPREL7A2 symbol
+ f2: 8f 81 lhu \$7,0x0\(\$tp\)
+ f2: R_MEP_TPREL7A2 symbol
+ f4: 00 d9 sh \$0,\(\$tp\)
+ f6: 00 dd lh \$0,\(\$tp\)
+ f8: 00 df lhu \$0,\(\$tp\)
+ fa: 07 d9 sh \$7,\(\$tp\)
+ fc: 07 dd lh \$7,\(\$tp\)
+ fe: 07 df lhu \$7,\(\$tp\)
+ 100: 80 fe sh \$0,0x7e\(\$tp\)
+ 102: 88 fe lh \$0,0x7e\(\$tp\)
+ 104: 88 ff lhu \$0,0x7e\(\$tp\)
+ 106: 87 fe sh \$7,0x7e\(\$tp\)
+ 108: 8f fe lh \$7,0x7e\(\$tp\)
+ 10a: 8f ff lhu \$7,0x7e\(\$tp\)
+ 10c: 80 80 sh \$0,0x0\(\$tp\)
+ 10c: R_MEP_TPREL7A2 symbol
+ 10e: 88 80 lh \$0,0x0\(\$tp\)
+ 10e: R_MEP_TPREL7A2 symbol
+ 110: 88 81 lhu \$0,0x0\(\$tp\)
+ 110: R_MEP_TPREL7A2 symbol
+ 112: 87 80 sh \$7,0x0\(\$tp\)
+ 112: R_MEP_TPREL7A2 symbol
+ 114: 8f 80 lh \$7,0x0\(\$tp\)
+ 114: R_MEP_TPREL7A2 symbol
+ 116: 8f 81 lhu \$7,0x0\(\$tp\)
+ 116: R_MEP_TPREL7A2 symbol
+ 118: 00 da sw \$0,\(\$tp\)
+ 11a: 00 de lw \$0,\(\$tp\)
+ 11c: 07 da sw \$7,\(\$tp\)
+ 11e: 07 de lw \$7,\(\$tp\)
+ 120: 40 fe sw \$0,0x7c\(\$tp\)
+ 122: 40 ff lw \$0,0x7c\(\$tp\)
+ 124: 47 fe sw \$7,0x7c\(\$tp\)
+ 126: 47 ff lw \$7,0x7c\(\$tp\)
+ 128: 40 82 sw \$0,0x0\(\$tp\)
+ 128: R_MEP_TPREL7A4 symbol
+ 12a: 40 83 lw \$0,0x0\(\$tp\)
+ 12a: R_MEP_TPREL7A4 symbol
+ 12c: 47 82 sw \$7,0x0\(\$tp\)
+ 12c: R_MEP_TPREL7A4 symbol
+ 12e: 47 83 lw \$7,0x0\(\$tp\)
+ 12e: R_MEP_TPREL7A4 symbol
+ 130: 00 da sw \$0,\(\$tp\)
+ 132: 00 de lw \$0,\(\$tp\)
+ 134: 07 da sw \$7,\(\$tp\)
+ 136: 07 de lw \$7,\(\$tp\)
+ 138: 40 fe sw \$0,0x7c\(\$tp\)
+ 13a: 40 ff lw \$0,0x7c\(\$tp\)
+ 13c: 47 fe sw \$7,0x7c\(\$tp\)
+ 13e: 47 ff lw \$7,0x7c\(\$tp\)
+ 140: 40 82 sw \$0,0x0\(\$tp\)
+ 140: R_MEP_TPREL7A4 symbol
+ 142: 40 83 lw \$0,0x0\(\$tp\)
+ 142: R_MEP_TPREL7A4 symbol
+ 144: 47 82 sw \$7,0x0\(\$tp\)
+ 144: R_MEP_TPREL7A4 symbol
+ 146: 47 83 lw \$7,0x0\(\$tp\)
+ 146: R_MEP_TPREL7A4 symbol
+ 148: c0 08 80 00 sb \$0,-32768\(\$0\)
+ 14c: c0 09 80 00 sh \$0,-32768\(\$0\)
+ 150: c0 0a 80 00 sw \$0,-32768\(\$0\)
+ 154: c0 0c 80 00 lb \$0,-32768\(\$0\)
+ 158: c0 0d 80 00 lh \$0,-32768\(\$0\)
+ 15c: c0 0e 80 00 lw \$0,-32768\(\$0\)
+ 160: c0 0b 80 00 lbu \$0,-32768\(\$0\)
+ 164: c0 0f 80 00 lhu \$0,-32768\(\$0\)
+ 168: cf 08 80 00 sb \$sp,-32768\(\$0\)
+ 16c: cf 09 80 00 sh \$sp,-32768\(\$0\)
+ 170: cf 0a 80 00 sw \$sp,-32768\(\$0\)
+ 174: cf 0c 80 00 lb \$sp,-32768\(\$0\)
+ 178: cf 0d 80 00 lh \$sp,-32768\(\$0\)
+ 17c: cf 0e 80 00 lw \$sp,-32768\(\$0\)
+ 180: cf 0b 80 00 lbu \$sp,-32768\(\$0\)
+ 184: cf 0f 80 00 lhu \$sp,-32768\(\$0\)
+ 188: c0 08 7f ff sb \$0,32767\(\$0\)
+ 18c: c0 09 7f ff sh \$0,32767\(\$0\)
+ 190: c0 0a 7f ff sw \$0,32767\(\$0\)
+ 194: c0 0c 7f ff lb \$0,32767\(\$0\)
+ 198: c0 0d 7f ff lh \$0,32767\(\$0\)
+ 19c: c0 0e 7f ff lw \$0,32767\(\$0\)
+ 1a0: c0 0b 7f ff lbu \$0,32767\(\$0\)
+ 1a4: c0 0f 7f ff lhu \$0,32767\(\$0\)
+ 1a8: cf 08 7f ff sb \$sp,32767\(\$0\)
+ 1ac: cf 09 7f ff sh \$sp,32767\(\$0\)
+ 1b0: cf 0a 7f ff sw \$sp,32767\(\$0\)
+ 1b4: cf 0c 7f ff lb \$sp,32767\(\$0\)
+ 1b8: cf 0d 7f ff lh \$sp,32767\(\$0\)
+ 1bc: cf 0e 7f ff lw \$sp,32767\(\$0\)
+ 1c0: cf 0b 7f ff lbu \$sp,32767\(\$0\)
+ 1c4: cf 0f 7f ff lhu \$sp,32767\(\$0\)
+ 1c8: c0 08 00 00 sb \$0,0\(\$0\)
+ 1c8: R_MEP_GPREL symbol
+ 1cc: c0 09 00 00 sh \$0,0\(\$0\)
+ 1cc: R_MEP_GPREL symbol
+ 1d0: c0 0a 00 00 sw \$0,0\(\$0\)
+ 1d0: R_MEP_GPREL symbol
+ 1d4: c0 0c 00 00 lb \$0,0\(\$0\)
+ 1d4: R_MEP_GPREL symbol
+ 1d8: c0 0d 00 00 lh \$0,0\(\$0\)
+ 1d8: R_MEP_GPREL symbol
+ 1dc: c0 0e 00 00 lw \$0,0\(\$0\)
+ 1dc: R_MEP_GPREL symbol
+ 1e0: c0 0b 00 00 lbu \$0,0\(\$0\)
+ 1e0: R_MEP_GPREL symbol
+ 1e4: c0 0f 00 00 lhu \$0,0\(\$0\)
+ 1e4: R_MEP_GPREL symbol
+ 1e8: cf 08 00 00 sb \$sp,0\(\$0\)
+ 1e8: R_MEP_GPREL symbol
+ 1ec: cf 09 00 00 sh \$sp,0\(\$0\)
+ 1ec: R_MEP_GPREL symbol
+ 1f0: cf 0a 00 00 sw \$sp,0\(\$0\)
+ 1f0: R_MEP_GPREL symbol
+ 1f4: cf 0c 00 00 lb \$sp,0\(\$0\)
+ 1f4: R_MEP_GPREL symbol
+ 1f8: cf 0d 00 00 lh \$sp,0\(\$0\)
+ 1f8: R_MEP_GPREL symbol
+ 1fc: cf 0e 00 00 lw \$sp,0\(\$0\)
+ 1fc: R_MEP_GPREL symbol
+ 200: cf 0b 00 00 lbu \$sp,0\(\$0\)
+ 200: R_MEP_GPREL symbol
+ 204: cf 0f 00 00 lhu \$sp,0\(\$0\)
+ 204: R_MEP_GPREL symbol
+ 208: c0 08 80 00 sb \$0,-32768\(\$0\)
+ 20c: c0 09 80 00 sh \$0,-32768\(\$0\)
+ 210: c0 0a 80 00 sw \$0,-32768\(\$0\)
+ 214: c0 0c 80 00 lb \$0,-32768\(\$0\)
+ 218: c0 0d 80 00 lh \$0,-32768\(\$0\)
+ 21c: c0 0e 80 00 lw \$0,-32768\(\$0\)
+ 220: c0 0b 80 00 lbu \$0,-32768\(\$0\)
+ 224: c0 0f 80 00 lhu \$0,-32768\(\$0\)
+ 228: cf 08 80 00 sb \$sp,-32768\(\$0\)
+ 22c: cf 09 80 00 sh \$sp,-32768\(\$0\)
+ 230: cf 0a 80 00 sw \$sp,-32768\(\$0\)
+ 234: cf 0c 80 00 lb \$sp,-32768\(\$0\)
+ 238: cf 0d 80 00 lh \$sp,-32768\(\$0\)
+ 23c: cf 0e 80 00 lw \$sp,-32768\(\$0\)
+ 240: cf 0b 80 00 lbu \$sp,-32768\(\$0\)
+ 244: cf 0f 80 00 lhu \$sp,-32768\(\$0\)
+ 248: c0 08 7f ff sb \$0,32767\(\$0\)
+ 24c: c0 09 7f ff sh \$0,32767\(\$0\)
+ 250: c0 0a 7f ff sw \$0,32767\(\$0\)
+ 254: c0 0c 7f ff lb \$0,32767\(\$0\)
+ 258: c0 0d 7f ff lh \$0,32767\(\$0\)
+ 25c: c0 0e 7f ff lw \$0,32767\(\$0\)
+ 260: c0 0b 7f ff lbu \$0,32767\(\$0\)
+ 264: c0 0f 7f ff lhu \$0,32767\(\$0\)
+ 268: cf 08 7f ff sb \$sp,32767\(\$0\)
+ 26c: cf 09 7f ff sh \$sp,32767\(\$0\)
+ 270: cf 0a 7f ff sw \$sp,32767\(\$0\)
+ 274: cf 0c 7f ff lb \$sp,32767\(\$0\)
+ 278: cf 0d 7f ff lh \$sp,32767\(\$0\)
+ 27c: cf 0e 7f ff lw \$sp,32767\(\$0\)
+ 280: cf 0b 7f ff lbu \$sp,32767\(\$0\)
+ 284: cf 0f 7f ff lhu \$sp,32767\(\$0\)
+ 288: c0 08 00 00 sb \$0,0\(\$0\)
+ 288: R_MEP_TPREL symbol
+ 28c: c0 09 00 00 sh \$0,0\(\$0\)
+ 28c: R_MEP_TPREL symbol
+ 290: c0 0a 00 00 sw \$0,0\(\$0\)
+ 290: R_MEP_TPREL symbol
+ 294: c0 0c 00 00 lb \$0,0\(\$0\)
+ 294: R_MEP_TPREL symbol
+ 298: c0 0d 00 00 lh \$0,0\(\$0\)
+ 298: R_MEP_TPREL symbol
+ 29c: c0 0e 00 00 lw \$0,0\(\$0\)
+ 29c: R_MEP_TPREL symbol
+ 2a0: c0 0b 00 00 lbu \$0,0\(\$0\)
+ 2a0: R_MEP_TPREL symbol
+ 2a4: c0 0f 00 00 lhu \$0,0\(\$0\)
+ 2a4: R_MEP_TPREL symbol
+ 2a8: cf 08 00 00 sb \$sp,0\(\$0\)
+ 2a8: R_MEP_TPREL symbol
+ 2ac: cf 09 00 00 sh \$sp,0\(\$0\)
+ 2ac: R_MEP_TPREL symbol
+ 2b0: cf 0a 00 00 sw \$sp,0\(\$0\)
+ 2b0: R_MEP_TPREL symbol
+ 2b4: cf 0c 00 00 lb \$sp,0\(\$0\)
+ 2b4: R_MEP_TPREL symbol
+ 2b8: cf 0d 00 00 lh \$sp,0\(\$0\)
+ 2b8: R_MEP_TPREL symbol
+ 2bc: cf 0e 00 00 lw \$sp,0\(\$0\)
+ 2bc: R_MEP_TPREL symbol
+ 2c0: cf 0b 00 00 lbu \$sp,0\(\$0\)
+ 2c0: R_MEP_TPREL symbol
+ 2c4: cf 0f 00 00 lhu \$sp,0\(\$0\)
+ 2c4: R_MEP_TPREL symbol
+ 2c8: c0 f8 80 00 sb \$0,-32768\(\$sp\)
+ 2cc: c0 f9 80 00 sh \$0,-32768\(\$sp\)
+ 2d0: c0 fa 80 00 sw \$0,-32768\(\$sp\)
+ 2d4: c0 fc 80 00 lb \$0,-32768\(\$sp\)
+ 2d8: c0 fd 80 00 lh \$0,-32768\(\$sp\)
+ 2dc: c0 fe 80 00 lw \$0,-32768\(\$sp\)
+ 2e0: c0 fb 80 00 lbu \$0,-32768\(\$sp\)
+ 2e4: c0 ff 80 00 lhu \$0,-32768\(\$sp\)
+ 2e8: cf f8 80 00 sb \$sp,-32768\(\$sp\)
+ 2ec: cf f9 80 00 sh \$sp,-32768\(\$sp\)
+ 2f0: cf fa 80 00 sw \$sp,-32768\(\$sp\)
+ 2f4: cf fc 80 00 lb \$sp,-32768\(\$sp\)
+ 2f8: cf fd 80 00 lh \$sp,-32768\(\$sp\)
+ 2fc: cf fe 80 00 lw \$sp,-32768\(\$sp\)
+ 300: cf fb 80 00 lbu \$sp,-32768\(\$sp\)
+ 304: cf ff 80 00 lhu \$sp,-32768\(\$sp\)
+ 308: c0 f8 7f ff sb \$0,32767\(\$sp\)
+ 30c: c0 f9 7f ff sh \$0,32767\(\$sp\)
+ 310: c0 fa 7f ff sw \$0,32767\(\$sp\)
+ 314: c0 fc 7f ff lb \$0,32767\(\$sp\)
+ 318: c0 fd 7f ff lh \$0,32767\(\$sp\)
+ 31c: c0 fe 7f ff lw \$0,32767\(\$sp\)
+ 320: c0 fb 7f ff lbu \$0,32767\(\$sp\)
+ 324: c0 ff 7f ff lhu \$0,32767\(\$sp\)
+ 328: cf f8 7f ff sb \$sp,32767\(\$sp\)
+ 32c: cf f9 7f ff sh \$sp,32767\(\$sp\)
+ 330: cf fa 7f ff sw \$sp,32767\(\$sp\)
+ 334: cf fc 7f ff lb \$sp,32767\(\$sp\)
+ 338: cf fd 7f ff lh \$sp,32767\(\$sp\)
+ 33c: cf fe 7f ff lw \$sp,32767\(\$sp\)
+ 340: cf fb 7f ff lbu \$sp,32767\(\$sp\)
+ 344: cf ff 7f ff lhu \$sp,32767\(\$sp\)
+ 348: c0 f8 00 00 sb \$0,0\(\$sp\)
+ 348: R_MEP_GPREL symbol
+ 34c: c0 f9 00 00 sh \$0,0\(\$sp\)
+ 34c: R_MEP_GPREL symbol
+ 350: c0 fa 00 00 sw \$0,0\(\$sp\)
+ 350: R_MEP_GPREL symbol
+ 354: c0 fc 00 00 lb \$0,0\(\$sp\)
+ 354: R_MEP_GPREL symbol
+ 358: c0 fd 00 00 lh \$0,0\(\$sp\)
+ 358: R_MEP_GPREL symbol
+ 35c: c0 fe 00 00 lw \$0,0\(\$sp\)
+ 35c: R_MEP_GPREL symbol
+ 360: c0 fb 00 00 lbu \$0,0\(\$sp\)
+ 360: R_MEP_GPREL symbol
+ 364: c0 ff 00 00 lhu \$0,0\(\$sp\)
+ 364: R_MEP_GPREL symbol
+ 368: cf f8 00 00 sb \$sp,0\(\$sp\)
+ 368: R_MEP_GPREL symbol
+ 36c: cf f9 00 00 sh \$sp,0\(\$sp\)
+ 36c: R_MEP_GPREL symbol
+ 370: cf fa 00 00 sw \$sp,0\(\$sp\)
+ 370: R_MEP_GPREL symbol
+ 374: cf fc 00 00 lb \$sp,0\(\$sp\)
+ 374: R_MEP_GPREL symbol
+ 378: cf fd 00 00 lh \$sp,0\(\$sp\)
+ 378: R_MEP_GPREL symbol
+ 37c: cf fe 00 00 lw \$sp,0\(\$sp\)
+ 37c: R_MEP_GPREL symbol
+ 380: cf fb 00 00 lbu \$sp,0\(\$sp\)
+ 380: R_MEP_GPREL symbol
+ 384: cf ff 00 00 lhu \$sp,0\(\$sp\)
+ 384: R_MEP_GPREL symbol
+ 388: c0 f8 80 00 sb \$0,-32768\(\$sp\)
+ 38c: c0 f9 80 00 sh \$0,-32768\(\$sp\)
+ 390: c0 fa 80 00 sw \$0,-32768\(\$sp\)
+ 394: c0 fc 80 00 lb \$0,-32768\(\$sp\)
+ 398: c0 fd 80 00 lh \$0,-32768\(\$sp\)
+ 39c: c0 fe 80 00 lw \$0,-32768\(\$sp\)
+ 3a0: c0 fb 80 00 lbu \$0,-32768\(\$sp\)
+ 3a4: c0 ff 80 00 lhu \$0,-32768\(\$sp\)
+ 3a8: cf f8 80 00 sb \$sp,-32768\(\$sp\)
+ 3ac: cf f9 80 00 sh \$sp,-32768\(\$sp\)
+ 3b0: cf fa 80 00 sw \$sp,-32768\(\$sp\)
+ 3b4: cf fc 80 00 lb \$sp,-32768\(\$sp\)
+ 3b8: cf fd 80 00 lh \$sp,-32768\(\$sp\)
+ 3bc: cf fe 80 00 lw \$sp,-32768\(\$sp\)
+ 3c0: cf fb 80 00 lbu \$sp,-32768\(\$sp\)
+ 3c4: cf ff 80 00 lhu \$sp,-32768\(\$sp\)
+ 3c8: c0 f8 7f ff sb \$0,32767\(\$sp\)
+ 3cc: c0 f9 7f ff sh \$0,32767\(\$sp\)
+ 3d0: c0 fa 7f ff sw \$0,32767\(\$sp\)
+ 3d4: c0 fc 7f ff lb \$0,32767\(\$sp\)
+ 3d8: c0 fd 7f ff lh \$0,32767\(\$sp\)
+ 3dc: c0 fe 7f ff lw \$0,32767\(\$sp\)
+ 3e0: c0 fb 7f ff lbu \$0,32767\(\$sp\)
+ 3e4: c0 ff 7f ff lhu \$0,32767\(\$sp\)
+ 3e8: cf f8 7f ff sb \$sp,32767\(\$sp\)
+ 3ec: cf f9 7f ff sh \$sp,32767\(\$sp\)
+ 3f0: cf fa 7f ff sw \$sp,32767\(\$sp\)
+ 3f4: cf fc 7f ff lb \$sp,32767\(\$sp\)
+ 3f8: cf fd 7f ff lh \$sp,32767\(\$sp\)
+ 3fc: cf fe 7f ff lw \$sp,32767\(\$sp\)
+ 400: cf fb 7f ff lbu \$sp,32767\(\$sp\)
+ 404: cf ff 7f ff lhu \$sp,32767\(\$sp\)
+ 408: c0 f8 00 00 sb \$0,0\(\$sp\)
+ 408: R_MEP_TPREL symbol
+ 40c: c0 f9 00 00 sh \$0,0\(\$sp\)
+ 40c: R_MEP_TPREL symbol
+ 410: 40 02 sw \$0,0x0\(\$sp\)
+ 410: R_MEP_TPREL7A4 symbol
+ 412: c0 fc 00 00 lb \$0,0\(\$sp\)
+ 412: R_MEP_TPREL symbol
+ 416: c0 fd 00 00 lh \$0,0\(\$sp\)
+ 416: R_MEP_TPREL symbol
+ 41a: 40 03 lw \$0,0x0\(\$sp\)
+ 41a: R_MEP_TPREL7A4 symbol
+ 41c: c0 fb 00 00 lbu \$0,0\(\$sp\)
+ 41c: R_MEP_TPREL symbol
+ 420: c0 ff 00 00 lhu \$0,0\(\$sp\)
+ 420: R_MEP_TPREL symbol
+ 424: cf f8 00 00 sb \$sp,0\(\$sp\)
+ 424: R_MEP_TPREL symbol
+ 428: cf f9 00 00 sh \$sp,0\(\$sp\)
+ 428: R_MEP_TPREL symbol
+ 42c: 4f 02 sw \$sp,0x0\(\$sp\)
+ 42c: R_MEP_TPREL7A4 symbol
+ 42e: cf fc 00 00 lb \$sp,0\(\$sp\)
+ 42e: R_MEP_TPREL symbol
+ 432: cf fd 00 00 lh \$sp,0\(\$sp\)
+ 432: R_MEP_TPREL symbol
+ 436: 4f 03 lw \$sp,0x0\(\$sp\)
+ 436: R_MEP_TPREL7A4 symbol
+ 438: cf fb 00 00 lbu \$sp,0\(\$sp\)
+ 438: R_MEP_TPREL symbol
+ 43c: cf ff 00 00 lhu \$sp,0\(\$sp\)
+ 43c: R_MEP_TPREL symbol
+ 440: e0 02 00 00 sw \$0,\(0x0\)
+ 444: e0 03 00 00 lw \$0,\(0x0\)
+ 448: ef 02 00 00 sw \$sp,\(0x0\)
+ 44c: ef 03 00 00 lw \$sp,\(0x0\)
+ 450: e0 fe ff ff sw \$0,\(0xfffffc\)
+ 454: e0 ff ff ff lw \$0,\(0xfffffc\)
+ 458: ef fe ff ff sw \$sp,\(0xfffffc\)
+ 45c: ef ff ff ff lw \$sp,\(0xfffffc\)
+ 460: e0 02 00 00 sw \$0,\(0x0\)
+ 460: R_MEP_ADDR24A4 symbol
+ 464: e0 03 00 00 lw \$0,\(0x0\)
+ 464: R_MEP_ADDR24A4 symbol
+ 468: ef 02 00 00 sw \$sp,\(0x0\)
+ 468: R_MEP_ADDR24A4 symbol
+ 46c: ef 03 00 00 lw \$sp,\(0x0\)
+ 46c: R_MEP_ADDR24A4 symbol
+ 470: 10 0d extb \$0
+ 472: 10 8d extub \$0
+ 474: 10 2d exth \$0
+ 476: 10 ad extuh \$0
+ 478: 1f 0d extb \$sp
+ 47a: 1f 8d extub \$sp
+ 47c: 1f 2d exth \$sp
+ 47e: 1f ad extuh \$sp
+ 480: 10 0c ssarb 0\(\$0\)
+ 482: 13 0c ssarb 3\(\$0\)
+ 484: 10 fc ssarb 0\(\$sp\)
+ 486: 13 fc ssarb 3\(\$sp\)
+ 488: 00 00 nop
+ 48a: 0f 00 mov \$sp,\$0
+ 48c: 00 f0 mov \$0,\$sp
+ 48e: 0f f0 mov \$sp,\$sp
+ 490: c0 01 80 00 mov \$0,-32768
+ 494: cf 01 80 00 mov \$sp,-32768
+ 498: 50 80 mov \$0,-128
+ 49a: 5f 80 mov \$sp,-128
+ 49c: 50 00 mov \$0,0
+ 49e: 5f 00 mov \$sp,0
+ 4a0: 50 7f mov \$0,127
+ 4a2: 5f 7f mov \$sp,127
+ 4a4: c0 01 7f ff mov \$0,32767
+ 4a8: cf 01 7f ff mov \$sp,32767
+ 4ac: c0 01 00 00 mov \$0,0
+ 4ac: R_MEP_LOW16 symbol
+ 4b0: c0 01 00 00 mov \$0,0
+ 4b0: R_MEP_HI16S symbol
+ 4b4: c0 01 00 00 mov \$0,0
+ 4b4: R_MEP_HI16U symbol
+ 4b8: c0 01 00 00 mov \$0,0
+ 4b8: R_MEP_GPREL symbol
+ 4bc: c0 01 00 00 mov \$0,0
+ 4bc: R_MEP_TPREL symbol
+ 4c0: d0 00 00 00 movu \$0,0x0
+ 4c4: d7 00 00 00 movu \$7,0x0
+ 4c8: d0 ff ff ff movu \$0,0xffffff
+ 4cc: d7 ff ff ff movu \$7,0xffffff
+ 4d0: c0 11 00 00 movu \$0,0x0
+ 4d0: R_MEP_LOW16 symbol
+ 4d4: c7 11 00 00 movu \$7,0x0
+ 4d4: R_MEP_LOW16 symbol
+ 4d8: d0 00 00 00 movu \$0,0x0
+ 4d8: R_MEP_UIMM24 symbol
+ 4dc: d7 00 00 00 movu \$7,0x0
+ 4dc: R_MEP_UIMM24 symbol
+ 4e0: d0 00 00 00 movu \$0,0x0
+ 4e4: c0 21 00 00 movh \$0,0x0
+ 4e8: cf 11 00 00 movu \$sp,0x0
+ 4ec: cf 21 00 00 movh \$sp,0x0
+ 4f0: d0 ff 00 ff movu \$0,0xffff
+ 4f4: c0 21 ff ff movh \$0,0xffff
+ 4f8: cf 11 ff ff movu \$sp,0xffff
+ 4fc: cf 21 ff ff movh \$sp,0xffff
+ 500: c0 11 00 00 movu \$0,0x0
+ 500: R_MEP_LOW16 symbol
+ 504: c0 21 00 00 movh \$0,0x0
+ 504: R_MEP_LOW16 symbol
+ 508: cf 11 00 00 movu \$sp,0x0
+ 508: R_MEP_LOW16 symbol
+ 50c: cf 21 00 00 movh \$sp,0x0
+ 50c: R_MEP_LOW16 symbol
+ 510: c0 11 00 00 movu \$0,0x0
+ 510: R_MEP_HI16S symbol
+ 514: c0 21 00 00 movh \$0,0x0
+ 514: R_MEP_HI16S symbol
+ 518: cf 11 00 00 movu \$sp,0x0
+ 518: R_MEP_HI16S symbol
+ 51c: cf 21 00 00 movh \$sp,0x0
+ 51c: R_MEP_HI16S symbol
+ 520: c0 11 00 00 movu \$0,0x0
+ 520: R_MEP_HI16U symbol
+ 524: c0 21 00 00 movh \$0,0x0
+ 524: R_MEP_HI16U symbol
+ 528: cf 11 00 00 movu \$sp,0x0
+ 528: R_MEP_HI16U symbol
+ 52c: cf 21 00 00 movh \$sp,0x0
+ 52c: R_MEP_HI16U symbol
+ 530: c0 11 56 78 movu \$0,0x5678
+ 534: c0 21 56 78 movh \$0,0x5678
+ 538: cf 11 56 78 movu \$sp,0x5678
+ 53c: cf 21 56 78 movh \$sp,0x5678
+ 540: c0 11 12 34 movu \$0,0x1234
+ 544: c0 21 12 34 movh \$0,0x1234
+ 548: cf 11 12 34 movu \$sp,0x1234
+ 54c: cf 21 12 34 movh \$sp,0x1234
+ 550: c0 11 12 34 movu \$0,0x1234
+ 554: c0 21 12 34 movh \$0,0x1234
+ 558: cf 11 12 34 movu \$sp,0x1234
+ 55c: cf 21 12 34 movh \$sp,0x1234
+ 560: 90 00 add3 \$0,\$0,\$0
+ 562: 90 0f add3 \$sp,\$0,\$0
+ 564: 9f 00 add3 \$0,\$sp,\$0
+ 566: 9f 0f add3 \$sp,\$sp,\$0
+ 568: 90 f0 add3 \$0,\$0,\$sp
+ 56a: 90 ff add3 \$sp,\$0,\$sp
+ 56c: 9f f0 add3 \$0,\$sp,\$sp
+ 56e: 9f ff add3 \$sp,\$sp,\$sp
+ 570: 60 c0 add \$0,-16
+ 572: 6f c0 add \$sp,-16
+ 574: 60 00 add \$0,0
+ 576: 6f 00 add \$sp,0
+ 578: 60 3c add \$0,15
+ 57a: 6f 3c add \$sp,15
+ 57c: 40 00 add3 \$0,\$sp,0x0
+ 57e: 4f 00 add3 \$sp,\$sp,0x0
+ 580: 40 7c add3 \$0,\$sp,0x7c
+ 582: 4f 7c add3 \$sp,\$sp,0x7c
+ 584: c0 f0 00 01 add3 \$0,\$sp,1
+ 588: cf f0 00 01 add3 \$sp,\$sp,1
+ 58c: 00 07 advck3 \$0,\$0,\$0
+ 58e: 00 05 sbvck3 \$0,\$0,\$0
+ 590: 0f 07 advck3 \$0,\$sp,\$0
+ 592: 0f 05 sbvck3 \$0,\$sp,\$0
+ 594: 00 f7 advck3 \$0,\$0,\$sp
+ 596: 00 f5 sbvck3 \$0,\$0,\$sp
+ 598: 0f f7 advck3 \$0,\$sp,\$sp
+ 59a: 0f f5 sbvck3 \$0,\$sp,\$sp
+ 59c: 00 04 sub \$0,\$0
+ 59e: 00 01 neg \$0,\$0
+ 5a0: 0f 04 sub \$sp,\$0
+ 5a2: 0f 01 neg \$sp,\$0
+ 5a4: 00 f4 sub \$0,\$sp
+ 5a6: 00 f1 neg \$0,\$sp
+ 5a8: 0f f4 sub \$sp,\$sp
+ 5aa: 0f f1 neg \$sp,\$sp
+ 5ac: 00 02 slt3 \$0,\$0,\$0
+ 5ae: 00 03 sltu3 \$0,\$0,\$0
+ 5b0: 20 06 sl1ad3 \$0,\$0,\$0
+ 5b2: 20 07 sl2ad3 \$0,\$0,\$0
+ 5b4: 0f 02 slt3 \$0,\$sp,\$0
+ 5b6: 0f 03 sltu3 \$0,\$sp,\$0
+ 5b8: 2f 06 sl1ad3 \$0,\$sp,\$0
+ 5ba: 2f 07 sl2ad3 \$0,\$sp,\$0
+ 5bc: 00 f2 slt3 \$0,\$0,\$sp
+ 5be: 00 f3 sltu3 \$0,\$0,\$sp
+ 5c0: 20 f6 sl1ad3 \$0,\$0,\$sp
+ 5c2: 20 f7 sl2ad3 \$0,\$0,\$sp
+ 5c4: 0f f2 slt3 \$0,\$sp,\$sp
+ 5c6: 0f f3 sltu3 \$0,\$sp,\$sp
+ 5c8: 2f f6 sl1ad3 \$0,\$sp,\$sp
+ 5ca: 2f f7 sl2ad3 \$0,\$sp,\$sp
+ 5cc: c0 00 80 00 add3 \$0,\$0,-32768
+ 5d0: cf 00 80 00 add3 \$sp,\$0,-32768
+ 5d4: c0 f0 80 00 add3 \$0,\$sp,-32768
+ 5d8: cf f0 80 00 add3 \$sp,\$sp,-32768
+ 5dc: c0 00 7f ff add3 \$0,\$0,32767
+ 5e0: cf 00 7f ff add3 \$sp,\$0,32767
+ 5e4: c0 f0 7f ff add3 \$0,\$sp,32767
+ 5e8: cf f0 7f ff add3 \$sp,\$sp,32767
+ 5ec: c0 00 00 00 add3 \$0,\$0,0
+ 5ec: R_MEP_LOW16 symbol
+ 5f0: cf 00 00 00 add3 \$sp,\$0,0
+ 5f0: R_MEP_LOW16 symbol
+ 5f4: c0 f0 00 00 add3 \$0,\$sp,0
+ 5f4: R_MEP_LOW16 symbol
+ 5f8: cf f0 00 00 add3 \$sp,\$sp,0
+ 5f8: R_MEP_LOW16 symbol
+ 5fc: 60 01 slt3 \$0,\$0,0x0
+ 5fe: 60 05 sltu3 \$0,\$0,0x0
+ 600: 6f 01 slt3 \$0,\$sp,0x0
+ 602: 6f 05 sltu3 \$0,\$sp,0x0
+ 604: 60 f9 slt3 \$0,\$0,0x1f
+ 606: 60 fd sltu3 \$0,\$0,0x1f
+ 608: 6f f9 slt3 \$0,\$sp,0x1f
+ 60a: 6f fd sltu3 \$0,\$sp,0x1f
+ 60c: 10 00 or \$0,\$0
+ 60e: 10 01 and \$0,\$0
+ 610: 10 02 xor \$0,\$0
+ 612: 10 03 nor \$0,\$0
+ 614: 1f 00 or \$sp,\$0
+ 616: 1f 01 and \$sp,\$0
+ 618: 1f 02 xor \$sp,\$0
+ 61a: 1f 03 nor \$sp,\$0
+ 61c: 10 f0 or \$0,\$sp
+ 61e: 10 f1 and \$0,\$sp
+ 620: 10 f2 xor \$0,\$sp
+ 622: 10 f3 nor \$0,\$sp
+ 624: 1f f0 or \$sp,\$sp
+ 626: 1f f1 and \$sp,\$sp
+ 628: 1f f2 xor \$sp,\$sp
+ 62a: 1f f3 nor \$sp,\$sp
+ 62c: c0 04 00 00 or3 \$0,\$0,0x0
+ 630: c0 05 00 00 and3 \$0,\$0,0x0
+ 634: c0 06 00 00 xor3 \$0,\$0,0x0
+ 638: cf 04 00 00 or3 \$sp,\$0,0x0
+ 63c: cf 05 00 00 and3 \$sp,\$0,0x0
+ 640: cf 06 00 00 xor3 \$sp,\$0,0x0
+ 644: c0 f4 00 00 or3 \$0,\$sp,0x0
+ 648: c0 f5 00 00 and3 \$0,\$sp,0x0
+ 64c: c0 f6 00 00 xor3 \$0,\$sp,0x0
+ 650: cf f4 00 00 or3 \$sp,\$sp,0x0
+ 654: cf f5 00 00 and3 \$sp,\$sp,0x0
+ 658: cf f6 00 00 xor3 \$sp,\$sp,0x0
+ 65c: c0 04 ff ff or3 \$0,\$0,0xffff
+ 660: c0 05 ff ff and3 \$0,\$0,0xffff
+ 664: c0 06 ff ff xor3 \$0,\$0,0xffff
+ 668: cf 04 ff ff or3 \$sp,\$0,0xffff
+ 66c: cf 05 ff ff and3 \$sp,\$0,0xffff
+ 670: cf 06 ff ff xor3 \$sp,\$0,0xffff
+ 674: c0 f4 ff ff or3 \$0,\$sp,0xffff
+ 678: c0 f5 ff ff and3 \$0,\$sp,0xffff
+ 67c: c0 f6 ff ff xor3 \$0,\$sp,0xffff
+ 680: cf f4 ff ff or3 \$sp,\$sp,0xffff
+ 684: cf f5 ff ff and3 \$sp,\$sp,0xffff
+ 688: cf f6 ff ff xor3 \$sp,\$sp,0xffff
+ 68c: c0 04 00 00 or3 \$0,\$0,0x0
+ 68c: R_MEP_LOW16 symbol
+ 690: c0 05 00 00 and3 \$0,\$0,0x0
+ 690: R_MEP_LOW16 symbol
+ 694: c0 06 00 00 xor3 \$0,\$0,0x0
+ 694: R_MEP_LOW16 symbol
+ 698: cf 04 00 00 or3 \$sp,\$0,0x0
+ 698: R_MEP_LOW16 symbol
+ 69c: cf 05 00 00 and3 \$sp,\$0,0x0
+ 69c: R_MEP_LOW16 symbol
+ 6a0: cf 06 00 00 xor3 \$sp,\$0,0x0
+ 6a0: R_MEP_LOW16 symbol
+ 6a4: c0 f4 00 00 or3 \$0,\$sp,0x0
+ 6a4: R_MEP_LOW16 symbol
+ 6a8: c0 f5 00 00 and3 \$0,\$sp,0x0
+ 6a8: R_MEP_LOW16 symbol
+ 6ac: c0 f6 00 00 xor3 \$0,\$sp,0x0
+ 6ac: R_MEP_LOW16 symbol
+ 6b0: cf f4 00 00 or3 \$sp,\$sp,0x0
+ 6b0: R_MEP_LOW16 symbol
+ 6b4: cf f5 00 00 and3 \$sp,\$sp,0x0
+ 6b4: R_MEP_LOW16 symbol
+ 6b8: cf f6 00 00 xor3 \$sp,\$sp,0x0
+ 6b8: R_MEP_LOW16 symbol
+ 6bc: 20 0d sra \$0,\$0
+ 6be: 20 0c srl \$0,\$0
+ 6c0: 20 0e sll \$0,\$0
+ 6c2: 20 0f fsft \$0,\$0
+ 6c4: 2f 0d sra \$sp,\$0
+ 6c6: 2f 0c srl \$sp,\$0
+ 6c8: 2f 0e sll \$sp,\$0
+ 6ca: 2f 0f fsft \$sp,\$0
+ 6cc: 20 fd sra \$0,\$sp
+ 6ce: 20 fc srl \$0,\$sp
+ 6d0: 20 fe sll \$0,\$sp
+ 6d2: 20 ff fsft \$0,\$sp
+ 6d4: 2f fd sra \$sp,\$sp
+ 6d6: 2f fc srl \$sp,\$sp
+ 6d8: 2f fe sll \$sp,\$sp
+ 6da: 2f ff fsft \$sp,\$sp
+ 6dc: 60 03 sra \$0,0x0
+ 6de: 60 02 srl \$0,0x0
+ 6e0: 60 06 sll \$0,0x0
+ 6e2: 6f 03 sra \$sp,0x0
+ 6e4: 6f 02 srl \$sp,0x0
+ 6e6: 6f 06 sll \$sp,0x0
+ 6e8: 60 fb sra \$0,0x1f
+ 6ea: 60 fa srl \$0,0x1f
+ 6ec: 60 fe sll \$0,0x1f
+ 6ee: 6f fb sra \$sp,0x1f
+ 6f0: 6f fa srl \$sp,0x1f
+ 6f2: 6f fe sll \$sp,0x1f
+ 6f4: 60 07 sll3 \$0,\$0,0x0
+ 6f6: 6f 07 sll3 \$0,\$sp,0x0
+ 6f8: 60 ff sll3 \$0,\$0,0x1f
+ 6fa: 6f ff sll3 \$0,\$sp,0x1f
+ 6fc: b8 02 bra 0xfffffefe
+ 6fe: e0 01 04 00 beq \$0,\$0,0xefe
+ 702: b0 00 bra 0x702
+ 702: R_MEP_PCREL12A2 symbol
+ 704: a0 82 beqz \$0,0x686
+ 706: a0 83 bnez \$0,0x688
+ 708: af 82 beqz \$sp,0x68a
+ 70a: af 83 bnez \$sp,0x68c
+ 70c: e0 00 00 40 beqi \$0,0x0,0x78c
+ 710: e0 04 00 40 bnei \$0,0x0,0x790
+ 714: ef 00 00 40 beqi \$sp,0x0,0x794
+ 718: ef 04 00 40 bnei \$sp,0x0,0x798
+ 71c: a0 00 beqz \$0,0x71c
+ 71c: R_MEP_PCREL8A2 symbol
+ 71e: a0 01 bnez \$0,0x71e
+ 71e: R_MEP_PCREL8A2 symbol
+ 720: af 00 beqz \$sp,0x720
+ 720: R_MEP_PCREL8A2 symbol
+ 722: af 01 bnez \$sp,0x722
+ 722: R_MEP_PCREL8A2 symbol
+ 724: e0 00 80 02 beqi \$0,0x0,0xffff0728
+ 728: e0 04 80 02 bnei \$0,0x0,0xffff072c
+ 72c: e0 0c 80 02 blti \$0,0x0,0xffff0730
+ 730: e0 08 80 02 bgei \$0,0x0,0xffff0734
+ 734: ef 00 80 02 beqi \$sp,0x0,0xffff0738
+ 738: ef 04 80 02 bnei \$sp,0x0,0xffff073c
+ 73c: ef 0c 80 02 blti \$sp,0x0,0xffff0740
+ 740: ef 08 80 02 bgei \$sp,0x0,0xffff0744
+ 744: e0 f0 80 02 beqi \$0,0xf,0xffff0748
+ 748: e0 f4 80 02 bnei \$0,0xf,0xffff074c
+ 74c: e0 fc 80 02 blti \$0,0xf,0xffff0750
+ 750: e0 f8 80 02 bgei \$0,0xf,0xffff0754
+ 754: ef f0 80 02 beqi \$sp,0xf,0xffff0758
+ 758: ef f4 80 02 bnei \$sp,0xf,0xffff075c
+ 75c: ef fc 80 02 blti \$sp,0xf,0xffff0760
+ 760: ef f8 80 02 bgei \$sp,0xf,0xffff0764
+ 764: e0 00 3f ff beqi \$0,0x0,0x8762
+ 768: e0 04 3f ff bnei \$0,0x0,0x8766
+ 76c: e0 0c 3f ff blti \$0,0x0,0x876a
+ 770: e0 08 3f ff bgei \$0,0x0,0x876e
+ 774: ef 00 3f ff beqi \$sp,0x0,0x8772
+ 778: ef 04 3f ff bnei \$sp,0x0,0x8776
+ 77c: ef 0c 3f ff blti \$sp,0x0,0x877a
+ 780: ef 08 3f ff bgei \$sp,0x0,0x877e
+ 784: e0 f0 3f ff beqi \$0,0xf,0x8782
+ 788: e0 f4 3f ff bnei \$0,0xf,0x8786
+ 78c: e0 fc 3f ff blti \$0,0xf,0x878a
+ 790: e0 f8 3f ff bgei \$0,0xf,0x878e
+ 794: ef f0 3f ff beqi \$sp,0xf,0x8792
+ 798: ef f4 3f ff bnei \$sp,0xf,0x8796
+ 79c: ef fc 3f ff blti \$sp,0xf,0x879a
+ 7a0: ef f8 3f ff bgei \$sp,0xf,0x879e
+ 7a4: e0 00 00 00 beqi \$0,0x0,0x7a4
+ 7a4: R_MEP_PCREL17A2 symbol
+ 7a8: e0 04 00 00 bnei \$0,0x0,0x7a8
+ 7a8: R_MEP_PCREL17A2 symbol
+ 7ac: e0 0c 00 00 blti \$0,0x0,0x7ac
+ 7ac: R_MEP_PCREL17A2 symbol
+ 7b0: e0 08 00 00 bgei \$0,0x0,0x7b0
+ 7b0: R_MEP_PCREL17A2 symbol
+ 7b4: ef 00 00 00 beqi \$sp,0x0,0x7b4
+ 7b4: R_MEP_PCREL17A2 symbol
+ 7b8: ef 04 00 00 bnei \$sp,0x0,0x7b8
+ 7b8: R_MEP_PCREL17A2 symbol
+ 7bc: ef 0c 00 00 blti \$sp,0x0,0x7bc
+ 7bc: R_MEP_PCREL17A2 symbol
+ 7c0: ef 08 00 00 bgei \$sp,0x0,0x7c0
+ 7c0: R_MEP_PCREL17A2 symbol
+ 7c4: e0 f0 00 00 beqi \$0,0xf,0x7c4
+ 7c4: R_MEP_PCREL17A2 symbol
+ 7c8: e0 f4 00 00 bnei \$0,0xf,0x7c8
+ 7c8: R_MEP_PCREL17A2 symbol
+ 7cc: e0 fc 00 00 blti \$0,0xf,0x7cc
+ 7cc: R_MEP_PCREL17A2 symbol
+ 7d0: e0 f8 00 00 bgei \$0,0xf,0x7d0
+ 7d0: R_MEP_PCREL17A2 symbol
+ 7d4: ef f0 00 00 beqi \$sp,0xf,0x7d4
+ 7d4: R_MEP_PCREL17A2 symbol
+ 7d8: ef f4 00 00 bnei \$sp,0xf,0x7d8
+ 7d8: R_MEP_PCREL17A2 symbol
+ 7dc: ef fc 00 00 blti \$sp,0xf,0x7dc
+ 7dc: R_MEP_PCREL17A2 symbol
+ 7e0: ef f8 00 00 bgei \$sp,0xf,0x7e0
+ 7e0: R_MEP_PCREL17A2 symbol
+ 7e4: e0 01 80 02 beq \$0,\$0,0xffff07e8
+ 7e8: e0 05 80 02 bne \$0,\$0,0xffff07ec
+ 7ec: ef 01 80 02 beq \$sp,\$0,0xffff07f0
+ 7f0: ef 05 80 02 bne \$sp,\$0,0xffff07f4
+ 7f4: e0 f1 80 02 beq \$0,\$sp,0xffff07f8
+ 7f8: e0 f5 80 02 bne \$0,\$sp,0xffff07fc
+ 7fc: ef f1 80 02 beq \$sp,\$sp,0xffff0800
+ 800: ef f5 80 02 bne \$sp,\$sp,0xffff0804
+ 804: e0 01 3f ff beq \$0,\$0,0x8802
+ 808: e0 05 3f ff bne \$0,\$0,0x8806
+ 80c: ef 01 3f ff beq \$sp,\$0,0x880a
+ 810: ef 05 3f ff bne \$sp,\$0,0x880e
+ 814: e0 f1 3f ff beq \$0,\$sp,0x8812
+ 818: e0 f5 3f ff bne \$0,\$sp,0x8816
+ 81c: ef f1 3f ff beq \$sp,\$sp,0x881a
+ 820: ef f5 3f ff bne \$sp,\$sp,0x881e
+ 824: e0 01 00 00 beq \$0,\$0,0x824
+ 824: R_MEP_PCREL17A2 symbol
+ 828: e0 05 00 00 bne \$0,\$0,0x828
+ 828: R_MEP_PCREL17A2 symbol
+ 82c: ef 01 00 00 beq \$sp,\$0,0x82c
+ 82c: R_MEP_PCREL17A2 symbol
+ 830: ef 05 00 00 bne \$sp,\$0,0x830
+ 830: R_MEP_PCREL17A2 symbol
+ 834: e0 f1 00 00 beq \$0,\$sp,0x834
+ 834: R_MEP_PCREL17A2 symbol
+ 838: e0 f5 00 00 bne \$0,\$sp,0x838
+ 838: R_MEP_PCREL17A2 symbol
+ 83c: ef f1 00 00 beq \$sp,\$sp,0x83c
+ 83c: R_MEP_PCREL17A2 symbol
+ 840: ef f5 00 00 bne \$sp,\$sp,0x840
+ 840: R_MEP_PCREL17A2 symbol
+ 844: d8 29 80 00 bsr 0xff800848
+ 848: b8 03 bsr 0x4a
+ 84a: d8 09 00 08 bsr 0x104a
+ 84e: d8 19 80 00 bsr 0xff800850
+ 852: d8 09 00 00 bsr 0x852
+ 852: R_MEP_PCREL24A2 symbol
+ 856: 10 0e jmp \$0
+ 858: 10 fe jmp \$sp
+ 85a: d8 08 00 00 jmp 0x0
+ 85e: df f8 ff ff jmp 0xfffffe
+ 862: d8 08 00 00 jmp 0x0
+ 862: R_MEP_PCABS24A2 symbol
+ 866: 10 0f jsr \$0
+ 868: 10 ff jsr \$sp
+ 86a: 70 02 ret
+ 86c: e0 09 80 02 repeat \$0,0xffff0870
+ 870: ef 09 80 02 repeat \$sp,0xffff0874
+ 874: e0 09 3f ff repeat \$0,0x8872
+ 878: ef 09 3f ff repeat \$sp,0x8876
+ 87c: e0 09 00 00 repeat \$0,0x87c
+ 87c: R_MEP_PCREL17A2 symbol
+ 880: ef 09 00 00 repeat \$sp,0x880
+ 880: R_MEP_PCREL17A2 symbol
+ 884: e0 19 80 02 erepeat 0xffff0888
+ 888: e0 19 3f ff erepeat 0x8886
+ 88c: e0 19 00 00 erepeat 0x88c
+ 88c: R_MEP_PCREL17A2 symbol
+ 890: 70 08 stc \$0,\$pc
+ 892: 70 0a ldc \$0,\$pc
+ 894: 7f 08 stc \$sp,\$pc
+ 896: 7f 0a ldc \$sp,\$pc
+ 898: 70 18 stc \$0,\$lp
+ 89a: 70 1a ldc \$0,\$lp
+ 89c: 7f 18 stc \$sp,\$lp
+ 89e: 7f 1a ldc \$sp,\$lp
+ 8a0: 70 28 stc \$0,\$sar
+ 8a2: 70 2a ldc \$0,\$sar
+ 8a4: 7f 28 stc \$sp,\$sar
+ 8a6: 7f 2a ldc \$sp,\$sar
+ 8a8: 70 48 stc \$0,\$rpb
+ 8aa: 70 4a ldc \$0,\$rpb
+ 8ac: 7f 48 stc \$sp,\$rpb
+ 8ae: 7f 4a ldc \$sp,\$rpb
+ 8b0: 70 58 stc \$0,\$rpe
+ 8b2: 70 5a ldc \$0,\$rpe
+ 8b4: 7f 58 stc \$sp,\$rpe
+ 8b6: 7f 5a ldc \$sp,\$rpe
+ 8b8: 70 68 stc \$0,\$rpc
+ 8ba: 70 6a ldc \$0,\$rpc
+ 8bc: 7f 68 stc \$sp,\$rpc
+ 8be: 7f 6a ldc \$sp,\$rpc
+ 8c0: 70 78 stc \$0,\$hi
+ 8c2: 70 7a ldc \$0,\$hi
+ 8c4: 7f 78 stc \$sp,\$hi
+ 8c6: 7f 7a ldc \$sp,\$hi
+ 8c8: 70 88 stc \$0,\$lo
+ 8ca: 70 8a ldc \$0,\$lo
+ 8cc: 7f 88 stc \$sp,\$lo
+ 8ce: 7f 8a ldc \$sp,\$lo
+ 8d0: 70 c8 stc \$0,\$mb0
+ 8d2: 70 ca ldc \$0,\$mb0
+ 8d4: 7f c8 stc \$sp,\$mb0
+ 8d6: 7f ca ldc \$sp,\$mb0
+ 8d8: 70 d8 stc \$0,\$me0
+ 8da: 70 da ldc \$0,\$me0
+ 8dc: 7f d8 stc \$sp,\$me0
+ 8de: 7f da ldc \$sp,\$me0
+ 8e0: 70 e8 stc \$0,\$mb1
+ 8e2: 70 ea ldc \$0,\$mb1
+ 8e4: 7f e8 stc \$sp,\$mb1
+ 8e6: 7f ea ldc \$sp,\$mb1
+ 8e8: 70 f8 stc \$0,\$me1
+ 8ea: 70 fa ldc \$0,\$me1
+ 8ec: 7f f8 stc \$sp,\$me1
+ 8ee: 7f fa ldc \$sp,\$me1
+ 8f0: 70 09 stc \$0,\$psw
+ 8f2: 70 0b ldc \$0,\$psw
+ 8f4: 7f 09 stc \$sp,\$psw
+ 8f6: 7f 0b ldc \$sp,\$psw
+ 8f8: 70 19 stc \$0,\$id
+ 8fa: 70 1b ldc \$0,\$id
+ 8fc: 7f 19 stc \$sp,\$id
+ 8fe: 7f 1b ldc \$sp,\$id
+ 900: 70 29 stc \$0,\$tmp
+ 902: 70 2b ldc \$0,\$tmp
+ 904: 7f 29 stc \$sp,\$tmp
+ 906: 7f 2b ldc \$sp,\$tmp
+ 908: 70 39 stc \$0,\$epc
+ 90a: 70 3b ldc \$0,\$epc
+ 90c: 7f 39 stc \$sp,\$epc
+ 90e: 7f 3b ldc \$sp,\$epc
+ 910: 70 49 stc \$0,\$exc
+ 912: 70 4b ldc \$0,\$exc
+ 914: 7f 49 stc \$sp,\$exc
+ 916: 7f 4b ldc \$sp,\$exc
+ 918: 70 59 stc \$0,\$cfg
+ 91a: 70 5b ldc \$0,\$cfg
+ 91c: 7f 59 stc \$sp,\$cfg
+ 91e: 7f 5b ldc \$sp,\$cfg
+ 920: 70 79 stc \$0,\$npc
+ 922: 70 7b ldc \$0,\$npc
+ 924: 7f 79 stc \$sp,\$npc
+ 926: 7f 7b ldc \$sp,\$npc
+ 928: 70 89 stc \$0,\$dbg
+ 92a: 70 8b ldc \$0,\$dbg
+ 92c: 7f 89 stc \$sp,\$dbg
+ 92e: 7f 8b ldc \$sp,\$dbg
+ 930: 70 99 stc \$0,\$depc
+ 932: 70 9b ldc \$0,\$depc
+ 934: 7f 99 stc \$sp,\$depc
+ 936: 7f 9b ldc \$sp,\$depc
+ 938: 70 a9 stc \$0,\$opt
+ 93a: 70 ab ldc \$0,\$opt
+ 93c: 7f a9 stc \$sp,\$opt
+ 93e: 7f ab ldc \$sp,\$opt
+ 940: 70 b9 stc \$0,\$rcfg
+ 942: 70 bb ldc \$0,\$rcfg
+ 944: 7f b9 stc \$sp,\$rcfg
+ 946: 7f bb ldc \$sp,\$rcfg
+ 948: 70 c9 stc \$0,\$ccfg
+ 94a: 70 cb ldc \$0,\$ccfg
+ 94c: 7f c9 stc \$sp,\$ccfg
+ 94e: 7f cb ldc \$sp,\$ccfg
+ 950: 70 00 di
+ 952: 70 10 ei
+ 954: 70 12 reti
+ 956: 70 22 halt
+ 958: 70 32 break
+ 95a: 70 11 syncm
+ 95c: 70 06 swi 0x0
+ 95e: 70 36 swi 0x3
+ 960: f0 04 00 00 stcb \$0,0x0
+ 964: f0 14 00 00 ldcb \$0,0x0
+ 968: ff 04 00 00 stcb \$sp,0x0
+ 96c: ff 14 00 00 ldcb \$sp,0x0
+ 970: f0 04 ff ff stcb \$0,0xffff
+ 974: f0 14 ff ff ldcb \$0,0xffff
+ 978: ff 04 ff ff stcb \$sp,0xffff
+ 97c: ff 14 ff ff ldcb \$sp,0xffff
+ 980: f0 04 00 00 stcb \$0,0x0
+ 982: R_MEP_16 symbol
+ 984: f0 14 00 00 ldcb \$0,0x0
+ 986: R_MEP_16 symbol
+ 988: ff 04 00 00 stcb \$sp,0x0
+ 98a: R_MEP_16 symbol
+ 98c: ff 14 00 00 ldcb \$sp,0x0
+ 98e: R_MEP_16 symbol
+ 990: 20 00 bsetm \(\$0\),0x0
+ 992: 20 01 bclrm \(\$0\),0x0
+ 994: 20 02 bnotm \(\$0\),0x0
+ 996: 20 f0 bsetm \(\$sp\),0x0
+ 998: 20 f1 bclrm \(\$sp\),0x0
+ 99a: 20 f2 bnotm \(\$sp\),0x0
+ 99c: 27 00 bsetm \(\$0\),0x7
+ 99e: 27 01 bclrm \(\$0\),0x7
+ 9a0: 27 02 bnotm \(\$0\),0x7
+ 9a2: 27 f0 bsetm \(\$sp\),0x7
+ 9a4: 27 f1 bclrm \(\$sp\),0x7
+ 9a6: 27 f2 bnotm \(\$sp\),0x7
+ 9a8: 20 03 btstm \$0,\(\$0\),0x0
+ 9aa: 20 f3 btstm \$0,\(\$sp\),0x0
+ 9ac: 27 03 btstm \$0,\(\$0\),0x7
+ 9ae: 27 f3 btstm \$0,\(\$sp\),0x7
+ 9b0: 20 04 tas \$0,\(\$0\)
+ 9b2: 2f 04 tas \$sp,\(\$0\)
+ 9b4: 20 f4 tas \$0,\(\$sp\)
+ 9b6: 2f f4 tas \$sp,\(\$sp\)
+ 9b8: 70 04 cache 0x0,\(\$0\)
+ 9ba: 73 04 cache 0x3,\(\$0\)
+ 9bc: 70 f4 cache 0x0,\(\$sp\)
+ 9be: 73 f4 cache 0x3,\(\$sp\)
+ 9c0: 10 04 mul \$0,\$0
+ 9c2: f0 01 30 04 madd \$0,\$0
+ 9c6: 10 06 mulr \$0,\$0
+ 9c8: f0 01 30 06 maddr \$0,\$0
+ 9cc: 10 05 mulu \$0,\$0
+ 9ce: f0 01 30 05 maddu \$0,\$0
+ 9d2: 10 07 mulru \$0,\$0
+ 9d4: f0 01 30 07 maddru \$0,\$0
+ 9d8: 1f 04 mul \$sp,\$0
+ 9da: ff 01 30 04 madd \$sp,\$0
+ 9de: 1f 06 mulr \$sp,\$0
+ 9e0: ff 01 30 06 maddr \$sp,\$0
+ 9e4: 1f 05 mulu \$sp,\$0
+ 9e6: ff 01 30 05 maddu \$sp,\$0
+ 9ea: 1f 07 mulru \$sp,\$0
+ 9ec: ff 01 30 07 maddru \$sp,\$0
+ 9f0: 10 f4 mul \$0,\$sp
+ 9f2: f0 f1 30 04 madd \$0,\$sp
+ 9f6: 10 f6 mulr \$0,\$sp
+ 9f8: f0 f1 30 06 maddr \$0,\$sp
+ 9fc: 10 f5 mulu \$0,\$sp
+ 9fe: f0 f1 30 05 maddu \$0,\$sp
+ a02: 10 f7 mulru \$0,\$sp
+ a04: f0 f1 30 07 maddru \$0,\$sp
+ a08: 1f f4 mul \$sp,\$sp
+ a0a: ff f1 30 04 madd \$sp,\$sp
+ a0e: 1f f6 mulr \$sp,\$sp
+ a10: ff f1 30 06 maddr \$sp,\$sp
+ a14: 1f f5 mulu \$sp,\$sp
+ a16: ff f1 30 05 maddu \$sp,\$sp
+ a1a: 1f f7 mulru \$sp,\$sp
+ a1c: ff f1 30 07 maddru \$sp,\$sp
+ a20: 10 08 div \$0,\$0
+ a22: 10 09 divu \$0,\$0
+ a24: 1f 08 div \$sp,\$0
+ a26: 1f 09 divu \$sp,\$0
+ a28: 10 f8 div \$0,\$sp
+ a2a: 10 f9 divu \$0,\$sp
+ a2c: 1f f8 div \$sp,\$sp
+ a2e: 1f f9 divu \$sp,\$sp
+ a30: 70 13 dret
+ a32: 70 33 dbreak
+ a34: f0 01 00 00 ldz \$0,\$0
+ a38: f0 01 00 03 abs \$0,\$0
+ a3c: f0 01 00 02 ave \$0,\$0
+ a40: ff 01 00 00 ldz \$sp,\$0
+ a44: ff 01 00 03 abs \$sp,\$0
+ a48: ff 01 00 02 ave \$sp,\$0
+ a4c: f0 f1 00 00 ldz \$0,\$sp
+ a50: f0 f1 00 03 abs \$0,\$sp
+ a54: f0 f1 00 02 ave \$0,\$sp
+ a58: ff f1 00 00 ldz \$sp,\$sp
+ a5c: ff f1 00 03 abs \$sp,\$sp
+ a60: ff f1 00 02 ave \$sp,\$sp
+ a64: f0 01 00 04 min \$0,\$0
+ a68: f0 01 00 05 max \$0,\$0
+ a6c: f0 01 00 06 minu \$0,\$0
+ a70: f0 01 00 07 maxu \$0,\$0
+ a74: ff 01 00 04 min \$sp,\$0
+ a78: ff 01 00 05 max \$sp,\$0
+ a7c: ff 01 00 06 minu \$sp,\$0
+ a80: ff 01 00 07 maxu \$sp,\$0
+ a84: f0 f1 00 04 min \$0,\$sp
+ a88: f0 f1 00 05 max \$0,\$sp
+ a8c: f0 f1 00 06 minu \$0,\$sp
+ a90: f0 f1 00 07 maxu \$0,\$sp
+ a94: ff f1 00 04 min \$sp,\$sp
+ a98: ff f1 00 05 max \$sp,\$sp
+ a9c: ff f1 00 06 minu \$sp,\$sp
+ aa0: ff f1 00 07 maxu \$sp,\$sp
+ aa4: f0 01 10 00 clip \$0,0x0
+ aa8: f0 01 10 01 clipu \$0,0x0
+ aac: ff 01 10 00 clip \$sp,0x0
+ ab0: ff 01 10 01 clipu \$sp,0x0
+ ab4: f0 01 10 f8 clip \$0,0x1f
+ ab8: f0 01 10 f9 clipu \$0,0x1f
+ abc: ff 01 10 f8 clip \$sp,0x1f
+ ac0: ff 01 10 f9 clipu \$sp,0x1f
+ ac4: f0 01 00 08 sadd \$0,\$0
+ ac8: f0 01 00 0a ssub \$0,\$0
+ acc: f0 01 00 09 saddu \$0,\$0
+ ad0: f0 01 00 0b ssubu \$0,\$0
+ ad4: ff 01 00 08 sadd \$sp,\$0
+ ad8: ff 01 00 0a ssub \$sp,\$0
+ adc: ff 01 00 09 saddu \$sp,\$0
+ ae0: ff 01 00 0b ssubu \$sp,\$0
+ ae4: f0 f1 00 08 sadd \$0,\$sp
+ ae8: f0 f1 00 0a ssub \$0,\$sp
+ aec: f0 f1 00 09 saddu \$0,\$sp
+ af0: f0 f1 00 0b ssubu \$0,\$sp
+ af4: ff f1 00 08 sadd \$sp,\$sp
+ af8: ff f1 00 0a ssub \$sp,\$sp
+ afc: ff f1 00 09 saddu \$sp,\$sp
+ b00: ff f1 00 0b ssubu \$sp,\$sp
+ b04: 30 08 swcp \$c0,\(\$0\)
+ b06: 30 09 lwcp \$c0,\(\$0\)
+ b08: 30 0a smcp \$c0,\(\$0\)
+ b0a: 30 0b lmcp \$c0,\(\$0\)
+ b0c: 3f 08 swcp \$c15,\(\$0\)
+ b0e: 3f 09 lwcp \$c15,\(\$0\)
+ b10: 3f 0a smcp \$c15,\(\$0\)
+ b12: 3f 0b lmcp \$c15,\(\$0\)
+ b14: 30 f8 swcp \$c0,\(\$sp\)
+ b16: 30 f9 lwcp \$c0,\(\$sp\)
+ b18: 30 fa smcp \$c0,\(\$sp\)
+ b1a: 30 fb lmcp \$c0,\(\$sp\)
+ b1c: 3f f8 swcp \$c15,\(\$sp\)
+ b1e: 3f f9 lwcp \$c15,\(\$sp\)
+ b20: 3f fa smcp \$c15,\(\$sp\)
+ b22: 3f fb lmcp \$c15,\(\$sp\)
+ b24: 30 00 swcpi \$c0,\(\$0\+\)
+ b26: 30 01 lwcpi \$c0,\(\$0\+\)
+ b28: 30 02 smcpi \$c0,\(\$0\+\)
+ b2a: 30 03 lmcpi \$c0,\(\$0\+\)
+ b2c: 3f 00 swcpi \$c15,\(\$0\+\)
+ b2e: 3f 01 lwcpi \$c15,\(\$0\+\)
+ b30: 3f 02 smcpi \$c15,\(\$0\+\)
+ b32: 3f 03 lmcpi \$c15,\(\$0\+\)
+ b34: 30 f0 swcpi \$c0,\(\$sp\+\)
+ b36: 30 f1 lwcpi \$c0,\(\$sp\+\)
+ b38: 30 f2 smcpi \$c0,\(\$sp\+\)
+ b3a: 30 f3 lmcpi \$c0,\(\$sp\+\)
+ b3c: 3f f0 swcpi \$c15,\(\$sp\+\)
+ b3e: 3f f1 lwcpi \$c15,\(\$sp\+\)
+ b40: 3f f2 smcpi \$c15,\(\$sp\+\)
+ b42: 3f f3 lmcpi \$c15,\(\$sp\+\)
+ b44: f0 05 00 80 sbcpa \$c0,\(\$0\+\),-128
+ b48: f0 05 40 80 lbcpa \$c0,\(\$0\+\),-128
+ b4c: f0 05 08 80 sbcpm0 \$c0,\(\$0\+\),-128
+ b50: f0 05 48 80 lbcpm0 \$c0,\(\$0\+\),-128
+ b54: f0 05 0c 80 sbcpm1 \$c0,\(\$0\+\),-128
+ b58: f0 05 4c 80 lbcpm1 \$c0,\(\$0\+\),-128
+ b5c: ff 05 00 80 sbcpa \$c15,\(\$0\+\),-128
+ b60: ff 05 40 80 lbcpa \$c15,\(\$0\+\),-128
+ b64: ff 05 08 80 sbcpm0 \$c15,\(\$0\+\),-128
+ b68: ff 05 48 80 lbcpm0 \$c15,\(\$0\+\),-128
+ b6c: ff 05 0c 80 sbcpm1 \$c15,\(\$0\+\),-128
+ b70: ff 05 4c 80 lbcpm1 \$c15,\(\$0\+\),-128
+ b74: f0 f5 00 80 sbcpa \$c0,\(\$sp\+\),-128
+ b78: f0 f5 40 80 lbcpa \$c0,\(\$sp\+\),-128
+ b7c: f0 f5 08 80 sbcpm0 \$c0,\(\$sp\+\),-128
+ b80: f0 f5 48 80 lbcpm0 \$c0,\(\$sp\+\),-128
+ b84: f0 f5 0c 80 sbcpm1 \$c0,\(\$sp\+\),-128
+ b88: f0 f5 4c 80 lbcpm1 \$c0,\(\$sp\+\),-128
+ b8c: ff f5 00 80 sbcpa \$c15,\(\$sp\+\),-128
+ b90: ff f5 40 80 lbcpa \$c15,\(\$sp\+\),-128
+ b94: ff f5 08 80 sbcpm0 \$c15,\(\$sp\+\),-128
+ b98: ff f5 48 80 lbcpm0 \$c15,\(\$sp\+\),-128
+ b9c: ff f5 0c 80 sbcpm1 \$c15,\(\$sp\+\),-128
+ ba0: ff f5 4c 80 lbcpm1 \$c15,\(\$sp\+\),-128
+ ba4: f0 05 00 7f sbcpa \$c0,\(\$0\+\),127
+ ba8: f0 05 40 7f lbcpa \$c0,\(\$0\+\),127
+ bac: f0 05 08 7f sbcpm0 \$c0,\(\$0\+\),127
+ bb0: f0 05 48 7f lbcpm0 \$c0,\(\$0\+\),127
+ bb4: f0 05 0c 7f sbcpm1 \$c0,\(\$0\+\),127
+ bb8: f0 05 4c 7f lbcpm1 \$c0,\(\$0\+\),127
+ bbc: ff 05 00 7f sbcpa \$c15,\(\$0\+\),127
+ bc0: ff 05 40 7f lbcpa \$c15,\(\$0\+\),127
+ bc4: ff 05 08 7f sbcpm0 \$c15,\(\$0\+\),127
+ bc8: ff 05 48 7f lbcpm0 \$c15,\(\$0\+\),127
+ bcc: ff 05 0c 7f sbcpm1 \$c15,\(\$0\+\),127
+ bd0: ff 05 4c 7f lbcpm1 \$c15,\(\$0\+\),127
+ bd4: f0 f5 00 7f sbcpa \$c0,\(\$sp\+\),127
+ bd8: f0 f5 40 7f lbcpa \$c0,\(\$sp\+\),127
+ bdc: f0 f5 08 7f sbcpm0 \$c0,\(\$sp\+\),127
+ be0: f0 f5 48 7f lbcpm0 \$c0,\(\$sp\+\),127
+ be4: f0 f5 0c 7f sbcpm1 \$c0,\(\$sp\+\),127
+ be8: f0 f5 4c 7f lbcpm1 \$c0,\(\$sp\+\),127
+ bec: ff f5 00 7f sbcpa \$c15,\(\$sp\+\),127
+ bf0: ff f5 40 7f lbcpa \$c15,\(\$sp\+\),127
+ bf4: ff f5 08 7f sbcpm0 \$c15,\(\$sp\+\),127
+ bf8: ff f5 48 7f lbcpm0 \$c15,\(\$sp\+\),127
+ bfc: ff f5 0c 7f sbcpm1 \$c15,\(\$sp\+\),127
+ c00: ff f5 4c 7f lbcpm1 \$c15,\(\$sp\+\),127
+ c04: f0 05 10 80 shcpa \$c0,\(\$0\+\),-128
+ c08: f0 05 50 80 lhcpa \$c0,\(\$0\+\),-128
+ c0c: f0 05 18 80 shcpm0 \$c0,\(\$0\+\),-128
+ c10: f0 05 58 80 lhcpm0 \$c0,\(\$0\+\),-128
+ c14: f0 05 1c 80 shcpm1 \$c0,\(\$0\+\),-128
+ c18: f0 05 5c 80 lhcpm1 \$c0,\(\$0\+\),-128
+ c1c: ff 05 10 80 shcpa \$c15,\(\$0\+\),-128
+ c20: ff 05 50 80 lhcpa \$c15,\(\$0\+\),-128
+ c24: ff 05 18 80 shcpm0 \$c15,\(\$0\+\),-128
+ c28: ff 05 58 80 lhcpm0 \$c15,\(\$0\+\),-128
+ c2c: ff 05 1c 80 shcpm1 \$c15,\(\$0\+\),-128
+ c30: ff 05 5c 80 lhcpm1 \$c15,\(\$0\+\),-128
+ c34: f0 f5 10 80 shcpa \$c0,\(\$sp\+\),-128
+ c38: f0 f5 50 80 lhcpa \$c0,\(\$sp\+\),-128
+ c3c: f0 f5 18 80 shcpm0 \$c0,\(\$sp\+\),-128
+ c40: f0 f5 58 80 lhcpm0 \$c0,\(\$sp\+\),-128
+ c44: f0 f5 1c 80 shcpm1 \$c0,\(\$sp\+\),-128
+ c48: f0 f5 5c 80 lhcpm1 \$c0,\(\$sp\+\),-128
+ c4c: ff f5 10 80 shcpa \$c15,\(\$sp\+\),-128
+ c50: ff f5 50 80 lhcpa \$c15,\(\$sp\+\),-128
+ c54: ff f5 18 80 shcpm0 \$c15,\(\$sp\+\),-128
+ c58: ff f5 58 80 lhcpm0 \$c15,\(\$sp\+\),-128
+ c5c: ff f5 1c 80 shcpm1 \$c15,\(\$sp\+\),-128
+ c60: ff f5 5c 80 lhcpm1 \$c15,\(\$sp\+\),-128
+ c64: f0 05 10 7e shcpa \$c0,\(\$0\+\),126
+ c68: f0 05 50 7e lhcpa \$c0,\(\$0\+\),126
+ c6c: f0 05 18 7e shcpm0 \$c0,\(\$0\+\),126
+ c70: f0 05 58 7e lhcpm0 \$c0,\(\$0\+\),126
+ c74: f0 05 1c 7e shcpm1 \$c0,\(\$0\+\),126
+ c78: f0 05 5c 7e lhcpm1 \$c0,\(\$0\+\),126
+ c7c: ff 05 10 7e shcpa \$c15,\(\$0\+\),126
+ c80: ff 05 50 7e lhcpa \$c15,\(\$0\+\),126
+ c84: ff 05 18 7e shcpm0 \$c15,\(\$0\+\),126
+ c88: ff 05 58 7e lhcpm0 \$c15,\(\$0\+\),126
+ c8c: ff 05 1c 7e shcpm1 \$c15,\(\$0\+\),126
+ c90: ff 05 5c 7e lhcpm1 \$c15,\(\$0\+\),126
+ c94: f0 f5 10 7e shcpa \$c0,\(\$sp\+\),126
+ c98: f0 f5 50 7e lhcpa \$c0,\(\$sp\+\),126
+ c9c: f0 f5 18 7e shcpm0 \$c0,\(\$sp\+\),126
+ ca0: f0 f5 58 7e lhcpm0 \$c0,\(\$sp\+\),126
+ ca4: f0 f5 1c 7e shcpm1 \$c0,\(\$sp\+\),126
+ ca8: f0 f5 5c 7e lhcpm1 \$c0,\(\$sp\+\),126
+ cac: ff f5 10 7e shcpa \$c15,\(\$sp\+\),126
+ cb0: ff f5 50 7e lhcpa \$c15,\(\$sp\+\),126
+ cb4: ff f5 18 7e shcpm0 \$c15,\(\$sp\+\),126
+ cb8: ff f5 58 7e lhcpm0 \$c15,\(\$sp\+\),126
+ cbc: ff f5 1c 7e shcpm1 \$c15,\(\$sp\+\),126
+ cc0: ff f5 5c 7e lhcpm1 \$c15,\(\$sp\+\),126
+ cc4: f0 05 20 80 swcpa \$c0,\(\$0\+\),-128
+ cc8: f0 05 60 80 lwcpa \$c0,\(\$0\+\),-128
+ ccc: f0 05 28 80 swcpm0 \$c0,\(\$0\+\),-128
+ cd0: f0 05 68 80 lwcpm0 \$c0,\(\$0\+\),-128
+ cd4: f0 05 2c 80 swcpm1 \$c0,\(\$0\+\),-128
+ cd8: f0 05 6c 80 lwcpm1 \$c0,\(\$0\+\),-128
+ cdc: ff 05 20 80 swcpa \$c15,\(\$0\+\),-128
+ ce0: ff 05 60 80 lwcpa \$c15,\(\$0\+\),-128
+ ce4: ff 05 28 80 swcpm0 \$c15,\(\$0\+\),-128
+ ce8: ff 05 68 80 lwcpm0 \$c15,\(\$0\+\),-128
+ cec: ff 05 2c 80 swcpm1 \$c15,\(\$0\+\),-128
+ cf0: ff 05 6c 80 lwcpm1 \$c15,\(\$0\+\),-128
+ cf4: f0 f5 20 80 swcpa \$c0,\(\$sp\+\),-128
+ cf8: f0 f5 60 80 lwcpa \$c0,\(\$sp\+\),-128
+ cfc: f0 f5 28 80 swcpm0 \$c0,\(\$sp\+\),-128
+ d00: f0 f5 68 80 lwcpm0 \$c0,\(\$sp\+\),-128
+ d04: f0 f5 2c 80 swcpm1 \$c0,\(\$sp\+\),-128
+ d08: f0 f5 6c 80 lwcpm1 \$c0,\(\$sp\+\),-128
+ d0c: ff f5 20 80 swcpa \$c15,\(\$sp\+\),-128
+ d10: ff f5 60 80 lwcpa \$c15,\(\$sp\+\),-128
+ d14: ff f5 28 80 swcpm0 \$c15,\(\$sp\+\),-128
+ d18: ff f5 68 80 lwcpm0 \$c15,\(\$sp\+\),-128
+ d1c: ff f5 2c 80 swcpm1 \$c15,\(\$sp\+\),-128
+ d20: ff f5 6c 80 lwcpm1 \$c15,\(\$sp\+\),-128
+ d24: f0 05 20 7c swcpa \$c0,\(\$0\+\),124
+ d28: f0 05 60 7c lwcpa \$c0,\(\$0\+\),124
+ d2c: f0 05 28 7c swcpm0 \$c0,\(\$0\+\),124
+ d30: f0 05 68 7c lwcpm0 \$c0,\(\$0\+\),124
+ d34: f0 05 2c 7c swcpm1 \$c0,\(\$0\+\),124
+ d38: f0 05 6c 7c lwcpm1 \$c0,\(\$0\+\),124
+ d3c: ff 05 20 7c swcpa \$c15,\(\$0\+\),124
+ d40: ff 05 60 7c lwcpa \$c15,\(\$0\+\),124
+ d44: ff 05 28 7c swcpm0 \$c15,\(\$0\+\),124
+ d48: ff 05 68 7c lwcpm0 \$c15,\(\$0\+\),124
+ d4c: ff 05 2c 7c swcpm1 \$c15,\(\$0\+\),124
+ d50: ff 05 6c 7c lwcpm1 \$c15,\(\$0\+\),124
+ d54: f0 f5 20 7c swcpa \$c0,\(\$sp\+\),124
+ d58: f0 f5 60 7c lwcpa \$c0,\(\$sp\+\),124
+ d5c: f0 f5 28 7c swcpm0 \$c0,\(\$sp\+\),124
+ d60: f0 f5 68 7c lwcpm0 \$c0,\(\$sp\+\),124
+ d64: f0 f5 2c 7c swcpm1 \$c0,\(\$sp\+\),124
+ d68: f0 f5 6c 7c lwcpm1 \$c0,\(\$sp\+\),124
+ d6c: ff f5 20 7c swcpa \$c15,\(\$sp\+\),124
+ d70: ff f5 60 7c lwcpa \$c15,\(\$sp\+\),124
+ d74: ff f5 28 7c swcpm0 \$c15,\(\$sp\+\),124
+ d78: ff f5 68 7c lwcpm0 \$c15,\(\$sp\+\),124
+ d7c: ff f5 2c 7c swcpm1 \$c15,\(\$sp\+\),124
+ d80: ff f5 6c 7c lwcpm1 \$c15,\(\$sp\+\),124
+ d84: f0 05 30 80 smcpa \$c0,\(\$0\+\),-128
+ d88: f0 05 70 80 lmcpa \$c0,\(\$0\+\),-128
+ d8c: f0 05 38 80 smcpm0 \$c0,\(\$0\+\),-128
+ d90: f0 05 78 80 lmcpm0 \$c0,\(\$0\+\),-128
+ d94: f0 05 3c 80 smcpm1 \$c0,\(\$0\+\),-128
+ d98: f0 05 7c 80 lmcpm1 \$c0,\(\$0\+\),-128
+ d9c: ff 05 30 80 smcpa \$c15,\(\$0\+\),-128
+ da0: ff 05 70 80 lmcpa \$c15,\(\$0\+\),-128
+ da4: ff 05 38 80 smcpm0 \$c15,\(\$0\+\),-128
+ da8: ff 05 78 80 lmcpm0 \$c15,\(\$0\+\),-128
+ dac: ff 05 3c 80 smcpm1 \$c15,\(\$0\+\),-128
+ db0: ff 05 7c 80 lmcpm1 \$c15,\(\$0\+\),-128
+ db4: f0 f5 30 80 smcpa \$c0,\(\$sp\+\),-128
+ db8: f0 f5 70 80 lmcpa \$c0,\(\$sp\+\),-128
+ dbc: f0 f5 38 80 smcpm0 \$c0,\(\$sp\+\),-128
+ dc0: f0 f5 78 80 lmcpm0 \$c0,\(\$sp\+\),-128
+ dc4: f0 f5 3c 80 smcpm1 \$c0,\(\$sp\+\),-128
+ dc8: f0 f5 7c 80 lmcpm1 \$c0,\(\$sp\+\),-128
+ dcc: ff f5 30 80 smcpa \$c15,\(\$sp\+\),-128
+ dd0: ff f5 70 80 lmcpa \$c15,\(\$sp\+\),-128
+ dd4: ff f5 38 80 smcpm0 \$c15,\(\$sp\+\),-128
+ dd8: ff f5 78 80 lmcpm0 \$c15,\(\$sp\+\),-128
+ ddc: ff f5 3c 80 smcpm1 \$c15,\(\$sp\+\),-128
+ de0: ff f5 7c 80 lmcpm1 \$c15,\(\$sp\+\),-128
+ de4: f0 05 30 78 smcpa \$c0,\(\$0\+\),120
+ de8: f0 05 70 78 lmcpa \$c0,\(\$0\+\),120
+ dec: f0 05 38 78 smcpm0 \$c0,\(\$0\+\),120
+ df0: f0 05 78 78 lmcpm0 \$c0,\(\$0\+\),120
+ df4: f0 05 3c 78 smcpm1 \$c0,\(\$0\+\),120
+ df8: f0 05 7c 78 lmcpm1 \$c0,\(\$0\+\),120
+ dfc: ff 05 30 78 smcpa \$c15,\(\$0\+\),120
+ e00: ff 05 70 78 lmcpa \$c15,\(\$0\+\),120
+ e04: ff 05 38 78 smcpm0 \$c15,\(\$0\+\),120
+ e08: ff 05 78 78 lmcpm0 \$c15,\(\$0\+\),120
+ e0c: ff 05 3c 78 smcpm1 \$c15,\(\$0\+\),120
+ e10: ff 05 7c 78 lmcpm1 \$c15,\(\$0\+\),120
+ e14: f0 f5 30 78 smcpa \$c0,\(\$sp\+\),120
+ e18: f0 f5 70 78 lmcpa \$c0,\(\$sp\+\),120
+ e1c: f0 f5 38 78 smcpm0 \$c0,\(\$sp\+\),120
+ e20: f0 f5 78 78 lmcpm0 \$c0,\(\$sp\+\),120
+ e24: f0 f5 3c 78 smcpm1 \$c0,\(\$sp\+\),120
+ e28: f0 f5 7c 78 lmcpm1 \$c0,\(\$sp\+\),120
+ e2c: ff f5 30 78 smcpa \$c15,\(\$sp\+\),120
+ e30: ff f5 70 78 lmcpa \$c15,\(\$sp\+\),120
+ e34: ff f5 38 78 smcpm0 \$c15,\(\$sp\+\),120
+ e38: ff f5 78 78 lmcpm0 \$c15,\(\$sp\+\),120
+ e3c: ff f5 3c 78 smcpm1 \$c15,\(\$sp\+\),120
+ e40: ff f5 7c 78 lmcpm1 \$c15,\(\$sp\+\),120
+ e44: d8 04 80 02 bcpeq 0x0,0xffff0e48
+ e48: d8 05 80 02 bcpne 0x0,0xffff0e4c
+ e4c: d8 06 80 02 bcpat 0x0,0xffff0e50
+ e50: d8 07 80 02 bcpaf 0x0,0xffff0e54
+ e54: d8 f4 80 02 bcpeq 0xf,0xffff0e58
+ e58: d8 f5 80 02 bcpne 0xf,0xffff0e5c
+ e5c: d8 f6 80 02 bcpat 0xf,0xffff0e60
+ e60: d8 f7 80 02 bcpaf 0xf,0xffff0e64
+ e64: d8 04 3f ff bcpeq 0x0,0x8e62
+ e68: d8 05 3f ff bcpne 0x0,0x8e66
+ e6c: d8 06 3f ff bcpat 0x0,0x8e6a
+ e70: d8 07 3f ff bcpaf 0x0,0x8e6e
+ e74: d8 f4 3f ff bcpeq 0xf,0x8e72
+ e78: d8 f5 3f ff bcpne 0xf,0x8e76
+ e7c: d8 f6 3f ff bcpat 0xf,0x8e7a
+ e80: d8 f7 3f ff bcpaf 0xf,0x8e7e
+ e84: d8 04 00 00 bcpeq 0x0,0xe84
+ e84: R_MEP_PCREL17A2 symbol
+ e88: d8 05 00 00 bcpne 0x0,0xe88
+ e88: R_MEP_PCREL17A2 symbol
+ e8c: d8 06 00 00 bcpat 0x0,0xe8c
+ e8c: R_MEP_PCREL17A2 symbol
+ e90: d8 07 00 00 bcpaf 0x0,0xe90
+ e90: R_MEP_PCREL17A2 symbol
+ e94: d8 f4 00 00 bcpeq 0xf,0xe94
+ e94: R_MEP_PCREL17A2 symbol
+ e98: d8 f5 00 00 bcpne 0xf,0xe98
+ e98: R_MEP_PCREL17A2 symbol
+ e9c: d8 f6 00 00 bcpat 0xf,0xe9c
+ e9c: R_MEP_PCREL17A2 symbol
+ ea0: d8 f7 00 00 bcpaf 0xf,0xea0
+ ea0: R_MEP_PCREL17A2 symbol
+ ea4: 70 21 synccp
+ ea6: 18 0f jsrv \$0
+ ea8: 18 ff jsrv \$sp
+ eaa: d8 2b 80 00 bsrv 0xff800eae
+ eae: df fb 7f ff bsrv 0x800eac
+ eb2: d8 0b 00 00 bsrv 0xeb2
+ eb2: R_MEP_PCREL24A2 symbol
+ eb6: 00 00 nop
+ eb6: R_MEP_8 symbol
+ eb7: R_MEP_16 symbol
+ eb8: 00 00 nop
+ eb9: R_MEP_32 symbol
+ eba: 00 00 nop
+.*
+
--- /dev/null
+#as: -EL
+#objdump: -dr
+#source: dj1.s
+#name: dj1.le
+
+dump.o: file format elf32-mep-little
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 00 00 nop
+ 2: 00 01 mov \$1,\$0
+ 4: 00 02 mov \$2,\$0
+ 6: 00 03 mov \$3,\$0
+ 8: 00 04 mov \$4,\$0
+ a: 00 05 mov \$5,\$0
+ c: 00 06 mov \$6,\$0
+ e: 00 07 mov \$7,\$0
+ 10: 00 08 mov \$8,\$0
+ 12: 00 09 mov \$9,\$0
+ 14: 00 0a mov \$10,\$0
+ 16: 00 0b mov \$11,\$0
+ 18: 00 0c mov \$12,\$0
+ 1a: 00 0d mov \$tp,\$0
+ 1c: 00 0e mov \$gp,\$0
+ 1e: 00 0f mov \$sp,\$0
+ 20: 00 08 mov \$8,\$0
+ 22: 00 0d mov \$tp,\$0
+ 24: 00 0e mov \$gp,\$0
+ 26: 00 0f mov \$sp,\$0
+ 28: 08 00 sb \$0,\(\$0\)
+ 2a: 09 00 sh \$0,\(\$0\)
+ 2c: 0a 00 sw \$0,\(\$0\)
+ 2e: 0c 00 lb \$0,\(\$0\)
+ 30: 0d 00 lh \$0,\(\$0\)
+ 32: 0e 00 lw \$0,\(\$0\)
+ 34: 0b 00 lbu \$0,\(\$0\)
+ 36: 0f 00 lhu \$0,\(\$0\)
+ 38: 08 0f sb \$sp,\(\$0\)
+ 3a: 09 0f sh \$sp,\(\$0\)
+ 3c: 0a 0f sw \$sp,\(\$0\)
+ 3e: 0c 0f lb \$sp,\(\$0\)
+ 40: 0d 0f lh \$sp,\(\$0\)
+ 42: 0e 0f lw \$sp,\(\$0\)
+ 44: 0b 0f lbu \$sp,\(\$0\)
+ 46: 0f 0f lhu \$sp,\(\$0\)
+ 48: f8 00 sb \$0,\(\$sp\)
+ 4a: f9 00 sh \$0,\(\$sp\)
+ 4c: fa 00 sw \$0,\(\$sp\)
+ 4e: fc 00 lb \$0,\(\$sp\)
+ 50: fd 00 lh \$0,\(\$sp\)
+ 52: fe 00 lw \$0,\(\$sp\)
+ 54: fb 00 lbu \$0,\(\$sp\)
+ 56: ff 00 lhu \$0,\(\$sp\)
+ 58: f8 0f sb \$sp,\(\$sp\)
+ 5a: f9 0f sh \$sp,\(\$sp\)
+ 5c: fa 0f sw \$sp,\(\$sp\)
+ 5e: fc 0f lb \$sp,\(\$sp\)
+ 60: fd 0f lh \$sp,\(\$sp\)
+ 62: fe 0f lw \$sp,\(\$sp\)
+ 64: fb 0f lbu \$sp,\(\$sp\)
+ 66: ff 0f lhu \$sp,\(\$sp\)
+ 68: fa 00 sw \$0,\(\$sp\)
+ 6a: fe 00 lw \$0,\(\$sp\)
+ 6c: fa 0f sw \$sp,\(\$sp\)
+ 6e: fe 0f lw \$sp,\(\$sp\)
+ 70: 7e 40 sw \$0,0x7c\(\$sp\)
+ 72: 7f 40 lw \$0,0x7c\(\$sp\)
+ 74: 7e 4f sw \$sp,0x7c\(\$sp\)
+ 76: 7f 4f lw \$sp,0x7c\(\$sp\)
+ 78: fa 00 sw \$0,\(\$sp\)
+ 7a: fe 00 lw \$0,\(\$sp\)
+ 7c: fa 0f sw \$sp,\(\$sp\)
+ 7e: fe 0f lw \$sp,\(\$sp\)
+ 80: 7e 40 sw \$0,0x7c\(\$sp\)
+ 82: 7f 40 lw \$0,0x7c\(\$sp\)
+ 84: 7e 4f sw \$sp,0x7c\(\$sp\)
+ 86: 7f 4f lw \$sp,0x7c\(\$sp\)
+ 88: d8 00 sb \$0,\(\$tp\)
+ 8a: dc 00 lb \$0,\(\$tp\)
+ 8c: db 00 lbu \$0,\(\$tp\)
+ 8e: d8 07 sb \$7,\(\$tp\)
+ 90: dc 07 lb \$7,\(\$tp\)
+ 92: db 07 lbu \$7,\(\$tp\)
+ 94: 7f 80 sb \$0,0x7f\(\$tp\)
+ 96: 7f 88 lb \$0,0x7f\(\$tp\)
+ 98: ff 48 lbu \$0,0x7f\(\$tp\)
+ 9a: 7f 87 sb \$7,0x7f\(\$tp\)
+ 9c: 7f 8f lb \$7,0x7f\(\$tp\)
+ 9e: ff 4f lbu \$7,0x7f\(\$tp\)
+ a0: 00 80 sb \$0,0x0\(\$tp\)
+ a0: R_MEP_TPREL7 symbol
+ a2: 00 88 lb \$0,0x0\(\$tp\)
+ a2: R_MEP_TPREL7 symbol
+ a4: 80 48 lbu \$0,0x0\(\$tp\)
+ a4: R_MEP_TPREL7 symbol
+ a6: 00 87 sb \$7,0x0\(\$tp\)
+ a6: R_MEP_TPREL7 symbol
+ a8: 00 8f lb \$7,0x0\(\$tp\)
+ a8: R_MEP_TPREL7 symbol
+ aa: 80 4f lbu \$7,0x0\(\$tp\)
+ aa: R_MEP_TPREL7 symbol
+ ac: d8 00 sb \$0,\(\$tp\)
+ ae: dc 00 lb \$0,\(\$tp\)
+ b0: db 00 lbu \$0,\(\$tp\)
+ b2: d8 07 sb \$7,\(\$tp\)
+ b4: dc 07 lb \$7,\(\$tp\)
+ b6: db 07 lbu \$7,\(\$tp\)
+ b8: 7f 80 sb \$0,0x7f\(\$tp\)
+ ba: 7f 88 lb \$0,0x7f\(\$tp\)
+ bc: ff 48 lbu \$0,0x7f\(\$tp\)
+ be: 7f 87 sb \$7,0x7f\(\$tp\)
+ c0: 7f 8f lb \$7,0x7f\(\$tp\)
+ c2: ff 4f lbu \$7,0x7f\(\$tp\)
+ c4: 00 80 sb \$0,0x0\(\$tp\)
+ c4: R_MEP_TPREL7 symbol
+ c6: 00 88 lb \$0,0x0\(\$tp\)
+ c6: R_MEP_TPREL7 symbol
+ c8: 80 48 lbu \$0,0x0\(\$tp\)
+ c8: R_MEP_TPREL7 symbol
+ ca: 00 87 sb \$7,0x0\(\$tp\)
+ ca: R_MEP_TPREL7 symbol
+ cc: 00 8f lb \$7,0x0\(\$tp\)
+ cc: R_MEP_TPREL7 symbol
+ ce: 80 4f lbu \$7,0x0\(\$tp\)
+ ce: R_MEP_TPREL7 symbol
+ d0: d9 00 sh \$0,\(\$tp\)
+ d2: dd 00 lh \$0,\(\$tp\)
+ d4: df 00 lhu \$0,\(\$tp\)
+ d6: d9 07 sh \$7,\(\$tp\)
+ d8: dd 07 lh \$7,\(\$tp\)
+ da: df 07 lhu \$7,\(\$tp\)
+ dc: fe 80 sh \$0,0x7e\(\$tp\)
+ de: fe 88 lh \$0,0x7e\(\$tp\)
+ e0: ff 88 lhu \$0,0x7e\(\$tp\)
+ e2: fe 87 sh \$7,0x7e\(\$tp\)
+ e4: fe 8f lh \$7,0x7e\(\$tp\)
+ e6: ff 8f lhu \$7,0x7e\(\$tp\)
+ e8: 80 80 sh \$0,0x0\(\$tp\)
+ e8: R_MEP_TPREL7A2 symbol
+ ea: 80 88 lh \$0,0x0\(\$tp\)
+ ea: R_MEP_TPREL7A2 symbol
+ ec: 81 88 lhu \$0,0x0\(\$tp\)
+ ec: R_MEP_TPREL7A2 symbol
+ ee: 80 87 sh \$7,0x0\(\$tp\)
+ ee: R_MEP_TPREL7A2 symbol
+ f0: 80 8f lh \$7,0x0\(\$tp\)
+ f0: R_MEP_TPREL7A2 symbol
+ f2: 81 8f lhu \$7,0x0\(\$tp\)
+ f2: R_MEP_TPREL7A2 symbol
+ f4: d9 00 sh \$0,\(\$tp\)
+ f6: dd 00 lh \$0,\(\$tp\)
+ f8: df 00 lhu \$0,\(\$tp\)
+ fa: d9 07 sh \$7,\(\$tp\)
+ fc: dd 07 lh \$7,\(\$tp\)
+ fe: df 07 lhu \$7,\(\$tp\)
+ 100: fe 80 sh \$0,0x7e\(\$tp\)
+ 102: fe 88 lh \$0,0x7e\(\$tp\)
+ 104: ff 88 lhu \$0,0x7e\(\$tp\)
+ 106: fe 87 sh \$7,0x7e\(\$tp\)
+ 108: fe 8f lh \$7,0x7e\(\$tp\)
+ 10a: ff 8f lhu \$7,0x7e\(\$tp\)
+ 10c: 80 80 sh \$0,0x0\(\$tp\)
+ 10c: R_MEP_TPREL7A2 symbol
+ 10e: 80 88 lh \$0,0x0\(\$tp\)
+ 10e: R_MEP_TPREL7A2 symbol
+ 110: 81 88 lhu \$0,0x0\(\$tp\)
+ 110: R_MEP_TPREL7A2 symbol
+ 112: 80 87 sh \$7,0x0\(\$tp\)
+ 112: R_MEP_TPREL7A2 symbol
+ 114: 80 8f lh \$7,0x0\(\$tp\)
+ 114: R_MEP_TPREL7A2 symbol
+ 116: 81 8f lhu \$7,0x0\(\$tp\)
+ 116: R_MEP_TPREL7A2 symbol
+ 118: da 00 sw \$0,\(\$tp\)
+ 11a: de 00 lw \$0,\(\$tp\)
+ 11c: da 07 sw \$7,\(\$tp\)
+ 11e: de 07 lw \$7,\(\$tp\)
+ 120: fe 40 sw \$0,0x7c\(\$tp\)
+ 122: ff 40 lw \$0,0x7c\(\$tp\)
+ 124: fe 47 sw \$7,0x7c\(\$tp\)
+ 126: ff 47 lw \$7,0x7c\(\$tp\)
+ 128: 82 40 sw \$0,0x0\(\$tp\)
+ 128: R_MEP_TPREL7A4 symbol
+ 12a: 83 40 lw \$0,0x0\(\$tp\)
+ 12a: R_MEP_TPREL7A4 symbol
+ 12c: 82 47 sw \$7,0x0\(\$tp\)
+ 12c: R_MEP_TPREL7A4 symbol
+ 12e: 83 47 lw \$7,0x0\(\$tp\)
+ 12e: R_MEP_TPREL7A4 symbol
+ 130: da 00 sw \$0,\(\$tp\)
+ 132: de 00 lw \$0,\(\$tp\)
+ 134: da 07 sw \$7,\(\$tp\)
+ 136: de 07 lw \$7,\(\$tp\)
+ 138: fe 40 sw \$0,0x7c\(\$tp\)
+ 13a: ff 40 lw \$0,0x7c\(\$tp\)
+ 13c: fe 47 sw \$7,0x7c\(\$tp\)
+ 13e: ff 47 lw \$7,0x7c\(\$tp\)
+ 140: 82 40 sw \$0,0x0\(\$tp\)
+ 140: R_MEP_TPREL7A4 symbol
+ 142: 83 40 lw \$0,0x0\(\$tp\)
+ 142: R_MEP_TPREL7A4 symbol
+ 144: 82 47 sw \$7,0x0\(\$tp\)
+ 144: R_MEP_TPREL7A4 symbol
+ 146: 83 47 lw \$7,0x0\(\$tp\)
+ 146: R_MEP_TPREL7A4 symbol
+ 148: 08 c0 00 80 sb \$0,-32768\(\$0\)
+ 14c: 09 c0 00 80 sh \$0,-32768\(\$0\)
+ 150: 0a c0 00 80 sw \$0,-32768\(\$0\)
+ 154: 0c c0 00 80 lb \$0,-32768\(\$0\)
+ 158: 0d c0 00 80 lh \$0,-32768\(\$0\)
+ 15c: 0e c0 00 80 lw \$0,-32768\(\$0\)
+ 160: 0b c0 00 80 lbu \$0,-32768\(\$0\)
+ 164: 0f c0 00 80 lhu \$0,-32768\(\$0\)
+ 168: 08 cf 00 80 sb \$sp,-32768\(\$0\)
+ 16c: 09 cf 00 80 sh \$sp,-32768\(\$0\)
+ 170: 0a cf 00 80 sw \$sp,-32768\(\$0\)
+ 174: 0c cf 00 80 lb \$sp,-32768\(\$0\)
+ 178: 0d cf 00 80 lh \$sp,-32768\(\$0\)
+ 17c: 0e cf 00 80 lw \$sp,-32768\(\$0\)
+ 180: 0b cf 00 80 lbu \$sp,-32768\(\$0\)
+ 184: 0f cf 00 80 lhu \$sp,-32768\(\$0\)
+ 188: 08 c0 ff 7f sb \$0,32767\(\$0\)
+ 18c: 09 c0 ff 7f sh \$0,32767\(\$0\)
+ 190: 0a c0 ff 7f sw \$0,32767\(\$0\)
+ 194: 0c c0 ff 7f lb \$0,32767\(\$0\)
+ 198: 0d c0 ff 7f lh \$0,32767\(\$0\)
+ 19c: 0e c0 ff 7f lw \$0,32767\(\$0\)
+ 1a0: 0b c0 ff 7f lbu \$0,32767\(\$0\)
+ 1a4: 0f c0 ff 7f lhu \$0,32767\(\$0\)
+ 1a8: 08 cf ff 7f sb \$sp,32767\(\$0\)
+ 1ac: 09 cf ff 7f sh \$sp,32767\(\$0\)
+ 1b0: 0a cf ff 7f sw \$sp,32767\(\$0\)
+ 1b4: 0c cf ff 7f lb \$sp,32767\(\$0\)
+ 1b8: 0d cf ff 7f lh \$sp,32767\(\$0\)
+ 1bc: 0e cf ff 7f lw \$sp,32767\(\$0\)
+ 1c0: 0b cf ff 7f lbu \$sp,32767\(\$0\)
+ 1c4: 0f cf ff 7f lhu \$sp,32767\(\$0\)
+ 1c8: 08 c0 00 00 sb \$0,0\(\$0\)
+ 1c8: R_MEP_GPREL symbol
+ 1cc: 09 c0 00 00 sh \$0,0\(\$0\)
+ 1cc: R_MEP_GPREL symbol
+ 1d0: 0a c0 00 00 sw \$0,0\(\$0\)
+ 1d0: R_MEP_GPREL symbol
+ 1d4: 0c c0 00 00 lb \$0,0\(\$0\)
+ 1d4: R_MEP_GPREL symbol
+ 1d8: 0d c0 00 00 lh \$0,0\(\$0\)
+ 1d8: R_MEP_GPREL symbol
+ 1dc: 0e c0 00 00 lw \$0,0\(\$0\)
+ 1dc: R_MEP_GPREL symbol
+ 1e0: 0b c0 00 00 lbu \$0,0\(\$0\)
+ 1e0: R_MEP_GPREL symbol
+ 1e4: 0f c0 00 00 lhu \$0,0\(\$0\)
+ 1e4: R_MEP_GPREL symbol
+ 1e8: 08 cf 00 00 sb \$sp,0\(\$0\)
+ 1e8: R_MEP_GPREL symbol
+ 1ec: 09 cf 00 00 sh \$sp,0\(\$0\)
+ 1ec: R_MEP_GPREL symbol
+ 1f0: 0a cf 00 00 sw \$sp,0\(\$0\)
+ 1f0: R_MEP_GPREL symbol
+ 1f4: 0c cf 00 00 lb \$sp,0\(\$0\)
+ 1f4: R_MEP_GPREL symbol
+ 1f8: 0d cf 00 00 lh \$sp,0\(\$0\)
+ 1f8: R_MEP_GPREL symbol
+ 1fc: 0e cf 00 00 lw \$sp,0\(\$0\)
+ 1fc: R_MEP_GPREL symbol
+ 200: 0b cf 00 00 lbu \$sp,0\(\$0\)
+ 200: R_MEP_GPREL symbol
+ 204: 0f cf 00 00 lhu \$sp,0\(\$0\)
+ 204: R_MEP_GPREL symbol
+ 208: 08 c0 00 80 sb \$0,-32768\(\$0\)
+ 20c: 09 c0 00 80 sh \$0,-32768\(\$0\)
+ 210: 0a c0 00 80 sw \$0,-32768\(\$0\)
+ 214: 0c c0 00 80 lb \$0,-32768\(\$0\)
+ 218: 0d c0 00 80 lh \$0,-32768\(\$0\)
+ 21c: 0e c0 00 80 lw \$0,-32768\(\$0\)
+ 220: 0b c0 00 80 lbu \$0,-32768\(\$0\)
+ 224: 0f c0 00 80 lhu \$0,-32768\(\$0\)
+ 228: 08 cf 00 80 sb \$sp,-32768\(\$0\)
+ 22c: 09 cf 00 80 sh \$sp,-32768\(\$0\)
+ 230: 0a cf 00 80 sw \$sp,-32768\(\$0\)
+ 234: 0c cf 00 80 lb \$sp,-32768\(\$0\)
+ 238: 0d cf 00 80 lh \$sp,-32768\(\$0\)
+ 23c: 0e cf 00 80 lw \$sp,-32768\(\$0\)
+ 240: 0b cf 00 80 lbu \$sp,-32768\(\$0\)
+ 244: 0f cf 00 80 lhu \$sp,-32768\(\$0\)
+ 248: 08 c0 ff 7f sb \$0,32767\(\$0\)
+ 24c: 09 c0 ff 7f sh \$0,32767\(\$0\)
+ 250: 0a c0 ff 7f sw \$0,32767\(\$0\)
+ 254: 0c c0 ff 7f lb \$0,32767\(\$0\)
+ 258: 0d c0 ff 7f lh \$0,32767\(\$0\)
+ 25c: 0e c0 ff 7f lw \$0,32767\(\$0\)
+ 260: 0b c0 ff 7f lbu \$0,32767\(\$0\)
+ 264: 0f c0 ff 7f lhu \$0,32767\(\$0\)
+ 268: 08 cf ff 7f sb \$sp,32767\(\$0\)
+ 26c: 09 cf ff 7f sh \$sp,32767\(\$0\)
+ 270: 0a cf ff 7f sw \$sp,32767\(\$0\)
+ 274: 0c cf ff 7f lb \$sp,32767\(\$0\)
+ 278: 0d cf ff 7f lh \$sp,32767\(\$0\)
+ 27c: 0e cf ff 7f lw \$sp,32767\(\$0\)
+ 280: 0b cf ff 7f lbu \$sp,32767\(\$0\)
+ 284: 0f cf ff 7f lhu \$sp,32767\(\$0\)
+ 288: 08 c0 00 00 sb \$0,0\(\$0\)
+ 288: R_MEP_TPREL symbol
+ 28c: 09 c0 00 00 sh \$0,0\(\$0\)
+ 28c: R_MEP_TPREL symbol
+ 290: 0a c0 00 00 sw \$0,0\(\$0\)
+ 290: R_MEP_TPREL symbol
+ 294: 0c c0 00 00 lb \$0,0\(\$0\)
+ 294: R_MEP_TPREL symbol
+ 298: 0d c0 00 00 lh \$0,0\(\$0\)
+ 298: R_MEP_TPREL symbol
+ 29c: 0e c0 00 00 lw \$0,0\(\$0\)
+ 29c: R_MEP_TPREL symbol
+ 2a0: 0b c0 00 00 lbu \$0,0\(\$0\)
+ 2a0: R_MEP_TPREL symbol
+ 2a4: 0f c0 00 00 lhu \$0,0\(\$0\)
+ 2a4: R_MEP_TPREL symbol
+ 2a8: 08 cf 00 00 sb \$sp,0\(\$0\)
+ 2a8: R_MEP_TPREL symbol
+ 2ac: 09 cf 00 00 sh \$sp,0\(\$0\)
+ 2ac: R_MEP_TPREL symbol
+ 2b0: 0a cf 00 00 sw \$sp,0\(\$0\)
+ 2b0: R_MEP_TPREL symbol
+ 2b4: 0c cf 00 00 lb \$sp,0\(\$0\)
+ 2b4: R_MEP_TPREL symbol
+ 2b8: 0d cf 00 00 lh \$sp,0\(\$0\)
+ 2b8: R_MEP_TPREL symbol
+ 2bc: 0e cf 00 00 lw \$sp,0\(\$0\)
+ 2bc: R_MEP_TPREL symbol
+ 2c0: 0b cf 00 00 lbu \$sp,0\(\$0\)
+ 2c0: R_MEP_TPREL symbol
+ 2c4: 0f cf 00 00 lhu \$sp,0\(\$0\)
+ 2c4: R_MEP_TPREL symbol
+ 2c8: f8 c0 00 80 sb \$0,-32768\(\$sp\)
+ 2cc: f9 c0 00 80 sh \$0,-32768\(\$sp\)
+ 2d0: fa c0 00 80 sw \$0,-32768\(\$sp\)
+ 2d4: fc c0 00 80 lb \$0,-32768\(\$sp\)
+ 2d8: fd c0 00 80 lh \$0,-32768\(\$sp\)
+ 2dc: fe c0 00 80 lw \$0,-32768\(\$sp\)
+ 2e0: fb c0 00 80 lbu \$0,-32768\(\$sp\)
+ 2e4: ff c0 00 80 lhu \$0,-32768\(\$sp\)
+ 2e8: f8 cf 00 80 sb \$sp,-32768\(\$sp\)
+ 2ec: f9 cf 00 80 sh \$sp,-32768\(\$sp\)
+ 2f0: fa cf 00 80 sw \$sp,-32768\(\$sp\)
+ 2f4: fc cf 00 80 lb \$sp,-32768\(\$sp\)
+ 2f8: fd cf 00 80 lh \$sp,-32768\(\$sp\)
+ 2fc: fe cf 00 80 lw \$sp,-32768\(\$sp\)
+ 300: fb cf 00 80 lbu \$sp,-32768\(\$sp\)
+ 304: ff cf 00 80 lhu \$sp,-32768\(\$sp\)
+ 308: f8 c0 ff 7f sb \$0,32767\(\$sp\)
+ 30c: f9 c0 ff 7f sh \$0,32767\(\$sp\)
+ 310: fa c0 ff 7f sw \$0,32767\(\$sp\)
+ 314: fc c0 ff 7f lb \$0,32767\(\$sp\)
+ 318: fd c0 ff 7f lh \$0,32767\(\$sp\)
+ 31c: fe c0 ff 7f lw \$0,32767\(\$sp\)
+ 320: fb c0 ff 7f lbu \$0,32767\(\$sp\)
+ 324: ff c0 ff 7f lhu \$0,32767\(\$sp\)
+ 328: f8 cf ff 7f sb \$sp,32767\(\$sp\)
+ 32c: f9 cf ff 7f sh \$sp,32767\(\$sp\)
+ 330: fa cf ff 7f sw \$sp,32767\(\$sp\)
+ 334: fc cf ff 7f lb \$sp,32767\(\$sp\)
+ 338: fd cf ff 7f lh \$sp,32767\(\$sp\)
+ 33c: fe cf ff 7f lw \$sp,32767\(\$sp\)
+ 340: fb cf ff 7f lbu \$sp,32767\(\$sp\)
+ 344: ff cf ff 7f lhu \$sp,32767\(\$sp\)
+ 348: f8 c0 00 00 sb \$0,0\(\$sp\)
+ 348: R_MEP_GPREL symbol
+ 34c: f9 c0 00 00 sh \$0,0\(\$sp\)
+ 34c: R_MEP_GPREL symbol
+ 350: fa c0 00 00 sw \$0,0\(\$sp\)
+ 350: R_MEP_GPREL symbol
+ 354: fc c0 00 00 lb \$0,0\(\$sp\)
+ 354: R_MEP_GPREL symbol
+ 358: fd c0 00 00 lh \$0,0\(\$sp\)
+ 358: R_MEP_GPREL symbol
+ 35c: fe c0 00 00 lw \$0,0\(\$sp\)
+ 35c: R_MEP_GPREL symbol
+ 360: fb c0 00 00 lbu \$0,0\(\$sp\)
+ 360: R_MEP_GPREL symbol
+ 364: ff c0 00 00 lhu \$0,0\(\$sp\)
+ 364: R_MEP_GPREL symbol
+ 368: f8 cf 00 00 sb \$sp,0\(\$sp\)
+ 368: R_MEP_GPREL symbol
+ 36c: f9 cf 00 00 sh \$sp,0\(\$sp\)
+ 36c: R_MEP_GPREL symbol
+ 370: fa cf 00 00 sw \$sp,0\(\$sp\)
+ 370: R_MEP_GPREL symbol
+ 374: fc cf 00 00 lb \$sp,0\(\$sp\)
+ 374: R_MEP_GPREL symbol
+ 378: fd cf 00 00 lh \$sp,0\(\$sp\)
+ 378: R_MEP_GPREL symbol
+ 37c: fe cf 00 00 lw \$sp,0\(\$sp\)
+ 37c: R_MEP_GPREL symbol
+ 380: fb cf 00 00 lbu \$sp,0\(\$sp\)
+ 380: R_MEP_GPREL symbol
+ 384: ff cf 00 00 lhu \$sp,0\(\$sp\)
+ 384: R_MEP_GPREL symbol
+ 388: f8 c0 00 80 sb \$0,-32768\(\$sp\)
+ 38c: f9 c0 00 80 sh \$0,-32768\(\$sp\)
+ 390: fa c0 00 80 sw \$0,-32768\(\$sp\)
+ 394: fc c0 00 80 lb \$0,-32768\(\$sp\)
+ 398: fd c0 00 80 lh \$0,-32768\(\$sp\)
+ 39c: fe c0 00 80 lw \$0,-32768\(\$sp\)
+ 3a0: fb c0 00 80 lbu \$0,-32768\(\$sp\)
+ 3a4: ff c0 00 80 lhu \$0,-32768\(\$sp\)
+ 3a8: f8 cf 00 80 sb \$sp,-32768\(\$sp\)
+ 3ac: f9 cf 00 80 sh \$sp,-32768\(\$sp\)
+ 3b0: fa cf 00 80 sw \$sp,-32768\(\$sp\)
+ 3b4: fc cf 00 80 lb \$sp,-32768\(\$sp\)
+ 3b8: fd cf 00 80 lh \$sp,-32768\(\$sp\)
+ 3bc: fe cf 00 80 lw \$sp,-32768\(\$sp\)
+ 3c0: fb cf 00 80 lbu \$sp,-32768\(\$sp\)
+ 3c4: ff cf 00 80 lhu \$sp,-32768\(\$sp\)
+ 3c8: f8 c0 ff 7f sb \$0,32767\(\$sp\)
+ 3cc: f9 c0 ff 7f sh \$0,32767\(\$sp\)
+ 3d0: fa c0 ff 7f sw \$0,32767\(\$sp\)
+ 3d4: fc c0 ff 7f lb \$0,32767\(\$sp\)
+ 3d8: fd c0 ff 7f lh \$0,32767\(\$sp\)
+ 3dc: fe c0 ff 7f lw \$0,32767\(\$sp\)
+ 3e0: fb c0 ff 7f lbu \$0,32767\(\$sp\)
+ 3e4: ff c0 ff 7f lhu \$0,32767\(\$sp\)
+ 3e8: f8 cf ff 7f sb \$sp,32767\(\$sp\)
+ 3ec: f9 cf ff 7f sh \$sp,32767\(\$sp\)
+ 3f0: fa cf ff 7f sw \$sp,32767\(\$sp\)
+ 3f4: fc cf ff 7f lb \$sp,32767\(\$sp\)
+ 3f8: fd cf ff 7f lh \$sp,32767\(\$sp\)
+ 3fc: fe cf ff 7f lw \$sp,32767\(\$sp\)
+ 400: fb cf ff 7f lbu \$sp,32767\(\$sp\)
+ 404: ff cf ff 7f lhu \$sp,32767\(\$sp\)
+ 408: f8 c0 00 00 sb \$0,0\(\$sp\)
+ 408: R_MEP_TPREL symbol
+ 40c: f9 c0 00 00 sh \$0,0\(\$sp\)
+ 40c: R_MEP_TPREL symbol
+ 410: 02 40 sw \$0,0x0\(\$sp\)
+ 410: R_MEP_TPREL7A4 symbol
+ 412: fc c0 00 00 lb \$0,0\(\$sp\)
+ 412: R_MEP_TPREL symbol
+ 416: fd c0 00 00 lh \$0,0\(\$sp\)
+ 416: R_MEP_TPREL symbol
+ 41a: 03 40 lw \$0,0x0\(\$sp\)
+ 41a: R_MEP_TPREL7A4 symbol
+ 41c: fb c0 00 00 lbu \$0,0\(\$sp\)
+ 41c: R_MEP_TPREL symbol
+ 420: ff c0 00 00 lhu \$0,0\(\$sp\)
+ 420: R_MEP_TPREL symbol
+ 424: f8 cf 00 00 sb \$sp,0\(\$sp\)
+ 424: R_MEP_TPREL symbol
+ 428: f9 cf 00 00 sh \$sp,0\(\$sp\)
+ 428: R_MEP_TPREL symbol
+ 42c: 02 4f sw \$sp,0x0\(\$sp\)
+ 42c: R_MEP_TPREL7A4 symbol
+ 42e: fc cf 00 00 lb \$sp,0\(\$sp\)
+ 42e: R_MEP_TPREL symbol
+ 432: fd cf 00 00 lh \$sp,0\(\$sp\)
+ 432: R_MEP_TPREL symbol
+ 436: 03 4f lw \$sp,0x0\(\$sp\)
+ 436: R_MEP_TPREL7A4 symbol
+ 438: fb cf 00 00 lbu \$sp,0\(\$sp\)
+ 438: R_MEP_TPREL symbol
+ 43c: ff cf 00 00 lhu \$sp,0\(\$sp\)
+ 43c: R_MEP_TPREL symbol
+ 440: 02 e0 00 00 sw \$0,\(0x0\)
+ 444: 03 e0 00 00 lw \$0,\(0x0\)
+ 448: 02 ef 00 00 sw \$sp,\(0x0\)
+ 44c: 03 ef 00 00 lw \$sp,\(0x0\)
+ 450: fe e0 ff ff sw \$0,\(0xfffffc\)
+ 454: ff e0 ff ff lw \$0,\(0xfffffc\)
+ 458: fe ef ff ff sw \$sp,\(0xfffffc\)
+ 45c: ff ef ff ff lw \$sp,\(0xfffffc\)
+ 460: 02 e0 00 00 sw \$0,\(0x0\)
+ 460: R_MEP_ADDR24A4 symbol
+ 464: 03 e0 00 00 lw \$0,\(0x0\)
+ 464: R_MEP_ADDR24A4 symbol
+ 468: 02 ef 00 00 sw \$sp,\(0x0\)
+ 468: R_MEP_ADDR24A4 symbol
+ 46c: 03 ef 00 00 lw \$sp,\(0x0\)
+ 46c: R_MEP_ADDR24A4 symbol
+ 470: 0d 10 extb \$0
+ 472: 8d 10 extub \$0
+ 474: 2d 10 exth \$0
+ 476: ad 10 extuh \$0
+ 478: 0d 1f extb \$sp
+ 47a: 8d 1f extub \$sp
+ 47c: 2d 1f exth \$sp
+ 47e: ad 1f extuh \$sp
+ 480: 0c 10 ssarb 0\(\$0\)
+ 482: 0c 13 ssarb 3\(\$0\)
+ 484: fc 10 ssarb 0\(\$sp\)
+ 486: fc 13 ssarb 3\(\$sp\)
+ 488: 00 00 nop
+ 48a: 00 0f mov \$sp,\$0
+ 48c: f0 00 mov \$0,\$sp
+ 48e: f0 0f mov \$sp,\$sp
+ 490: 01 c0 00 80 mov \$0,-32768
+ 494: 01 cf 00 80 mov \$sp,-32768
+ 498: 80 50 mov \$0,-128
+ 49a: 80 5f mov \$sp,-128
+ 49c: 00 50 mov \$0,0
+ 49e: 00 5f mov \$sp,0
+ 4a0: 7f 50 mov \$0,127
+ 4a2: 7f 5f mov \$sp,127
+ 4a4: 01 c0 ff 7f mov \$0,32767
+ 4a8: 01 cf ff 7f mov \$sp,32767
+ 4ac: 01 c0 00 00 mov \$0,0
+ 4ac: R_MEP_LOW16 symbol
+ 4b0: 01 c0 00 00 mov \$0,0
+ 4b0: R_MEP_HI16S symbol
+ 4b4: 01 c0 00 00 mov \$0,0
+ 4b4: R_MEP_HI16U symbol
+ 4b8: 01 c0 00 00 mov \$0,0
+ 4b8: R_MEP_GPREL symbol
+ 4bc: 01 c0 00 00 mov \$0,0
+ 4bc: R_MEP_TPREL symbol
+ 4c0: 00 d0 00 00 movu \$0,0x0
+ 4c4: 00 d7 00 00 movu \$7,0x0
+ 4c8: ff d0 ff ff movu \$0,0xffffff
+ 4cc: ff d7 ff ff movu \$7,0xffffff
+ 4d0: 11 c0 00 00 movu \$0,0x0
+ 4d0: R_MEP_LOW16 symbol
+ 4d4: 11 c7 00 00 movu \$7,0x0
+ 4d4: R_MEP_LOW16 symbol
+ 4d8: 00 d0 00 00 movu \$0,0x0
+ 4d8: R_MEP_UIMM24 symbol
+ 4dc: 00 d7 00 00 movu \$7,0x0
+ 4dc: R_MEP_UIMM24 symbol
+ 4e0: 00 d0 00 00 movu \$0,0x0
+ 4e4: 21 c0 00 00 movh \$0,0x0
+ 4e8: 11 cf 00 00 movu \$sp,0x0
+ 4ec: 21 cf 00 00 movh \$sp,0x0
+ 4f0: ff d0 ff 00 movu \$0,0xffff
+ 4f4: 21 c0 ff ff movh \$0,0xffff
+ 4f8: 11 cf ff ff movu \$sp,0xffff
+ 4fc: 21 cf ff ff movh \$sp,0xffff
+ 500: 11 c0 00 00 movu \$0,0x0
+ 500: R_MEP_LOW16 symbol
+ 504: 21 c0 00 00 movh \$0,0x0
+ 504: R_MEP_LOW16 symbol
+ 508: 11 cf 00 00 movu \$sp,0x0
+ 508: R_MEP_LOW16 symbol
+ 50c: 21 cf 00 00 movh \$sp,0x0
+ 50c: R_MEP_LOW16 symbol
+ 510: 11 c0 00 00 movu \$0,0x0
+ 510: R_MEP_HI16S symbol
+ 514: 21 c0 00 00 movh \$0,0x0
+ 514: R_MEP_HI16S symbol
+ 518: 11 cf 00 00 movu \$sp,0x0
+ 518: R_MEP_HI16S symbol
+ 51c: 21 cf 00 00 movh \$sp,0x0
+ 51c: R_MEP_HI16S symbol
+ 520: 11 c0 00 00 movu \$0,0x0
+ 520: R_MEP_HI16U symbol
+ 524: 21 c0 00 00 movh \$0,0x0
+ 524: R_MEP_HI16U symbol
+ 528: 11 cf 00 00 movu \$sp,0x0
+ 528: R_MEP_HI16U symbol
+ 52c: 21 cf 00 00 movh \$sp,0x0
+ 52c: R_MEP_HI16U symbol
+ 530: 11 c0 78 56 movu \$0,0x5678
+ 534: 21 c0 78 56 movh \$0,0x5678
+ 538: 11 cf 78 56 movu \$sp,0x5678
+ 53c: 21 cf 78 56 movh \$sp,0x5678
+ 540: 11 c0 34 12 movu \$0,0x1234
+ 544: 21 c0 34 12 movh \$0,0x1234
+ 548: 11 cf 34 12 movu \$sp,0x1234
+ 54c: 21 cf 34 12 movh \$sp,0x1234
+ 550: 11 c0 34 12 movu \$0,0x1234
+ 554: 21 c0 34 12 movh \$0,0x1234
+ 558: 11 cf 34 12 movu \$sp,0x1234
+ 55c: 21 cf 34 12 movh \$sp,0x1234
+ 560: 00 90 add3 \$0,\$0,\$0
+ 562: 0f 90 add3 \$sp,\$0,\$0
+ 564: 00 9f add3 \$0,\$sp,\$0
+ 566: 0f 9f add3 \$sp,\$sp,\$0
+ 568: f0 90 add3 \$0,\$0,\$sp
+ 56a: ff 90 add3 \$sp,\$0,\$sp
+ 56c: f0 9f add3 \$0,\$sp,\$sp
+ 56e: ff 9f add3 \$sp,\$sp,\$sp
+ 570: c0 60 add \$0,-16
+ 572: c0 6f add \$sp,-16
+ 574: 00 60 add \$0,0
+ 576: 00 6f add \$sp,0
+ 578: 3c 60 add \$0,15
+ 57a: 3c 6f add \$sp,15
+ 57c: 00 40 add3 \$0,\$sp,0x0
+ 57e: 00 4f add3 \$sp,\$sp,0x0
+ 580: 7c 40 add3 \$0,\$sp,0x7c
+ 582: 7c 4f add3 \$sp,\$sp,0x7c
+ 584: f0 c0 01 00 add3 \$0,\$sp,1
+ 588: f0 cf 01 00 add3 \$sp,\$sp,1
+ 58c: 07 00 advck3 \$0,\$0,\$0
+ 58e: 05 00 sbvck3 \$0,\$0,\$0
+ 590: 07 0f advck3 \$0,\$sp,\$0
+ 592: 05 0f sbvck3 \$0,\$sp,\$0
+ 594: f7 00 advck3 \$0,\$0,\$sp
+ 596: f5 00 sbvck3 \$0,\$0,\$sp
+ 598: f7 0f advck3 \$0,\$sp,\$sp
+ 59a: f5 0f sbvck3 \$0,\$sp,\$sp
+ 59c: 04 00 sub \$0,\$0
+ 59e: 01 00 neg \$0,\$0
+ 5a0: 04 0f sub \$sp,\$0
+ 5a2: 01 0f neg \$sp,\$0
+ 5a4: f4 00 sub \$0,\$sp
+ 5a6: f1 00 neg \$0,\$sp
+ 5a8: f4 0f sub \$sp,\$sp
+ 5aa: f1 0f neg \$sp,\$sp
+ 5ac: 02 00 slt3 \$0,\$0,\$0
+ 5ae: 03 00 sltu3 \$0,\$0,\$0
+ 5b0: 06 20 sl1ad3 \$0,\$0,\$0
+ 5b2: 07 20 sl2ad3 \$0,\$0,\$0
+ 5b4: 02 0f slt3 \$0,\$sp,\$0
+ 5b6: 03 0f sltu3 \$0,\$sp,\$0
+ 5b8: 06 2f sl1ad3 \$0,\$sp,\$0
+ 5ba: 07 2f sl2ad3 \$0,\$sp,\$0
+ 5bc: f2 00 slt3 \$0,\$0,\$sp
+ 5be: f3 00 sltu3 \$0,\$0,\$sp
+ 5c0: f6 20 sl1ad3 \$0,\$0,\$sp
+ 5c2: f7 20 sl2ad3 \$0,\$0,\$sp
+ 5c4: f2 0f slt3 \$0,\$sp,\$sp
+ 5c6: f3 0f sltu3 \$0,\$sp,\$sp
+ 5c8: f6 2f sl1ad3 \$0,\$sp,\$sp
+ 5ca: f7 2f sl2ad3 \$0,\$sp,\$sp
+ 5cc: 00 c0 00 80 add3 \$0,\$0,-32768
+ 5d0: 00 cf 00 80 add3 \$sp,\$0,-32768
+ 5d4: f0 c0 00 80 add3 \$0,\$sp,-32768
+ 5d8: f0 cf 00 80 add3 \$sp,\$sp,-32768
+ 5dc: 00 c0 ff 7f add3 \$0,\$0,32767
+ 5e0: 00 cf ff 7f add3 \$sp,\$0,32767
+ 5e4: f0 c0 ff 7f add3 \$0,\$sp,32767
+ 5e8: f0 cf ff 7f add3 \$sp,\$sp,32767
+ 5ec: 00 c0 00 00 add3 \$0,\$0,0
+ 5ec: R_MEP_LOW16 symbol
+ 5f0: 00 cf 00 00 add3 \$sp,\$0,0
+ 5f0: R_MEP_LOW16 symbol
+ 5f4: f0 c0 00 00 add3 \$0,\$sp,0
+ 5f4: R_MEP_LOW16 symbol
+ 5f8: f0 cf 00 00 add3 \$sp,\$sp,0
+ 5f8: R_MEP_LOW16 symbol
+ 5fc: 01 60 slt3 \$0,\$0,0x0
+ 5fe: 05 60 sltu3 \$0,\$0,0x0
+ 600: 01 6f slt3 \$0,\$sp,0x0
+ 602: 05 6f sltu3 \$0,\$sp,0x0
+ 604: f9 60 slt3 \$0,\$0,0x1f
+ 606: fd 60 sltu3 \$0,\$0,0x1f
+ 608: f9 6f slt3 \$0,\$sp,0x1f
+ 60a: fd 6f sltu3 \$0,\$sp,0x1f
+ 60c: 00 10 or \$0,\$0
+ 60e: 01 10 and \$0,\$0
+ 610: 02 10 xor \$0,\$0
+ 612: 03 10 nor \$0,\$0
+ 614: 00 1f or \$sp,\$0
+ 616: 01 1f and \$sp,\$0
+ 618: 02 1f xor \$sp,\$0
+ 61a: 03 1f nor \$sp,\$0
+ 61c: f0 10 or \$0,\$sp
+ 61e: f1 10 and \$0,\$sp
+ 620: f2 10 xor \$0,\$sp
+ 622: f3 10 nor \$0,\$sp
+ 624: f0 1f or \$sp,\$sp
+ 626: f1 1f and \$sp,\$sp
+ 628: f2 1f xor \$sp,\$sp
+ 62a: f3 1f nor \$sp,\$sp
+ 62c: 04 c0 00 00 or3 \$0,\$0,0x0
+ 630: 05 c0 00 00 and3 \$0,\$0,0x0
+ 634: 06 c0 00 00 xor3 \$0,\$0,0x0
+ 638: 04 cf 00 00 or3 \$sp,\$0,0x0
+ 63c: 05 cf 00 00 and3 \$sp,\$0,0x0
+ 640: 06 cf 00 00 xor3 \$sp,\$0,0x0
+ 644: f4 c0 00 00 or3 \$0,\$sp,0x0
+ 648: f5 c0 00 00 and3 \$0,\$sp,0x0
+ 64c: f6 c0 00 00 xor3 \$0,\$sp,0x0
+ 650: f4 cf 00 00 or3 \$sp,\$sp,0x0
+ 654: f5 cf 00 00 and3 \$sp,\$sp,0x0
+ 658: f6 cf 00 00 xor3 \$sp,\$sp,0x0
+ 65c: 04 c0 ff ff or3 \$0,\$0,0xffff
+ 660: 05 c0 ff ff and3 \$0,\$0,0xffff
+ 664: 06 c0 ff ff xor3 \$0,\$0,0xffff
+ 668: 04 cf ff ff or3 \$sp,\$0,0xffff
+ 66c: 05 cf ff ff and3 \$sp,\$0,0xffff
+ 670: 06 cf ff ff xor3 \$sp,\$0,0xffff
+ 674: f4 c0 ff ff or3 \$0,\$sp,0xffff
+ 678: f5 c0 ff ff and3 \$0,\$sp,0xffff
+ 67c: f6 c0 ff ff xor3 \$0,\$sp,0xffff
+ 680: f4 cf ff ff or3 \$sp,\$sp,0xffff
+ 684: f5 cf ff ff and3 \$sp,\$sp,0xffff
+ 688: f6 cf ff ff xor3 \$sp,\$sp,0xffff
+ 68c: 04 c0 00 00 or3 \$0,\$0,0x0
+ 68c: R_MEP_LOW16 symbol
+ 690: 05 c0 00 00 and3 \$0,\$0,0x0
+ 690: R_MEP_LOW16 symbol
+ 694: 06 c0 00 00 xor3 \$0,\$0,0x0
+ 694: R_MEP_LOW16 symbol
+ 698: 04 cf 00 00 or3 \$sp,\$0,0x0
+ 698: R_MEP_LOW16 symbol
+ 69c: 05 cf 00 00 and3 \$sp,\$0,0x0
+ 69c: R_MEP_LOW16 symbol
+ 6a0: 06 cf 00 00 xor3 \$sp,\$0,0x0
+ 6a0: R_MEP_LOW16 symbol
+ 6a4: f4 c0 00 00 or3 \$0,\$sp,0x0
+ 6a4: R_MEP_LOW16 symbol
+ 6a8: f5 c0 00 00 and3 \$0,\$sp,0x0
+ 6a8: R_MEP_LOW16 symbol
+ 6ac: f6 c0 00 00 xor3 \$0,\$sp,0x0
+ 6ac: R_MEP_LOW16 symbol
+ 6b0: f4 cf 00 00 or3 \$sp,\$sp,0x0
+ 6b0: R_MEP_LOW16 symbol
+ 6b4: f5 cf 00 00 and3 \$sp,\$sp,0x0
+ 6b4: R_MEP_LOW16 symbol
+ 6b8: f6 cf 00 00 xor3 \$sp,\$sp,0x0
+ 6b8: R_MEP_LOW16 symbol
+ 6bc: 0d 20 sra \$0,\$0
+ 6be: 0c 20 srl \$0,\$0
+ 6c0: 0e 20 sll \$0,\$0
+ 6c2: 0f 20 fsft \$0,\$0
+ 6c4: 0d 2f sra \$sp,\$0
+ 6c6: 0c 2f srl \$sp,\$0
+ 6c8: 0e 2f sll \$sp,\$0
+ 6ca: 0f 2f fsft \$sp,\$0
+ 6cc: fd 20 sra \$0,\$sp
+ 6ce: fc 20 srl \$0,\$sp
+ 6d0: fe 20 sll \$0,\$sp
+ 6d2: ff 20 fsft \$0,\$sp
+ 6d4: fd 2f sra \$sp,\$sp
+ 6d6: fc 2f srl \$sp,\$sp
+ 6d8: fe 2f sll \$sp,\$sp
+ 6da: ff 2f fsft \$sp,\$sp
+ 6dc: 03 60 sra \$0,0x0
+ 6de: 02 60 srl \$0,0x0
+ 6e0: 06 60 sll \$0,0x0
+ 6e2: 03 6f sra \$sp,0x0
+ 6e4: 02 6f srl \$sp,0x0
+ 6e6: 06 6f sll \$sp,0x0
+ 6e8: fb 60 sra \$0,0x1f
+ 6ea: fa 60 srl \$0,0x1f
+ 6ec: fe 60 sll \$0,0x1f
+ 6ee: fb 6f sra \$sp,0x1f
+ 6f0: fa 6f srl \$sp,0x1f
+ 6f2: fe 6f sll \$sp,0x1f
+ 6f4: 07 60 sll3 \$0,\$0,0x0
+ 6f6: 07 6f sll3 \$0,\$sp,0x0
+ 6f8: ff 60 sll3 \$0,\$0,0x1f
+ 6fa: ff 6f sll3 \$0,\$sp,0x1f
+ 6fc: 02 b8 bra 0xfffffefe
+ 6fe: 01 e0 00 04 beq \$0,\$0,0xefe
+ 702: 00 b0 bra 0x702
+ 702: R_MEP_PCREL12A2 symbol
+ 704: 82 a0 beqz \$0,0x686
+ 706: 83 a0 bnez \$0,0x688
+ 708: 82 af beqz \$sp,0x68a
+ 70a: 83 af bnez \$sp,0x68c
+ 70c: 00 e0 40 00 beqi \$0,0x0,0x78c
+ 710: 04 e0 40 00 bnei \$0,0x0,0x790
+ 714: 00 ef 40 00 beqi \$sp,0x0,0x794
+ 718: 04 ef 40 00 bnei \$sp,0x0,0x798
+ 71c: 00 a0 beqz \$0,0x71c
+ 71c: R_MEP_PCREL8A2 symbol
+ 71e: 01 a0 bnez \$0,0x71e
+ 71e: R_MEP_PCREL8A2 symbol
+ 720: 00 af beqz \$sp,0x720
+ 720: R_MEP_PCREL8A2 symbol
+ 722: 01 af bnez \$sp,0x722
+ 722: R_MEP_PCREL8A2 symbol
+ 724: 00 e0 02 80 beqi \$0,0x0,0xffff0728
+ 728: 04 e0 02 80 bnei \$0,0x0,0xffff072c
+ 72c: 0c e0 02 80 blti \$0,0x0,0xffff0730
+ 730: 08 e0 02 80 bgei \$0,0x0,0xffff0734
+ 734: 00 ef 02 80 beqi \$sp,0x0,0xffff0738
+ 738: 04 ef 02 80 bnei \$sp,0x0,0xffff073c
+ 73c: 0c ef 02 80 blti \$sp,0x0,0xffff0740
+ 740: 08 ef 02 80 bgei \$sp,0x0,0xffff0744
+ 744: f0 e0 02 80 beqi \$0,0xf,0xffff0748
+ 748: f4 e0 02 80 bnei \$0,0xf,0xffff074c
+ 74c: fc e0 02 80 blti \$0,0xf,0xffff0750
+ 750: f8 e0 02 80 bgei \$0,0xf,0xffff0754
+ 754: f0 ef 02 80 beqi \$sp,0xf,0xffff0758
+ 758: f4 ef 02 80 bnei \$sp,0xf,0xffff075c
+ 75c: fc ef 02 80 blti \$sp,0xf,0xffff0760
+ 760: f8 ef 02 80 bgei \$sp,0xf,0xffff0764
+ 764: 00 e0 ff 3f beqi \$0,0x0,0x8762
+ 768: 04 e0 ff 3f bnei \$0,0x0,0x8766
+ 76c: 0c e0 ff 3f blti \$0,0x0,0x876a
+ 770: 08 e0 ff 3f bgei \$0,0x0,0x876e
+ 774: 00 ef ff 3f beqi \$sp,0x0,0x8772
+ 778: 04 ef ff 3f bnei \$sp,0x0,0x8776
+ 77c: 0c ef ff 3f blti \$sp,0x0,0x877a
+ 780: 08 ef ff 3f bgei \$sp,0x0,0x877e
+ 784: f0 e0 ff 3f beqi \$0,0xf,0x8782
+ 788: f4 e0 ff 3f bnei \$0,0xf,0x8786
+ 78c: fc e0 ff 3f blti \$0,0xf,0x878a
+ 790: f8 e0 ff 3f bgei \$0,0xf,0x878e
+ 794: f0 ef ff 3f beqi \$sp,0xf,0x8792
+ 798: f4 ef ff 3f bnei \$sp,0xf,0x8796
+ 79c: fc ef ff 3f blti \$sp,0xf,0x879a
+ 7a0: f8 ef ff 3f bgei \$sp,0xf,0x879e
+ 7a4: 00 e0 00 00 beqi \$0,0x0,0x7a4
+ 7a4: R_MEP_PCREL17A2 symbol
+ 7a8: 04 e0 00 00 bnei \$0,0x0,0x7a8
+ 7a8: R_MEP_PCREL17A2 symbol
+ 7ac: 0c e0 00 00 blti \$0,0x0,0x7ac
+ 7ac: R_MEP_PCREL17A2 symbol
+ 7b0: 08 e0 00 00 bgei \$0,0x0,0x7b0
+ 7b0: R_MEP_PCREL17A2 symbol
+ 7b4: 00 ef 00 00 beqi \$sp,0x0,0x7b4
+ 7b4: R_MEP_PCREL17A2 symbol
+ 7b8: 04 ef 00 00 bnei \$sp,0x0,0x7b8
+ 7b8: R_MEP_PCREL17A2 symbol
+ 7bc: 0c ef 00 00 blti \$sp,0x0,0x7bc
+ 7bc: R_MEP_PCREL17A2 symbol
+ 7c0: 08 ef 00 00 bgei \$sp,0x0,0x7c0
+ 7c0: R_MEP_PCREL17A2 symbol
+ 7c4: f0 e0 00 00 beqi \$0,0xf,0x7c4
+ 7c4: R_MEP_PCREL17A2 symbol
+ 7c8: f4 e0 00 00 bnei \$0,0xf,0x7c8
+ 7c8: R_MEP_PCREL17A2 symbol
+ 7cc: fc e0 00 00 blti \$0,0xf,0x7cc
+ 7cc: R_MEP_PCREL17A2 symbol
+ 7d0: f8 e0 00 00 bgei \$0,0xf,0x7d0
+ 7d0: R_MEP_PCREL17A2 symbol
+ 7d4: f0 ef 00 00 beqi \$sp,0xf,0x7d4
+ 7d4: R_MEP_PCREL17A2 symbol
+ 7d8: f4 ef 00 00 bnei \$sp,0xf,0x7d8
+ 7d8: R_MEP_PCREL17A2 symbol
+ 7dc: fc ef 00 00 blti \$sp,0xf,0x7dc
+ 7dc: R_MEP_PCREL17A2 symbol
+ 7e0: f8 ef 00 00 bgei \$sp,0xf,0x7e0
+ 7e0: R_MEP_PCREL17A2 symbol
+ 7e4: 01 e0 02 80 beq \$0,\$0,0xffff07e8
+ 7e8: 05 e0 02 80 bne \$0,\$0,0xffff07ec
+ 7ec: 01 ef 02 80 beq \$sp,\$0,0xffff07f0
+ 7f0: 05 ef 02 80 bne \$sp,\$0,0xffff07f4
+ 7f4: f1 e0 02 80 beq \$0,\$sp,0xffff07f8
+ 7f8: f5 e0 02 80 bne \$0,\$sp,0xffff07fc
+ 7fc: f1 ef 02 80 beq \$sp,\$sp,0xffff0800
+ 800: f5 ef 02 80 bne \$sp,\$sp,0xffff0804
+ 804: 01 e0 ff 3f beq \$0,\$0,0x8802
+ 808: 05 e0 ff 3f bne \$0,\$0,0x8806
+ 80c: 01 ef ff 3f beq \$sp,\$0,0x880a
+ 810: 05 ef ff 3f bne \$sp,\$0,0x880e
+ 814: f1 e0 ff 3f beq \$0,\$sp,0x8812
+ 818: f5 e0 ff 3f bne \$0,\$sp,0x8816
+ 81c: f1 ef ff 3f beq \$sp,\$sp,0x881a
+ 820: f5 ef ff 3f bne \$sp,\$sp,0x881e
+ 824: 01 e0 00 00 beq \$0,\$0,0x824
+ 824: R_MEP_PCREL17A2 symbol
+ 828: 05 e0 00 00 bne \$0,\$0,0x828
+ 828: R_MEP_PCREL17A2 symbol
+ 82c: 01 ef 00 00 beq \$sp,\$0,0x82c
+ 82c: R_MEP_PCREL17A2 symbol
+ 830: 05 ef 00 00 bne \$sp,\$0,0x830
+ 830: R_MEP_PCREL17A2 symbol
+ 834: f1 e0 00 00 beq \$0,\$sp,0x834
+ 834: R_MEP_PCREL17A2 symbol
+ 838: f5 e0 00 00 bne \$0,\$sp,0x838
+ 838: R_MEP_PCREL17A2 symbol
+ 83c: f1 ef 00 00 beq \$sp,\$sp,0x83c
+ 83c: R_MEP_PCREL17A2 symbol
+ 840: f5 ef 00 00 bne \$sp,\$sp,0x840
+ 840: R_MEP_PCREL17A2 symbol
+ 844: 29 d8 00 80 bsr 0xff800848
+ 848: 03 b8 bsr 0x4a
+ 84a: 09 d8 08 00 bsr 0x104a
+ 84e: 19 d8 00 80 bsr 0xff800850
+ 852: 09 d8 00 00 bsr 0x852
+ 852: R_MEP_PCREL24A2 symbol
+ 856: 0e 10 jmp \$0
+ 858: fe 10 jmp \$sp
+ 85a: 08 d8 00 00 jmp 0x0
+ 85e: f8 df ff ff jmp 0xfffffe
+ 862: 08 d8 00 00 jmp 0x0
+ 862: R_MEP_PCABS24A2 symbol
+ 866: 0f 10 jsr \$0
+ 868: ff 10 jsr \$sp
+ 86a: 02 70 ret
+ 86c: 09 e0 02 80 repeat \$0,0xffff0870
+ 870: 09 ef 02 80 repeat \$sp,0xffff0874
+ 874: 09 e0 ff 3f repeat \$0,0x8872
+ 878: 09 ef ff 3f repeat \$sp,0x8876
+ 87c: 09 e0 00 00 repeat \$0,0x87c
+ 87c: R_MEP_PCREL17A2 symbol
+ 880: 09 ef 00 00 repeat \$sp,0x880
+ 880: R_MEP_PCREL17A2 symbol
+ 884: 19 e0 02 80 erepeat 0xffff0888
+ 888: 19 e0 ff 3f erepeat 0x8886
+ 88c: 19 e0 00 00 erepeat 0x88c
+ 88c: R_MEP_PCREL17A2 symbol
+ 890: 08 70 stc \$0,\$pc
+ 892: 0a 70 ldc \$0,\$pc
+ 894: 08 7f stc \$sp,\$pc
+ 896: 0a 7f ldc \$sp,\$pc
+ 898: 18 70 stc \$0,\$lp
+ 89a: 1a 70 ldc \$0,\$lp
+ 89c: 18 7f stc \$sp,\$lp
+ 89e: 1a 7f ldc \$sp,\$lp
+ 8a0: 28 70 stc \$0,\$sar
+ 8a2: 2a 70 ldc \$0,\$sar
+ 8a4: 28 7f stc \$sp,\$sar
+ 8a6: 2a 7f ldc \$sp,\$sar
+ 8a8: 48 70 stc \$0,\$rpb
+ 8aa: 4a 70 ldc \$0,\$rpb
+ 8ac: 48 7f stc \$sp,\$rpb
+ 8ae: 4a 7f ldc \$sp,\$rpb
+ 8b0: 58 70 stc \$0,\$rpe
+ 8b2: 5a 70 ldc \$0,\$rpe
+ 8b4: 58 7f stc \$sp,\$rpe
+ 8b6: 5a 7f ldc \$sp,\$rpe
+ 8b8: 68 70 stc \$0,\$rpc
+ 8ba: 6a 70 ldc \$0,\$rpc
+ 8bc: 68 7f stc \$sp,\$rpc
+ 8be: 6a 7f ldc \$sp,\$rpc
+ 8c0: 78 70 stc \$0,\$hi
+ 8c2: 7a 70 ldc \$0,\$hi
+ 8c4: 78 7f stc \$sp,\$hi
+ 8c6: 7a 7f ldc \$sp,\$hi
+ 8c8: 88 70 stc \$0,\$lo
+ 8ca: 8a 70 ldc \$0,\$lo
+ 8cc: 88 7f stc \$sp,\$lo
+ 8ce: 8a 7f ldc \$sp,\$lo
+ 8d0: c8 70 stc \$0,\$mb0
+ 8d2: ca 70 ldc \$0,\$mb0
+ 8d4: c8 7f stc \$sp,\$mb0
+ 8d6: ca 7f ldc \$sp,\$mb0
+ 8d8: d8 70 stc \$0,\$me0
+ 8da: da 70 ldc \$0,\$me0
+ 8dc: d8 7f stc \$sp,\$me0
+ 8de: da 7f ldc \$sp,\$me0
+ 8e0: e8 70 stc \$0,\$mb1
+ 8e2: ea 70 ldc \$0,\$mb1
+ 8e4: e8 7f stc \$sp,\$mb1
+ 8e6: ea 7f ldc \$sp,\$mb1
+ 8e8: f8 70 stc \$0,\$me1
+ 8ea: fa 70 ldc \$0,\$me1
+ 8ec: f8 7f stc \$sp,\$me1
+ 8ee: fa 7f ldc \$sp,\$me1
+ 8f0: 09 70 stc \$0,\$psw
+ 8f2: 0b 70 ldc \$0,\$psw
+ 8f4: 09 7f stc \$sp,\$psw
+ 8f6: 0b 7f ldc \$sp,\$psw
+ 8f8: 19 70 stc \$0,\$id
+ 8fa: 1b 70 ldc \$0,\$id
+ 8fc: 19 7f stc \$sp,\$id
+ 8fe: 1b 7f ldc \$sp,\$id
+ 900: 29 70 stc \$0,\$tmp
+ 902: 2b 70 ldc \$0,\$tmp
+ 904: 29 7f stc \$sp,\$tmp
+ 906: 2b 7f ldc \$sp,\$tmp
+ 908: 39 70 stc \$0,\$epc
+ 90a: 3b 70 ldc \$0,\$epc
+ 90c: 39 7f stc \$sp,\$epc
+ 90e: 3b 7f ldc \$sp,\$epc
+ 910: 49 70 stc \$0,\$exc
+ 912: 4b 70 ldc \$0,\$exc
+ 914: 49 7f stc \$sp,\$exc
+ 916: 4b 7f ldc \$sp,\$exc
+ 918: 59 70 stc \$0,\$cfg
+ 91a: 5b 70 ldc \$0,\$cfg
+ 91c: 59 7f stc \$sp,\$cfg
+ 91e: 5b 7f ldc \$sp,\$cfg
+ 920: 79 70 stc \$0,\$npc
+ 922: 7b 70 ldc \$0,\$npc
+ 924: 79 7f stc \$sp,\$npc
+ 926: 7b 7f ldc \$sp,\$npc
+ 928: 89 70 stc \$0,\$dbg
+ 92a: 8b 70 ldc \$0,\$dbg
+ 92c: 89 7f stc \$sp,\$dbg
+ 92e: 8b 7f ldc \$sp,\$dbg
+ 930: 99 70 stc \$0,\$depc
+ 932: 9b 70 ldc \$0,\$depc
+ 934: 99 7f stc \$sp,\$depc
+ 936: 9b 7f ldc \$sp,\$depc
+ 938: a9 70 stc \$0,\$opt
+ 93a: ab 70 ldc \$0,\$opt
+ 93c: a9 7f stc \$sp,\$opt
+ 93e: ab 7f ldc \$sp,\$opt
+ 940: b9 70 stc \$0,\$rcfg
+ 942: bb 70 ldc \$0,\$rcfg
+ 944: b9 7f stc \$sp,\$rcfg
+ 946: bb 7f ldc \$sp,\$rcfg
+ 948: c9 70 stc \$0,\$ccfg
+ 94a: cb 70 ldc \$0,\$ccfg
+ 94c: c9 7f stc \$sp,\$ccfg
+ 94e: cb 7f ldc \$sp,\$ccfg
+ 950: 00 70 di
+ 952: 10 70 ei
+ 954: 12 70 reti
+ 956: 22 70 halt
+ 958: 32 70 break
+ 95a: 11 70 syncm
+ 95c: 06 70 swi 0x0
+ 95e: 36 70 swi 0x3
+ 960: 04 f0 00 00 stcb \$0,0x0
+ 964: 14 f0 00 00 ldcb \$0,0x0
+ 968: 04 ff 00 00 stcb \$sp,0x0
+ 96c: 14 ff 00 00 ldcb \$sp,0x0
+ 970: 04 f0 ff ff stcb \$0,0xffff
+ 974: 14 f0 ff ff ldcb \$0,0xffff
+ 978: 04 ff ff ff stcb \$sp,0xffff
+ 97c: 14 ff ff ff ldcb \$sp,0xffff
+ 980: 04 f0 00 00 stcb \$0,0x0
+ 982: R_MEP_16 symbol
+ 984: 14 f0 00 00 ldcb \$0,0x0
+ 986: R_MEP_16 symbol
+ 988: 04 ff 00 00 stcb \$sp,0x0
+ 98a: R_MEP_16 symbol
+ 98c: 14 ff 00 00 ldcb \$sp,0x0
+ 98e: R_MEP_16 symbol
+ 990: 00 20 bsetm \(\$0\),0x0
+ 992: 01 20 bclrm \(\$0\),0x0
+ 994: 02 20 bnotm \(\$0\),0x0
+ 996: f0 20 bsetm \(\$sp\),0x0
+ 998: f1 20 bclrm \(\$sp\),0x0
+ 99a: f2 20 bnotm \(\$sp\),0x0
+ 99c: 00 27 bsetm \(\$0\),0x7
+ 99e: 01 27 bclrm \(\$0\),0x7
+ 9a0: 02 27 bnotm \(\$0\),0x7
+ 9a2: f0 27 bsetm \(\$sp\),0x7
+ 9a4: f1 27 bclrm \(\$sp\),0x7
+ 9a6: f2 27 bnotm \(\$sp\),0x7
+ 9a8: 03 20 btstm \$0,\(\$0\),0x0
+ 9aa: f3 20 btstm \$0,\(\$sp\),0x0
+ 9ac: 03 27 btstm \$0,\(\$0\),0x7
+ 9ae: f3 27 btstm \$0,\(\$sp\),0x7
+ 9b0: 04 20 tas \$0,\(\$0\)
+ 9b2: 04 2f tas \$sp,\(\$0\)
+ 9b4: f4 20 tas \$0,\(\$sp\)
+ 9b6: f4 2f tas \$sp,\(\$sp\)
+ 9b8: 04 70 cache 0x0,\(\$0\)
+ 9ba: 04 73 cache 0x3,\(\$0\)
+ 9bc: f4 70 cache 0x0,\(\$sp\)
+ 9be: f4 73 cache 0x3,\(\$sp\)
+ 9c0: 04 10 mul \$0,\$0
+ 9c2: 01 f0 04 30 madd \$0,\$0
+ 9c6: 06 10 mulr \$0,\$0
+ 9c8: 01 f0 06 30 maddr \$0,\$0
+ 9cc: 05 10 mulu \$0,\$0
+ 9ce: 01 f0 05 30 maddu \$0,\$0
+ 9d2: 07 10 mulru \$0,\$0
+ 9d4: 01 f0 07 30 maddru \$0,\$0
+ 9d8: 04 1f mul \$sp,\$0
+ 9da: 01 ff 04 30 madd \$sp,\$0
+ 9de: 06 1f mulr \$sp,\$0
+ 9e0: 01 ff 06 30 maddr \$sp,\$0
+ 9e4: 05 1f mulu \$sp,\$0
+ 9e6: 01 ff 05 30 maddu \$sp,\$0
+ 9ea: 07 1f mulru \$sp,\$0
+ 9ec: 01 ff 07 30 maddru \$sp,\$0
+ 9f0: f4 10 mul \$0,\$sp
+ 9f2: f1 f0 04 30 madd \$0,\$sp
+ 9f6: f6 10 mulr \$0,\$sp
+ 9f8: f1 f0 06 30 maddr \$0,\$sp
+ 9fc: f5 10 mulu \$0,\$sp
+ 9fe: f1 f0 05 30 maddu \$0,\$sp
+ a02: f7 10 mulru \$0,\$sp
+ a04: f1 f0 07 30 maddru \$0,\$sp
+ a08: f4 1f mul \$sp,\$sp
+ a0a: f1 ff 04 30 madd \$sp,\$sp
+ a0e: f6 1f mulr \$sp,\$sp
+ a10: f1 ff 06 30 maddr \$sp,\$sp
+ a14: f5 1f mulu \$sp,\$sp
+ a16: f1 ff 05 30 maddu \$sp,\$sp
+ a1a: f7 1f mulru \$sp,\$sp
+ a1c: f1 ff 07 30 maddru \$sp,\$sp
+ a20: 08 10 div \$0,\$0
+ a22: 09 10 divu \$0,\$0
+ a24: 08 1f div \$sp,\$0
+ a26: 09 1f divu \$sp,\$0
+ a28: f8 10 div \$0,\$sp
+ a2a: f9 10 divu \$0,\$sp
+ a2c: f8 1f div \$sp,\$sp
+ a2e: f9 1f divu \$sp,\$sp
+ a30: 13 70 dret
+ a32: 33 70 dbreak
+ a34: 01 f0 00 00 ldz \$0,\$0
+ a38: 01 f0 03 00 abs \$0,\$0
+ a3c: 01 f0 02 00 ave \$0,\$0
+ a40: 01 ff 00 00 ldz \$sp,\$0
+ a44: 01 ff 03 00 abs \$sp,\$0
+ a48: 01 ff 02 00 ave \$sp,\$0
+ a4c: f1 f0 00 00 ldz \$0,\$sp
+ a50: f1 f0 03 00 abs \$0,\$sp
+ a54: f1 f0 02 00 ave \$0,\$sp
+ a58: f1 ff 00 00 ldz \$sp,\$sp
+ a5c: f1 ff 03 00 abs \$sp,\$sp
+ a60: f1 ff 02 00 ave \$sp,\$sp
+ a64: 01 f0 04 00 min \$0,\$0
+ a68: 01 f0 05 00 max \$0,\$0
+ a6c: 01 f0 06 00 minu \$0,\$0
+ a70: 01 f0 07 00 maxu \$0,\$0
+ a74: 01 ff 04 00 min \$sp,\$0
+ a78: 01 ff 05 00 max \$sp,\$0
+ a7c: 01 ff 06 00 minu \$sp,\$0
+ a80: 01 ff 07 00 maxu \$sp,\$0
+ a84: f1 f0 04 00 min \$0,\$sp
+ a88: f1 f0 05 00 max \$0,\$sp
+ a8c: f1 f0 06 00 minu \$0,\$sp
+ a90: f1 f0 07 00 maxu \$0,\$sp
+ a94: f1 ff 04 00 min \$sp,\$sp
+ a98: f1 ff 05 00 max \$sp,\$sp
+ a9c: f1 ff 06 00 minu \$sp,\$sp
+ aa0: f1 ff 07 00 maxu \$sp,\$sp
+ aa4: 01 f0 00 10 clip \$0,0x0
+ aa8: 01 f0 01 10 clipu \$0,0x0
+ aac: 01 ff 00 10 clip \$sp,0x0
+ ab0: 01 ff 01 10 clipu \$sp,0x0
+ ab4: 01 f0 f8 10 clip \$0,0x1f
+ ab8: 01 f0 f9 10 clipu \$0,0x1f
+ abc: 01 ff f8 10 clip \$sp,0x1f
+ ac0: 01 ff f9 10 clipu \$sp,0x1f
+ ac4: 01 f0 08 00 sadd \$0,\$0
+ ac8: 01 f0 0a 00 ssub \$0,\$0
+ acc: 01 f0 09 00 saddu \$0,\$0
+ ad0: 01 f0 0b 00 ssubu \$0,\$0
+ ad4: 01 ff 08 00 sadd \$sp,\$0
+ ad8: 01 ff 0a 00 ssub \$sp,\$0
+ adc: 01 ff 09 00 saddu \$sp,\$0
+ ae0: 01 ff 0b 00 ssubu \$sp,\$0
+ ae4: f1 f0 08 00 sadd \$0,\$sp
+ ae8: f1 f0 0a 00 ssub \$0,\$sp
+ aec: f1 f0 09 00 saddu \$0,\$sp
+ af0: f1 f0 0b 00 ssubu \$0,\$sp
+ af4: f1 ff 08 00 sadd \$sp,\$sp
+ af8: f1 ff 0a 00 ssub \$sp,\$sp
+ afc: f1 ff 09 00 saddu \$sp,\$sp
+ b00: f1 ff 0b 00 ssubu \$sp,\$sp
+ b04: 08 30 swcp \$c0,\(\$0\)
+ b06: 09 30 lwcp \$c0,\(\$0\)
+ b08: 0a 30 smcp \$c0,\(\$0\)
+ b0a: 0b 30 lmcp \$c0,\(\$0\)
+ b0c: 08 3f swcp \$c15,\(\$0\)
+ b0e: 09 3f lwcp \$c15,\(\$0\)
+ b10: 0a 3f smcp \$c15,\(\$0\)
+ b12: 0b 3f lmcp \$c15,\(\$0\)
+ b14: f8 30 swcp \$c0,\(\$sp\)
+ b16: f9 30 lwcp \$c0,\(\$sp\)
+ b18: fa 30 smcp \$c0,\(\$sp\)
+ b1a: fb 30 lmcp \$c0,\(\$sp\)
+ b1c: f8 3f swcp \$c15,\(\$sp\)
+ b1e: f9 3f lwcp \$c15,\(\$sp\)
+ b20: fa 3f smcp \$c15,\(\$sp\)
+ b22: fb 3f lmcp \$c15,\(\$sp\)
+ b24: 00 30 swcpi \$c0,\(\$0\+\)
+ b26: 01 30 lwcpi \$c0,\(\$0\+\)
+ b28: 02 30 smcpi \$c0,\(\$0\+\)
+ b2a: 03 30 lmcpi \$c0,\(\$0\+\)
+ b2c: 00 3f swcpi \$c15,\(\$0\+\)
+ b2e: 01 3f lwcpi \$c15,\(\$0\+\)
+ b30: 02 3f smcpi \$c15,\(\$0\+\)
+ b32: 03 3f lmcpi \$c15,\(\$0\+\)
+ b34: f0 30 swcpi \$c0,\(\$sp\+\)
+ b36: f1 30 lwcpi \$c0,\(\$sp\+\)
+ b38: f2 30 smcpi \$c0,\(\$sp\+\)
+ b3a: f3 30 lmcpi \$c0,\(\$sp\+\)
+ b3c: f0 3f swcpi \$c15,\(\$sp\+\)
+ b3e: f1 3f lwcpi \$c15,\(\$sp\+\)
+ b40: f2 3f smcpi \$c15,\(\$sp\+\)
+ b42: f3 3f lmcpi \$c15,\(\$sp\+\)
+ b44: 05 f0 80 00 sbcpa \$c0,\(\$0\+\),-128
+ b48: 05 f0 80 40 lbcpa \$c0,\(\$0\+\),-128
+ b4c: 05 f0 80 08 sbcpm0 \$c0,\(\$0\+\),-128
+ b50: 05 f0 80 48 lbcpm0 \$c0,\(\$0\+\),-128
+ b54: 05 f0 80 0c sbcpm1 \$c0,\(\$0\+\),-128
+ b58: 05 f0 80 4c lbcpm1 \$c0,\(\$0\+\),-128
+ b5c: 05 ff 80 00 sbcpa \$c15,\(\$0\+\),-128
+ b60: 05 ff 80 40 lbcpa \$c15,\(\$0\+\),-128
+ b64: 05 ff 80 08 sbcpm0 \$c15,\(\$0\+\),-128
+ b68: 05 ff 80 48 lbcpm0 \$c15,\(\$0\+\),-128
+ b6c: 05 ff 80 0c sbcpm1 \$c15,\(\$0\+\),-128
+ b70: 05 ff 80 4c lbcpm1 \$c15,\(\$0\+\),-128
+ b74: f5 f0 80 00 sbcpa \$c0,\(\$sp\+\),-128
+ b78: f5 f0 80 40 lbcpa \$c0,\(\$sp\+\),-128
+ b7c: f5 f0 80 08 sbcpm0 \$c0,\(\$sp\+\),-128
+ b80: f5 f0 80 48 lbcpm0 \$c0,\(\$sp\+\),-128
+ b84: f5 f0 80 0c sbcpm1 \$c0,\(\$sp\+\),-128
+ b88: f5 f0 80 4c lbcpm1 \$c0,\(\$sp\+\),-128
+ b8c: f5 ff 80 00 sbcpa \$c15,\(\$sp\+\),-128
+ b90: f5 ff 80 40 lbcpa \$c15,\(\$sp\+\),-128
+ b94: f5 ff 80 08 sbcpm0 \$c15,\(\$sp\+\),-128
+ b98: f5 ff 80 48 lbcpm0 \$c15,\(\$sp\+\),-128
+ b9c: f5 ff 80 0c sbcpm1 \$c15,\(\$sp\+\),-128
+ ba0: f5 ff 80 4c lbcpm1 \$c15,\(\$sp\+\),-128
+ ba4: 05 f0 7f 00 sbcpa \$c0,\(\$0\+\),127
+ ba8: 05 f0 7f 40 lbcpa \$c0,\(\$0\+\),127
+ bac: 05 f0 7f 08 sbcpm0 \$c0,\(\$0\+\),127
+ bb0: 05 f0 7f 48 lbcpm0 \$c0,\(\$0\+\),127
+ bb4: 05 f0 7f 0c sbcpm1 \$c0,\(\$0\+\),127
+ bb8: 05 f0 7f 4c lbcpm1 \$c0,\(\$0\+\),127
+ bbc: 05 ff 7f 00 sbcpa \$c15,\(\$0\+\),127
+ bc0: 05 ff 7f 40 lbcpa \$c15,\(\$0\+\),127
+ bc4: 05 ff 7f 08 sbcpm0 \$c15,\(\$0\+\),127
+ bc8: 05 ff 7f 48 lbcpm0 \$c15,\(\$0\+\),127
+ bcc: 05 ff 7f 0c sbcpm1 \$c15,\(\$0\+\),127
+ bd0: 05 ff 7f 4c lbcpm1 \$c15,\(\$0\+\),127
+ bd4: f5 f0 7f 00 sbcpa \$c0,\(\$sp\+\),127
+ bd8: f5 f0 7f 40 lbcpa \$c0,\(\$sp\+\),127
+ bdc: f5 f0 7f 08 sbcpm0 \$c0,\(\$sp\+\),127
+ be0: f5 f0 7f 48 lbcpm0 \$c0,\(\$sp\+\),127
+ be4: f5 f0 7f 0c sbcpm1 \$c0,\(\$sp\+\),127
+ be8: f5 f0 7f 4c lbcpm1 \$c0,\(\$sp\+\),127
+ bec: f5 ff 7f 00 sbcpa \$c15,\(\$sp\+\),127
+ bf0: f5 ff 7f 40 lbcpa \$c15,\(\$sp\+\),127
+ bf4: f5 ff 7f 08 sbcpm0 \$c15,\(\$sp\+\),127
+ bf8: f5 ff 7f 48 lbcpm0 \$c15,\(\$sp\+\),127
+ bfc: f5 ff 7f 0c sbcpm1 \$c15,\(\$sp\+\),127
+ c00: f5 ff 7f 4c lbcpm1 \$c15,\(\$sp\+\),127
+ c04: 05 f0 80 10 shcpa \$c0,\(\$0\+\),-128
+ c08: 05 f0 80 50 lhcpa \$c0,\(\$0\+\),-128
+ c0c: 05 f0 80 18 shcpm0 \$c0,\(\$0\+\),-128
+ c10: 05 f0 80 58 lhcpm0 \$c0,\(\$0\+\),-128
+ c14: 05 f0 80 1c shcpm1 \$c0,\(\$0\+\),-128
+ c18: 05 f0 80 5c lhcpm1 \$c0,\(\$0\+\),-128
+ c1c: 05 ff 80 10 shcpa \$c15,\(\$0\+\),-128
+ c20: 05 ff 80 50 lhcpa \$c15,\(\$0\+\),-128
+ c24: 05 ff 80 18 shcpm0 \$c15,\(\$0\+\),-128
+ c28: 05 ff 80 58 lhcpm0 \$c15,\(\$0\+\),-128
+ c2c: 05 ff 80 1c shcpm1 \$c15,\(\$0\+\),-128
+ c30: 05 ff 80 5c lhcpm1 \$c15,\(\$0\+\),-128
+ c34: f5 f0 80 10 shcpa \$c0,\(\$sp\+\),-128
+ c38: f5 f0 80 50 lhcpa \$c0,\(\$sp\+\),-128
+ c3c: f5 f0 80 18 shcpm0 \$c0,\(\$sp\+\),-128
+ c40: f5 f0 80 58 lhcpm0 \$c0,\(\$sp\+\),-128
+ c44: f5 f0 80 1c shcpm1 \$c0,\(\$sp\+\),-128
+ c48: f5 f0 80 5c lhcpm1 \$c0,\(\$sp\+\),-128
+ c4c: f5 ff 80 10 shcpa \$c15,\(\$sp\+\),-128
+ c50: f5 ff 80 50 lhcpa \$c15,\(\$sp\+\),-128
+ c54: f5 ff 80 18 shcpm0 \$c15,\(\$sp\+\),-128
+ c58: f5 ff 80 58 lhcpm0 \$c15,\(\$sp\+\),-128
+ c5c: f5 ff 80 1c shcpm1 \$c15,\(\$sp\+\),-128
+ c60: f5 ff 80 5c lhcpm1 \$c15,\(\$sp\+\),-128
+ c64: 05 f0 7e 10 shcpa \$c0,\(\$0\+\),126
+ c68: 05 f0 7e 50 lhcpa \$c0,\(\$0\+\),126
+ c6c: 05 f0 7e 18 shcpm0 \$c0,\(\$0\+\),126
+ c70: 05 f0 7e 58 lhcpm0 \$c0,\(\$0\+\),126
+ c74: 05 f0 7e 1c shcpm1 \$c0,\(\$0\+\),126
+ c78: 05 f0 7e 5c lhcpm1 \$c0,\(\$0\+\),126
+ c7c: 05 ff 7e 10 shcpa \$c15,\(\$0\+\),126
+ c80: 05 ff 7e 50 lhcpa \$c15,\(\$0\+\),126
+ c84: 05 ff 7e 18 shcpm0 \$c15,\(\$0\+\),126
+ c88: 05 ff 7e 58 lhcpm0 \$c15,\(\$0\+\),126
+ c8c: 05 ff 7e 1c shcpm1 \$c15,\(\$0\+\),126
+ c90: 05 ff 7e 5c lhcpm1 \$c15,\(\$0\+\),126
+ c94: f5 f0 7e 10 shcpa \$c0,\(\$sp\+\),126
+ c98: f5 f0 7e 50 lhcpa \$c0,\(\$sp\+\),126
+ c9c: f5 f0 7e 18 shcpm0 \$c0,\(\$sp\+\),126
+ ca0: f5 f0 7e 58 lhcpm0 \$c0,\(\$sp\+\),126
+ ca4: f5 f0 7e 1c shcpm1 \$c0,\(\$sp\+\),126
+ ca8: f5 f0 7e 5c lhcpm1 \$c0,\(\$sp\+\),126
+ cac: f5 ff 7e 10 shcpa \$c15,\(\$sp\+\),126
+ cb0: f5 ff 7e 50 lhcpa \$c15,\(\$sp\+\),126
+ cb4: f5 ff 7e 18 shcpm0 \$c15,\(\$sp\+\),126
+ cb8: f5 ff 7e 58 lhcpm0 \$c15,\(\$sp\+\),126
+ cbc: f5 ff 7e 1c shcpm1 \$c15,\(\$sp\+\),126
+ cc0: f5 ff 7e 5c lhcpm1 \$c15,\(\$sp\+\),126
+ cc4: 05 f0 80 20 swcpa \$c0,\(\$0\+\),-128
+ cc8: 05 f0 80 60 lwcpa \$c0,\(\$0\+\),-128
+ ccc: 05 f0 80 28 swcpm0 \$c0,\(\$0\+\),-128
+ cd0: 05 f0 80 68 lwcpm0 \$c0,\(\$0\+\),-128
+ cd4: 05 f0 80 2c swcpm1 \$c0,\(\$0\+\),-128
+ cd8: 05 f0 80 6c lwcpm1 \$c0,\(\$0\+\),-128
+ cdc: 05 ff 80 20 swcpa \$c15,\(\$0\+\),-128
+ ce0: 05 ff 80 60 lwcpa \$c15,\(\$0\+\),-128
+ ce4: 05 ff 80 28 swcpm0 \$c15,\(\$0\+\),-128
+ ce8: 05 ff 80 68 lwcpm0 \$c15,\(\$0\+\),-128
+ cec: 05 ff 80 2c swcpm1 \$c15,\(\$0\+\),-128
+ cf0: 05 ff 80 6c lwcpm1 \$c15,\(\$0\+\),-128
+ cf4: f5 f0 80 20 swcpa \$c0,\(\$sp\+\),-128
+ cf8: f5 f0 80 60 lwcpa \$c0,\(\$sp\+\),-128
+ cfc: f5 f0 80 28 swcpm0 \$c0,\(\$sp\+\),-128
+ d00: f5 f0 80 68 lwcpm0 \$c0,\(\$sp\+\),-128
+ d04: f5 f0 80 2c swcpm1 \$c0,\(\$sp\+\),-128
+ d08: f5 f0 80 6c lwcpm1 \$c0,\(\$sp\+\),-128
+ d0c: f5 ff 80 20 swcpa \$c15,\(\$sp\+\),-128
+ d10: f5 ff 80 60 lwcpa \$c15,\(\$sp\+\),-128
+ d14: f5 ff 80 28 swcpm0 \$c15,\(\$sp\+\),-128
+ d18: f5 ff 80 68 lwcpm0 \$c15,\(\$sp\+\),-128
+ d1c: f5 ff 80 2c swcpm1 \$c15,\(\$sp\+\),-128
+ d20: f5 ff 80 6c lwcpm1 \$c15,\(\$sp\+\),-128
+ d24: 05 f0 7c 20 swcpa \$c0,\(\$0\+\),124
+ d28: 05 f0 7c 60 lwcpa \$c0,\(\$0\+\),124
+ d2c: 05 f0 7c 28 swcpm0 \$c0,\(\$0\+\),124
+ d30: 05 f0 7c 68 lwcpm0 \$c0,\(\$0\+\),124
+ d34: 05 f0 7c 2c swcpm1 \$c0,\(\$0\+\),124
+ d38: 05 f0 7c 6c lwcpm1 \$c0,\(\$0\+\),124
+ d3c: 05 ff 7c 20 swcpa \$c15,\(\$0\+\),124
+ d40: 05 ff 7c 60 lwcpa \$c15,\(\$0\+\),124
+ d44: 05 ff 7c 28 swcpm0 \$c15,\(\$0\+\),124
+ d48: 05 ff 7c 68 lwcpm0 \$c15,\(\$0\+\),124
+ d4c: 05 ff 7c 2c swcpm1 \$c15,\(\$0\+\),124
+ d50: 05 ff 7c 6c lwcpm1 \$c15,\(\$0\+\),124
+ d54: f5 f0 7c 20 swcpa \$c0,\(\$sp\+\),124
+ d58: f5 f0 7c 60 lwcpa \$c0,\(\$sp\+\),124
+ d5c: f5 f0 7c 28 swcpm0 \$c0,\(\$sp\+\),124
+ d60: f5 f0 7c 68 lwcpm0 \$c0,\(\$sp\+\),124
+ d64: f5 f0 7c 2c swcpm1 \$c0,\(\$sp\+\),124
+ d68: f5 f0 7c 6c lwcpm1 \$c0,\(\$sp\+\),124
+ d6c: f5 ff 7c 20 swcpa \$c15,\(\$sp\+\),124
+ d70: f5 ff 7c 60 lwcpa \$c15,\(\$sp\+\),124
+ d74: f5 ff 7c 28 swcpm0 \$c15,\(\$sp\+\),124
+ d78: f5 ff 7c 68 lwcpm0 \$c15,\(\$sp\+\),124
+ d7c: f5 ff 7c 2c swcpm1 \$c15,\(\$sp\+\),124
+ d80: f5 ff 7c 6c lwcpm1 \$c15,\(\$sp\+\),124
+ d84: 05 f0 80 30 smcpa \$c0,\(\$0\+\),-128
+ d88: 05 f0 80 70 lmcpa \$c0,\(\$0\+\),-128
+ d8c: 05 f0 80 38 smcpm0 \$c0,\(\$0\+\),-128
+ d90: 05 f0 80 78 lmcpm0 \$c0,\(\$0\+\),-128
+ d94: 05 f0 80 3c smcpm1 \$c0,\(\$0\+\),-128
+ d98: 05 f0 80 7c lmcpm1 \$c0,\(\$0\+\),-128
+ d9c: 05 ff 80 30 smcpa \$c15,\(\$0\+\),-128
+ da0: 05 ff 80 70 lmcpa \$c15,\(\$0\+\),-128
+ da4: 05 ff 80 38 smcpm0 \$c15,\(\$0\+\),-128
+ da8: 05 ff 80 78 lmcpm0 \$c15,\(\$0\+\),-128
+ dac: 05 ff 80 3c smcpm1 \$c15,\(\$0\+\),-128
+ db0: 05 ff 80 7c lmcpm1 \$c15,\(\$0\+\),-128
+ db4: f5 f0 80 30 smcpa \$c0,\(\$sp\+\),-128
+ db8: f5 f0 80 70 lmcpa \$c0,\(\$sp\+\),-128
+ dbc: f5 f0 80 38 smcpm0 \$c0,\(\$sp\+\),-128
+ dc0: f5 f0 80 78 lmcpm0 \$c0,\(\$sp\+\),-128
+ dc4: f5 f0 80 3c smcpm1 \$c0,\(\$sp\+\),-128
+ dc8: f5 f0 80 7c lmcpm1 \$c0,\(\$sp\+\),-128
+ dcc: f5 ff 80 30 smcpa \$c15,\(\$sp\+\),-128
+ dd0: f5 ff 80 70 lmcpa \$c15,\(\$sp\+\),-128
+ dd4: f5 ff 80 38 smcpm0 \$c15,\(\$sp\+\),-128
+ dd8: f5 ff 80 78 lmcpm0 \$c15,\(\$sp\+\),-128
+ ddc: f5 ff 80 3c smcpm1 \$c15,\(\$sp\+\),-128
+ de0: f5 ff 80 7c lmcpm1 \$c15,\(\$sp\+\),-128
+ de4: 05 f0 78 30 smcpa \$c0,\(\$0\+\),120
+ de8: 05 f0 78 70 lmcpa \$c0,\(\$0\+\),120
+ dec: 05 f0 78 38 smcpm0 \$c0,\(\$0\+\),120
+ df0: 05 f0 78 78 lmcpm0 \$c0,\(\$0\+\),120
+ df4: 05 f0 78 3c smcpm1 \$c0,\(\$0\+\),120
+ df8: 05 f0 78 7c lmcpm1 \$c0,\(\$0\+\),120
+ dfc: 05 ff 78 30 smcpa \$c15,\(\$0\+\),120
+ e00: 05 ff 78 70 lmcpa \$c15,\(\$0\+\),120
+ e04: 05 ff 78 38 smcpm0 \$c15,\(\$0\+\),120
+ e08: 05 ff 78 78 lmcpm0 \$c15,\(\$0\+\),120
+ e0c: 05 ff 78 3c smcpm1 \$c15,\(\$0\+\),120
+ e10: 05 ff 78 7c lmcpm1 \$c15,\(\$0\+\),120
+ e14: f5 f0 78 30 smcpa \$c0,\(\$sp\+\),120
+ e18: f5 f0 78 70 lmcpa \$c0,\(\$sp\+\),120
+ e1c: f5 f0 78 38 smcpm0 \$c0,\(\$sp\+\),120
+ e20: f5 f0 78 78 lmcpm0 \$c0,\(\$sp\+\),120
+ e24: f5 f0 78 3c smcpm1 \$c0,\(\$sp\+\),120
+ e28: f5 f0 78 7c lmcpm1 \$c0,\(\$sp\+\),120
+ e2c: f5 ff 78 30 smcpa \$c15,\(\$sp\+\),120
+ e30: f5 ff 78 70 lmcpa \$c15,\(\$sp\+\),120
+ e34: f5 ff 78 38 smcpm0 \$c15,\(\$sp\+\),120
+ e38: f5 ff 78 78 lmcpm0 \$c15,\(\$sp\+\),120
+ e3c: f5 ff 78 3c smcpm1 \$c15,\(\$sp\+\),120
+ e40: f5 ff 78 7c lmcpm1 \$c15,\(\$sp\+\),120
+ e44: 04 d8 02 80 bcpeq 0x0,0xffff0e48
+ e48: 05 d8 02 80 bcpne 0x0,0xffff0e4c
+ e4c: 06 d8 02 80 bcpat 0x0,0xffff0e50
+ e50: 07 d8 02 80 bcpaf 0x0,0xffff0e54
+ e54: f4 d8 02 80 bcpeq 0xf,0xffff0e58
+ e58: f5 d8 02 80 bcpne 0xf,0xffff0e5c
+ e5c: f6 d8 02 80 bcpat 0xf,0xffff0e60
+ e60: f7 d8 02 80 bcpaf 0xf,0xffff0e64
+ e64: 04 d8 ff 3f bcpeq 0x0,0x8e62
+ e68: 05 d8 ff 3f bcpne 0x0,0x8e66
+ e6c: 06 d8 ff 3f bcpat 0x0,0x8e6a
+ e70: 07 d8 ff 3f bcpaf 0x0,0x8e6e
+ e74: f4 d8 ff 3f bcpeq 0xf,0x8e72
+ e78: f5 d8 ff 3f bcpne 0xf,0x8e76
+ e7c: f6 d8 ff 3f bcpat 0xf,0x8e7a
+ e80: f7 d8 ff 3f bcpaf 0xf,0x8e7e
+ e84: 04 d8 00 00 bcpeq 0x0,0xe84
+ e84: R_MEP_PCREL17A2 symbol
+ e88: 05 d8 00 00 bcpne 0x0,0xe88
+ e88: R_MEP_PCREL17A2 symbol
+ e8c: 06 d8 00 00 bcpat 0x0,0xe8c
+ e8c: R_MEP_PCREL17A2 symbol
+ e90: 07 d8 00 00 bcpaf 0x0,0xe90
+ e90: R_MEP_PCREL17A2 symbol
+ e94: f4 d8 00 00 bcpeq 0xf,0xe94
+ e94: R_MEP_PCREL17A2 symbol
+ e98: f5 d8 00 00 bcpne 0xf,0xe98
+ e98: R_MEP_PCREL17A2 symbol
+ e9c: f6 d8 00 00 bcpat 0xf,0xe9c
+ e9c: R_MEP_PCREL17A2 symbol
+ ea0: f7 d8 00 00 bcpaf 0xf,0xea0
+ ea0: R_MEP_PCREL17A2 symbol
+ ea4: 21 70 synccp
+ ea6: 0f 18 jsrv \$0
+ ea8: ff 18 jsrv \$sp
+ eaa: 2b d8 00 80 bsrv 0xff800eae
+ eae: fb df ff 7f bsrv 0x800eac
+ eb2: 0b d8 00 00 bsrv 0xeb2
+ eb2: R_MEP_PCREL24A2 symbol
+ eb6: 00 00 nop
+ eb6: R_MEP_8 symbol
+ eb7: R_MEP_16 symbol
+ eb8: 00 00 nop
+ eb9: R_MEP_32 symbol
+ eba: 00 00 nop
+.*
--- /dev/null
+
+ mov $0,$0
+ mov $1,$0
+ mov $2,$0
+ mov $3,$0
+ mov $4,$0
+ mov $5,$0
+ mov $6,$0
+ mov $7,$0
+ mov $8,$0
+ mov $9,$0
+ mov $10,$0
+ mov $11,$0
+ mov $12,$0
+ mov $13,$0
+ mov $14,$0
+ mov $15,$0
+
+ mov $fp,$0
+ mov $tp,$0
+ mov $gp,$0
+ mov $sp,$0
+
+
+ sb $0,($0)
+ sh $0,($0)
+ sw $0,($0)
+ lb $0,($0)
+ lh $0,($0)
+ lw $0,($0)
+ lbu $0,($0)
+ lhu $0,($0)
+ sb $15,($0)
+ sh $15,($0)
+ sw $15,($0)
+ lb $15,($0)
+ lh $15,($0)
+ lw $15,($0)
+ lbu $15,($0)
+ lhu $15,($0)
+ sb $0,($15)
+ sh $0,($15)
+ sw $0,($15)
+ lb $0,($15)
+ lh $0,($15)
+ lw $0,($15)
+ lbu $0,($15)
+ lhu $0,($15)
+ sb $15,($15)
+ sh $15,($15)
+ sw $15,($15)
+ lb $15,($15)
+ lh $15,($15)
+ lw $15,($15)
+ lbu $15,($15)
+ lhu $15,($15)
+
+ sw $0,0($sp)
+ lw $0,0($sp)
+ sw $15,0($sp)
+ lw $15,0($sp)
+ sw $0,124($sp)
+ lw $0,124($sp)
+ sw $15,124($sp)
+ lw $15,124($sp)
+ sw $0,0($15)
+ lw $0,0($15)
+ sw $15,0($15)
+ lw $15,0($15)
+ sw $0,124($15)
+ lw $0,124($15)
+ sw $15,124($15)
+ lw $15,124($15)
+
+ sb $0,0($tp)
+ lb $0,0($tp)
+ lbu $0,0($tp)
+ sb $7,0($tp)
+ lb $7,0($tp)
+ lbu $7,0($tp)
+ sb $0,127($tp)
+ lb $0,127($tp)
+ lbu $0,127($tp)
+ sb $7,127($tp)
+ lb $7,127($tp)
+ lbu $7,127($tp)
+ sb $0,%tpoff(symbol)($tp)
+ lb $0,%tpoff(symbol)($tp)
+ lbu $0,%tpoff(symbol)($tp)
+ sb $7,%tpoff(symbol)($tp)
+ lb $7,%tpoff(symbol)($tp)
+ lbu $7,%tpoff(symbol)($tp)
+ sb $0,0($13)
+ lb $0,0($13)
+ lbu $0,0($13)
+ sb $7,0($13)
+ lb $7,0($13)
+ lbu $7,0($13)
+ sb $0,127($13)
+ lb $0,127($13)
+ lbu $0,127($13)
+ sb $7,127($13)
+ lb $7,127($13)
+ lbu $7,127($13)
+ sb $0,%tpoff(symbol)($13)
+ lb $0,%tpoff(symbol)($13)
+ lbu $0,%tpoff(symbol)($13)
+ sb $7,%tpoff(symbol)($13)
+ lb $7,%tpoff(symbol)($13)
+ lbu $7,%tpoff(symbol)($13)
+
+ sh $0,0($tp)
+ lh $0,0($tp)
+ lhu $0,0($tp)
+ sh $7,0($tp)
+ lh $7,0($tp)
+ lhu $7,0($tp)
+ sh $0,126($tp)
+ lh $0,126($tp)
+ lhu $0,126($tp)
+ sh $7,126($tp)
+ lh $7,126($tp)
+ lhu $7,126($tp)
+ sh $0,%tpoff(symbol)($tp)
+ lh $0,%tpoff(symbol)($tp)
+ lhu $0,%tpoff(symbol)($tp)
+ sh $7,%tpoff(symbol)($tp)
+ lh $7,%tpoff(symbol)($tp)
+ lhu $7,%tpoff(symbol)($tp)
+ sh $0,0($13)
+ lh $0,0($13)
+ lhu $0,0($13)
+ sh $7,0($13)
+ lh $7,0($13)
+ lhu $7,0($13)
+ sh $0,126($13)
+ lh $0,126($13)
+ lhu $0,126($13)
+ sh $7,126($13)
+ lh $7,126($13)
+ lhu $7,126($13)
+ sh $0,%tpoff(symbol)($13)
+ lh $0,%tpoff(symbol)($13)
+ lhu $0,%tpoff(symbol)($13)
+ sh $7,%tpoff(symbol)($13)
+ lh $7,%tpoff(symbol)($13)
+ lhu $7,%tpoff(symbol)($13)
+
+ sw $0,0($tp)
+ lw $0,0($tp)
+ sw $7,0($tp)
+ lw $7,0($tp)
+ sw $0,124($tp)
+ lw $0,124($tp)
+ sw $7,124($tp)
+ lw $7,124($tp)
+ sw $0,%tpoff(symbol)($tp)
+ lw $0,%tpoff(symbol)($tp)
+ sw $7,%tpoff(symbol)($tp)
+ lw $7,%tpoff(symbol)($tp)
+ sw $0,0($13)
+ lw $0,0($13)
+ sw $7,0($13)
+ lw $7,0($13)
+ sw $0,124($13)
+ lw $0,124($13)
+ sw $7,124($13)
+ lw $7,124($13)
+ sw $0,%tpoff(symbol)($13)
+ lw $0,%tpoff(symbol)($13)
+ sw $7,%tpoff(symbol)($13)
+ lw $7,%tpoff(symbol)($13)
+
+ sb $0,-32768($0)
+ sh $0,-32768($0)
+ sw $0,-32768($0)
+ lb $0,-32768($0)
+ lh $0,-32768($0)
+ lw $0,-32768($0)
+ lbu $0,-32768($0)
+ lhu $0,-32768($0)
+ sb $15,-32768($0)
+ sh $15,-32768($0)
+ sw $15,-32768($0)
+ lb $15,-32768($0)
+ lh $15,-32768($0)
+ lw $15,-32768($0)
+ lbu $15,-32768($0)
+ lhu $15,-32768($0)
+ sb $0,32767($0)
+ sh $0,32767($0)
+ sw $0,32767($0)
+ lb $0,32767($0)
+ lh $0,32767($0)
+ lw $0,32767($0)
+ lbu $0,32767($0)
+ lhu $0,32767($0)
+ sb $15,32767($0)
+ sh $15,32767($0)
+ sw $15,32767($0)
+ lb $15,32767($0)
+ lh $15,32767($0)
+ lw $15,32767($0)
+ lbu $15,32767($0)
+ lhu $15,32767($0)
+ sb $0,%sdaoff(symbol)($0)
+ sh $0,%sdaoff(symbol)($0)
+ sw $0,%sdaoff(symbol)($0)
+ lb $0,%sdaoff(symbol)($0)
+ lh $0,%sdaoff(symbol)($0)
+ lw $0,%sdaoff(symbol)($0)
+ lbu $0,%sdaoff(symbol)($0)
+ lhu $0,%sdaoff(symbol)($0)
+ sb $15,%sdaoff(symbol)($0)
+ sh $15,%sdaoff(symbol)($0)
+ sw $15,%sdaoff(symbol)($0)
+ lb $15,%sdaoff(symbol)($0)
+ lh $15,%sdaoff(symbol)($0)
+ lw $15,%sdaoff(symbol)($0)
+ lbu $15,%sdaoff(symbol)($0)
+ lhu $15,%sdaoff(symbol)($0)
+ sb $0,-32768($0)
+ sh $0,-32768($0)
+ sw $0,-32768($0)
+ lb $0,-32768($0)
+ lh $0,-32768($0)
+ lw $0,-32768($0)
+ lbu $0,-32768($0)
+ lhu $0,-32768($0)
+ sb $15,-32768($0)
+ sh $15,-32768($0)
+ sw $15,-32768($0)
+ lb $15,-32768($0)
+ lh $15,-32768($0)
+ lw $15,-32768($0)
+ lbu $15,-32768($0)
+ lhu $15,-32768($0)
+ sb $0,32767($0)
+ sh $0,32767($0)
+ sw $0,32767($0)
+ lb $0,32767($0)
+ lh $0,32767($0)
+ lw $0,32767($0)
+ lbu $0,32767($0)
+ lhu $0,32767($0)
+ sb $15,32767($0)
+ sh $15,32767($0)
+ sw $15,32767($0)
+ lb $15,32767($0)
+ lh $15,32767($0)
+ lw $15,32767($0)
+ lbu $15,32767($0)
+ lhu $15,32767($0)
+ sb $0,%tpoff(symbol)($0)
+ sh $0,%tpoff(symbol)($0)
+ sw $0,%tpoff(symbol)($0)
+ lb $0,%tpoff(symbol)($0)
+ lh $0,%tpoff(symbol)($0)
+ lw $0,%tpoff(symbol)($0)
+ lbu $0,%tpoff(symbol)($0)
+ lhu $0,%tpoff(symbol)($0)
+ sb $15,%tpoff(symbol)($0)
+ sh $15,%tpoff(symbol)($0)
+ sw $15,%tpoff(symbol)($0)
+ lb $15,%tpoff(symbol)($0)
+ lh $15,%tpoff(symbol)($0)
+ lw $15,%tpoff(symbol)($0)
+ lbu $15,%tpoff(symbol)($0)
+ lhu $15,%tpoff(symbol)($0)
+ sb $0,-32768($15)
+ sh $0,-32768($15)
+ sw $0,-32768($15)
+ lb $0,-32768($15)
+ lh $0,-32768($15)
+ lw $0,-32768($15)
+ lbu $0,-32768($15)
+ lhu $0,-32768($15)
+ sb $15,-32768($15)
+ sh $15,-32768($15)
+ sw $15,-32768($15)
+ lb $15,-32768($15)
+ lh $15,-32768($15)
+ lw $15,-32768($15)
+ lbu $15,-32768($15)
+ lhu $15,-32768($15)
+ sb $0,32767($15)
+ sh $0,32767($15)
+ sw $0,32767($15)
+ lb $0,32767($15)
+ lh $0,32767($15)
+ lw $0,32767($15)
+ lbu $0,32767($15)
+ lhu $0,32767($15)
+ sb $15,32767($15)
+ sh $15,32767($15)
+ sw $15,32767($15)
+ lb $15,32767($15)
+ lh $15,32767($15)
+ lw $15,32767($15)
+ lbu $15,32767($15)
+ lhu $15,32767($15)
+ sb $0,%sdaoff(symbol)($15)
+ sh $0,%sdaoff(symbol)($15)
+ sw $0,%sdaoff(symbol)($15)
+ lb $0,%sdaoff(symbol)($15)
+ lh $0,%sdaoff(symbol)($15)
+ lw $0,%sdaoff(symbol)($15)
+ lbu $0,%sdaoff(symbol)($15)
+ lhu $0,%sdaoff(symbol)($15)
+ sb $15,%sdaoff(symbol)($15)
+ sh $15,%sdaoff(symbol)($15)
+ sw $15,%sdaoff(symbol)($15)
+ lb $15,%sdaoff(symbol)($15)
+ lh $15,%sdaoff(symbol)($15)
+ lw $15,%sdaoff(symbol)($15)
+ lbu $15,%sdaoff(symbol)($15)
+ lhu $15,%sdaoff(symbol)($15)
+ sb $0,-32768($15)
+ sh $0,-32768($15)
+ sw $0,-32768($15)
+ lb $0,-32768($15)
+ lh $0,-32768($15)
+ lw $0,-32768($15)
+ lbu $0,-32768($15)
+ lhu $0,-32768($15)
+ sb $15,-32768($15)
+ sh $15,-32768($15)
+ sw $15,-32768($15)
+ lb $15,-32768($15)
+ lh $15,-32768($15)
+ lw $15,-32768($15)
+ lbu $15,-32768($15)
+ lhu $15,-32768($15)
+ sb $0,32767($15)
+ sh $0,32767($15)
+ sw $0,32767($15)
+ lb $0,32767($15)
+ lh $0,32767($15)
+ lw $0,32767($15)
+ lbu $0,32767($15)
+ lhu $0,32767($15)
+ sb $15,32767($15)
+ sh $15,32767($15)
+ sw $15,32767($15)
+ lb $15,32767($15)
+ lh $15,32767($15)
+ lw $15,32767($15)
+ lbu $15,32767($15)
+ lhu $15,32767($15)
+ sb $0,%tpoff(symbol)($15)
+ sh $0,%tpoff(symbol)($15)
+ sw $0,%tpoff(symbol)($15)
+ lb $0,%tpoff(symbol)($15)
+ lh $0,%tpoff(symbol)($15)
+ lw $0,%tpoff(symbol)($15)
+ lbu $0,%tpoff(symbol)($15)
+ lhu $0,%tpoff(symbol)($15)
+ sb $15,%tpoff(symbol)($15)
+ sh $15,%tpoff(symbol)($15)
+ sw $15,%tpoff(symbol)($15)
+ lb $15,%tpoff(symbol)($15)
+ lh $15,%tpoff(symbol)($15)
+ lw $15,%tpoff(symbol)($15)
+ lbu $15,%tpoff(symbol)($15)
+ lhu $15,%tpoff(symbol)($15)
+
+ sw $0,(0)
+ lw $0,(0)
+ sw $15,(0)
+ lw $15,(0)
+ sw $0,(0xfffffc)
+ lw $0,(0xfffffc)
+ sw $15,(0xfffffc)
+ lw $15,(0xfffffc)
+ sw $0,(symbol)
+ lw $0,(symbol)
+ sw $15,(symbol)
+ lw $15,(symbol)
+
+
+ extb $0
+ extub $0
+ exth $0
+ extuh $0
+ extb $15
+ extub $15
+ exth $15
+ extuh $15
+
+
+ ssarb 0($0)
+ ssarb 3($0)
+ ssarb 0($15)
+ ssarb 3($15)
+
+
+ mov $0,$0
+ mov $15,$0
+ mov $0,$15
+ mov $15,$15
+ mov $0,-32768
+ mov $15,-32768
+ mov $0,-128
+ mov $15,-128
+ mov $0,0
+ mov $15,0
+ mov $0,127
+ mov $15,127
+ mov $0,32767
+ mov $15,32767
+
+ mov $0,%lo(symbol)
+ mov $0,%hi(symbol)
+ mov $0,%uhi(symbol)
+ mov $0,%sdaoff(symbol)
+ mov $0,%tpoff(symbol)
+
+ movu $0,0
+ movu $7,0
+ movu $0,0xffffff
+ movu $7,0xffffff
+ movu $0,%lo(symbol)
+ movu $7,%lo(symbol)
+ movu $0,symbol
+ movu $7,symbol
+
+ movu $0,0
+ movh $0,0
+ movu $15,0
+ movh $15,0
+ movu $0,0xffff
+ movh $0,0xffff
+ movu $15,0xffff
+ movh $15,0xffff
+
+ movu $0,%lo(symbol)
+ movh $0,%lo(symbol)
+ movu $15,%lo(symbol)
+ movh $15,%lo(symbol)
+ movu $0,%hi(symbol)
+ movh $0,%hi(symbol)
+ movu $15,%hi(symbol)
+ movh $15,%hi(symbol)
+ movu $0,%uhi(symbol)
+ movh $0,%uhi(symbol)
+ movu $15,%uhi(symbol)
+ movh $15,%uhi(symbol)
+ movu $0,%lo(0x12345678)
+ movh $0,%lo(0x12345678)
+ movu $15,%lo(0x12345678)
+ movh $15,%lo(0x12345678)
+ movu $0,%hi(0x12345678)
+ movh $0,%hi(0x12345678)
+ movu $15,%hi(0x12345678)
+ movh $15,%hi(0x12345678)
+ movu $0,%uhi(0x12345678)
+ movh $0,%uhi(0x12345678)
+ movu $15,%uhi(0x12345678)
+ movh $15,%uhi(0x12345678)
+
+
+ add3 $0,$0,$0
+ add3 $15,$0,$0
+ add3 $0,$15,$0
+ add3 $15,$15,$0
+ add3 $0,$0,$15
+ add3 $15,$0,$15
+ add3 $0,$15,$15
+ add3 $15,$15,$15
+
+ add $0,-16
+ add $15,-16
+ add $0,0
+ add $15,0
+ add $0,15
+ add $15,15
+
+ add3 $0,$sp,0
+ add3 $15,$sp,0
+ add3 $0,$sp,124
+ add3 $15,$sp,124
+ add3 $0,$sp,1
+ add3 $15,$sp,1
+
+ advck3 $0,$0,$0
+ sbvck3 $0,$0,$0
+ advck3 $0,$15,$0
+ sbvck3 $0,$15,$0
+ advck3 $0,$0,$15
+ sbvck3 $0,$0,$15
+ advck3 $0,$15,$15
+ sbvck3 $0,$15,$15
+
+ sub $0,$0
+ neg $0,$0
+ sub $15,$0
+ neg $15,$0
+ sub $0,$15
+ neg $0,$15
+ sub $15,$15
+ neg $15,$15
+
+ slt3 $0,$0,$0
+ sltu3 $0,$0,$0
+ sl1ad3 $0,$0,$0
+ sl2ad3 $0,$0,$0
+ slt3 $0,$15,$0
+ sltu3 $0,$15,$0
+ sl1ad3 $0,$15,$0
+ sl2ad3 $0,$15,$0
+ slt3 $0,$0,$15
+ sltu3 $0,$0,$15
+ sl1ad3 $0,$0,$15
+ sl2ad3 $0,$0,$15
+ slt3 $0,$15,$15
+ sltu3 $0,$15,$15
+ sl1ad3 $0,$15,$15
+ sl2ad3 $0,$15,$15
+
+ add3 $0,$0,-32768
+ add3 $15,$0,-32768
+ add3 $0,$15,-32768
+ add3 $15,$15,-32768
+ add3 $0,$0,32767
+ add3 $15,$0,32767
+ add3 $0,$15,32767
+ add3 $15,$15,32767
+ add3 $0,$0,%lo(symbol)
+ add3 $15,$0,%lo(symbol)
+ add3 $0,$15,%lo(symbol)
+ add3 $15,$15,%lo(symbol)
+
+ slt3 $0,$0,0
+ sltu3 $0,$0,0
+ slt3 $0,$15,0
+ sltu3 $0,$15,0
+ slt3 $0,$0,31
+ sltu3 $0,$0,31
+ slt3 $0,$15,31
+ sltu3 $0,$15,31
+
+
+ or $0,$0
+ and $0,$0
+ xor $0,$0
+ nor $0,$0
+ or $15,$0
+ and $15,$0
+ xor $15,$0
+ nor $15,$0
+ or $0,$15
+ and $0,$15
+ xor $0,$15
+ nor $0,$15
+ or $15,$15
+ and $15,$15
+ xor $15,$15
+ nor $15,$15
+
+ or3 $0,$0,0
+ and3 $0,$0,0
+ xor3 $0,$0,0
+ or3 $15,$0,0
+ and3 $15,$0,0
+ xor3 $15,$0,0
+ or3 $0,$15,0
+ and3 $0,$15,0
+ xor3 $0,$15,0
+ or3 $15,$15,0
+ and3 $15,$15,0
+ xor3 $15,$15,0
+ or3 $0,$0,65535
+ and3 $0,$0,65535
+ xor3 $0,$0,65535
+ or3 $15,$0,65535
+ and3 $15,$0,65535
+ xor3 $15,$0,65535
+ or3 $0,$15,65535
+ and3 $0,$15,65535
+ xor3 $0,$15,65535
+ or3 $15,$15,65535
+ and3 $15,$15,65535
+ xor3 $15,$15,65535
+ or3 $0,$0,%lo(symbol)
+ and3 $0,$0,%lo(symbol)
+ xor3 $0,$0,%lo(symbol)
+ or3 $15,$0,%lo(symbol)
+ and3 $15,$0,%lo(symbol)
+ xor3 $15,$0,%lo(symbol)
+ or3 $0,$15,%lo(symbol)
+ and3 $0,$15,%lo(symbol)
+ xor3 $0,$15,%lo(symbol)
+ or3 $15,$15,%lo(symbol)
+ and3 $15,$15,%lo(symbol)
+ xor3 $15,$15,%lo(symbol)
+
+
+ sra $0,$0
+ srl $0,$0
+ sll $0,$0
+ fsft $0,$0
+ sra $15,$0
+ srl $15,$0
+ sll $15,$0
+ fsft $15,$0
+ sra $0,$15
+ srl $0,$15
+ sll $0,$15
+ fsft $0,$15
+ sra $15,$15
+ srl $15,$15
+ sll $15,$15
+ fsft $15,$15
+
+ sra $0,0
+ srl $0,0
+ sll $0,0
+ sra $15,0
+ srl $15,0
+ sll $15,0
+ sra $0,31
+ srl $0,31
+ sll $0,31
+ sra $15,31
+ srl $15,31
+ sll $15,31
+
+ sll3 $0,$0,0
+ sll3 $0,$15,0
+ sll3 $0,$0,31
+ sll3 $0,$15,31
+
+
+ bra .-2048+2
+ bra .+2046+2
+ bra symbol
+
+ beqz $0,.-128+2
+ bnez $0,.-128+2
+ beqz $15,.-128+2
+ bnez $15,.-128+2
+ beqz $0,.+126+2
+ bnez $0,.+126+2
+ beqz $15,.+126+2
+ bnez $15,.+126+2
+ beqz $0,symbol
+ bnez $0,symbol
+ beqz $15,symbol
+ bnez $15,symbol
+
+ beqi $0,0,.-65536+4
+ bnei $0,0,.-65536+4
+ blti $0,0,.-65536+4
+ bgei $0,0,.-65536+4
+ beqi $15,0,.-65536+4
+ bnei $15,0,.-65536+4
+ blti $15,0,.-65536+4
+ bgei $15,0,.-65536+4
+ beqi $0,15,.-65536+4
+ bnei $0,15,.-65536+4
+ blti $0,15,.-65536+4
+ bgei $0,15,.-65536+4
+ beqi $15,15,.-65536+4
+ bnei $15,15,.-65536+4
+ blti $15,15,.-65536+4
+ bgei $15,15,.-65536+4
+ beqi $0,0,.+32763+4
+ bnei $0,0,.+32763+4
+ blti $0,0,.+32763+4
+ bgei $0,0,.+32763+4
+ beqi $15,0,.+32763+4
+ bnei $15,0,.+32763+4
+ blti $15,0,.+32763+4
+ bgei $15,0,.+32763+4
+ beqi $0,15,.+32763+4
+ bnei $0,15,.+32763+4
+ blti $0,15,.+32763+4
+ bgei $0,15,.+32763+4
+ beqi $15,15,.+32763+4
+ bnei $15,15,.+32763+4
+ blti $15,15,.+32763+4
+ bgei $15,15,.+32763+4
+ beqi $0,0,symbol
+ bnei $0,0,symbol
+ blti $0,0,symbol
+ bgei $0,0,symbol
+ beqi $15,0,symbol
+ bnei $15,0,symbol
+ blti $15,0,symbol
+ bgei $15,0,symbol
+ beqi $0,15,symbol
+ bnei $0,15,symbol
+ blti $0,15,symbol
+ bgei $0,15,symbol
+ beqi $15,15,symbol
+ bnei $15,15,symbol
+ blti $15,15,symbol
+ bgei $15,15,symbol
+
+ beq $0,$0,.-65536+4
+ bne $0,$0,.-65536+4
+ beq $15,$0,.-65536+4
+ bne $15,$0,.-65536+4
+ beq $0,$15,.-65536+4
+ bne $0,$15,.-65536+4
+ beq $15,$15,.-65536+4
+ bne $15,$15,.-65536+4
+ beq $0,$0,.+32763+4
+ bne $0,$0,.+32763+4
+ beq $15,$0,.+32763+4
+ bne $15,$0,.+32763+4
+ beq $0,$15,.+32763+4
+ bne $0,$15,.+32763+4
+ beq $15,$15,.+32763+4
+ bne $15,$15,.+32763+4
+ beq $0,$0,symbol
+ bne $0,$0,symbol
+ beq $15,$0,symbol
+ bne $15,$0,symbol
+ beq $0,$15,symbol
+ bne $0,$15,symbol
+ beq $15,$15,symbol
+ bne $15,$15,symbol
+
+ bsr .-0x800000+4
+ bsr .-2048+2
+ bsr .+2046+2
+ bsr .+0x7ffffe+4
+ bsr symbol
+
+ jmp $0
+ jmp $15
+ jmp 0
+ jmp 0xfffffe
+ jmp symbol
+
+ jsr $0
+ jsr $15
+
+ ret
+
+ repeat $0,.-65536+4
+ repeat $15,.-65536+4
+ repeat $0,.+32763+4
+ repeat $15,.+32763+4
+ repeat $0,symbol
+ repeat $15,symbol
+
+ erepeat .-65536+4
+ erepeat .+32763+4
+ erepeat symbol
+
+
+ stc $0,$pc
+ ldc $0,$pc
+ stc $15,$pc
+ ldc $15,$pc
+ stc $0,$lp
+ ldc $0,$lp
+ stc $15,$lp
+ ldc $15,$lp
+ stc $0,$sar
+ ldc $0,$sar
+ stc $15,$sar
+ ldc $15,$sar
+ stc $0,$rpb
+ ldc $0,$rpb
+ stc $15,$rpb
+ ldc $15,$rpb
+ stc $0,$rpe
+ ldc $0,$rpe
+ stc $15,$rpe
+ ldc $15,$rpe
+ stc $0,$rpc
+ ldc $0,$rpc
+ stc $15,$rpc
+ ldc $15,$rpc
+ stc $0,$hi
+ ldc $0,$hi
+ stc $15,$hi
+ ldc $15,$hi
+ stc $0,$lo
+ ldc $0,$lo
+ stc $15,$lo
+ ldc $15,$lo
+ stc $0,$mb0
+ ldc $0,$mb0
+ stc $15,$mb0
+ ldc $15,$mb0
+ stc $0,$me0
+ ldc $0,$me0
+ stc $15,$me0
+ ldc $15,$me0
+ stc $0,$mb1
+ ldc $0,$mb1
+ stc $15,$mb1
+ ldc $15,$mb1
+ stc $0,$me1
+ ldc $0,$me1
+ stc $15,$me1
+ ldc $15,$me1
+
+ stc $0,$psw
+ ldc $0,$psw
+ stc $15,$psw
+ ldc $15,$psw
+ stc $0,$id
+ ldc $0,$id
+ stc $15,$id
+ ldc $15,$id
+ stc $0,$tmp
+ ldc $0,$tmp
+ stc $15,$tmp
+ ldc $15,$tmp
+ stc $0,$epc
+ ldc $0,$epc
+ stc $15,$epc
+ ldc $15,$epc
+ stc $0,$exc
+ ldc $0,$exc
+ stc $15,$exc
+ ldc $15,$exc
+ stc $0,$cfg
+ ldc $0,$cfg
+ stc $15,$cfg
+ ldc $15,$cfg
+ stc $0,$npc
+ ldc $0,$npc
+ stc $15,$npc
+ ldc $15,$npc
+ stc $0,$dbg
+ ldc $0,$dbg
+ stc $15,$dbg
+ ldc $15,$dbg
+ stc $0,$depc
+ ldc $0,$depc
+ stc $15,$depc
+ ldc $15,$depc
+ stc $0,$opt
+ ldc $0,$opt
+ stc $15,$opt
+ ldc $15,$opt
+ stc $0,$rcfg
+ ldc $0,$rcfg
+ stc $15,$rcfg
+ ldc $15,$rcfg
+ stc $0,$ccfg
+ ldc $0,$ccfg
+ stc $15,$ccfg
+ ldc $15,$ccfg
+
+ di
+ ei
+ reti
+ halt
+ break
+ syncm
+
+ swi 0
+ swi 3
+
+ stcb $0,0
+ ldcb $0,0
+ stcb $15,0
+ ldcb $15,0
+ stcb $0,65535
+ ldcb $0,65535
+ stcb $15,65535
+ ldcb $15,65535
+ stcb $0,symbol
+ ldcb $0,symbol
+ stcb $15,symbol
+ ldcb $15,symbol
+
+
+ bsetm ($0),0
+ bclrm ($0),0
+ bnotm ($0),0
+ bsetm ($15),0
+ bclrm ($15),0
+ bnotm ($15),0
+ bsetm ($0),7
+ bclrm ($0),7
+ bnotm ($0),7
+ bsetm ($15),7
+ bclrm ($15),7
+ bnotm ($15),7
+
+ btstm $0,($0),0
+ btstm $0,($15),0
+ btstm $0,($0),7
+ btstm $0,($15),7
+
+ tas $0,($0)
+ tas $15,($0)
+ tas $0,($15)
+ tas $15,($15)
+
+
+ cache 0,($0)
+ cache 3,($0)
+ cache 0,($15)
+ cache 3,($15)
+
+ mul $0,$0
+ madd $0,$0
+ mulr $0,$0
+ maddr $0,$0
+ mulu $0,$0
+ maddu $0,$0
+ mulru $0,$0
+ maddru $0,$0
+ mul $15,$0
+ madd $15,$0
+ mulr $15,$0
+ maddr $15,$0
+ mulu $15,$0
+ maddu $15,$0
+ mulru $15,$0
+ maddru $15,$0
+ mul $0,$15
+ madd $0,$15
+ mulr $0,$15
+ maddr $0,$15
+ mulu $0,$15
+ maddu $0,$15
+ mulru $0,$15
+ maddru $0,$15
+ mul $15,$15
+ madd $15,$15
+ mulr $15,$15
+ maddr $15,$15
+ mulu $15,$15
+ maddu $15,$15
+ mulru $15,$15
+ maddru $15,$15
+
+ div $0,$0
+ divu $0,$0
+ div $15,$0
+ divu $15,$0
+ div $0,$15
+ divu $0,$15
+ div $15,$15
+ divu $15,$15
+
+ dret
+ dbreak
+
+ ldz $0,$0
+ abs $0,$0
+ ave $0,$0
+ ldz $15,$0
+ abs $15,$0
+ ave $15,$0
+ ldz $0,$15
+ abs $0,$15
+ ave $0,$15
+ ldz $15,$15
+ abs $15,$15
+ ave $15,$15
+
+ min $0,$0
+ max $0,$0
+ minu $0,$0
+ maxu $0,$0
+ min $15,$0
+ max $15,$0
+ minu $15,$0
+ maxu $15,$0
+ min $0,$15
+ max $0,$15
+ minu $0,$15
+ maxu $0,$15
+ min $15,$15
+ max $15,$15
+ minu $15,$15
+ maxu $15,$15
+
+ clip $0,0
+ clipu $0,0
+ clip $15,0
+ clipu $15,0
+ clip $0,31
+ clipu $0,31
+ clip $15,31
+ clipu $15,31
+
+ sadd $0,$0
+ ssub $0,$0
+ saddu $0,$0
+ ssubu $0,$0
+ sadd $15,$0
+ ssub $15,$0
+ saddu $15,$0
+ ssubu $15,$0
+ sadd $0,$15
+ ssub $0,$15
+ saddu $0,$15
+ ssubu $0,$15
+ sadd $15,$15
+ ssub $15,$15
+ saddu $15,$15
+ ssubu $15,$15
+
+ swcp $c0,($0)
+ lwcp $c0,($0)
+ smcp $c0,($0)
+ lmcp $c0,($0)
+ swcp $c15,($0)
+ lwcp $c15,($0)
+ smcp $c15,($0)
+ lmcp $c15,($0)
+ swcp $c0,($15)
+ lwcp $c0,($15)
+ smcp $c0,($15)
+ lmcp $c0,($15)
+ swcp $c15,($15)
+ lwcp $c15,($15)
+ smcp $c15,($15)
+ lmcp $c15,($15)
+
+ swcpi $c0,($0+)
+ lwcpi $c0,($0+)
+ smcpi $c0,($0+)
+ lmcpi $c0,($0+)
+ swcpi $c15,($0+)
+ lwcpi $c15,($0+)
+ smcpi $c15,($0+)
+ lmcpi $c15,($0+)
+ swcpi $c0,($15+)
+ lwcpi $c0,($15+)
+ smcpi $c0,($15+)
+ lmcpi $c0,($15+)
+ swcpi $c15,($15+)
+ lwcpi $c15,($15+)
+ smcpi $c15,($15+)
+ lmcpi $c15,($15+)
+
+ sbcpa $c0,($0+),-128
+ lbcpa $c0,($0+),-128
+ sbcpm0 $c0,($0+),-128
+ lbcpm0 $c0,($0+),-128
+ sbcpm1 $c0,($0+),-128
+ lbcpm1 $c0,($0+),-128
+ sbcpa $c15,($0+),-128
+ lbcpa $c15,($0+),-128
+ sbcpm0 $c15,($0+),-128
+ lbcpm0 $c15,($0+),-128
+ sbcpm1 $c15,($0+),-128
+ lbcpm1 $c15,($0+),-128
+ sbcpa $c0,($15+),-128
+ lbcpa $c0,($15+),-128
+ sbcpm0 $c0,($15+),-128
+ lbcpm0 $c0,($15+),-128
+ sbcpm1 $c0,($15+),-128
+ lbcpm1 $c0,($15+),-128
+ sbcpa $c15,($15+),-128
+ lbcpa $c15,($15+),-128
+ sbcpm0 $c15,($15+),-128
+ lbcpm0 $c15,($15+),-128
+ sbcpm1 $c15,($15+),-128
+ lbcpm1 $c15,($15+),-128
+ sbcpa $c0,($0+),127
+ lbcpa $c0,($0+),127
+ sbcpm0 $c0,($0+),127
+ lbcpm0 $c0,($0+),127
+ sbcpm1 $c0,($0+),127
+ lbcpm1 $c0,($0+),127
+ sbcpa $c15,($0+),127
+ lbcpa $c15,($0+),127
+ sbcpm0 $c15,($0+),127
+ lbcpm0 $c15,($0+),127
+ sbcpm1 $c15,($0+),127
+ lbcpm1 $c15,($0+),127
+ sbcpa $c0,($15+),127
+ lbcpa $c0,($15+),127
+ sbcpm0 $c0,($15+),127
+ lbcpm0 $c0,($15+),127
+ sbcpm1 $c0,($15+),127
+ lbcpm1 $c0,($15+),127
+ sbcpa $c15,($15+),127
+ lbcpa $c15,($15+),127
+ sbcpm0 $c15,($15+),127
+ lbcpm0 $c15,($15+),127
+ sbcpm1 $c15,($15+),127
+ lbcpm1 $c15,($15+),127
+
+ shcpa $c0,($0+),-128
+ lhcpa $c0,($0+),-128
+ shcpm0 $c0,($0+),-128
+ lhcpm0 $c0,($0+),-128
+ shcpm1 $c0,($0+),-128
+ lhcpm1 $c0,($0+),-128
+ shcpa $c15,($0+),-128
+ lhcpa $c15,($0+),-128
+ shcpm0 $c15,($0+),-128
+ lhcpm0 $c15,($0+),-128
+ shcpm1 $c15,($0+),-128
+ lhcpm1 $c15,($0+),-128
+ shcpa $c0,($15+),-128
+ lhcpa $c0,($15+),-128
+ shcpm0 $c0,($15+),-128
+ lhcpm0 $c0,($15+),-128
+ shcpm1 $c0,($15+),-128
+ lhcpm1 $c0,($15+),-128
+ shcpa $c15,($15+),-128
+ lhcpa $c15,($15+),-128
+ shcpm0 $c15,($15+),-128
+ lhcpm0 $c15,($15+),-128
+ shcpm1 $c15,($15+),-128
+ lhcpm1 $c15,($15+),-128
+ shcpa $c0,($0+),126
+ lhcpa $c0,($0+),126
+ shcpm0 $c0,($0+),126
+ lhcpm0 $c0,($0+),126
+ shcpm1 $c0,($0+),126
+ lhcpm1 $c0,($0+),126
+ shcpa $c15,($0+),126
+ lhcpa $c15,($0+),126
+ shcpm0 $c15,($0+),126
+ lhcpm0 $c15,($0+),126
+ shcpm1 $c15,($0+),126
+ lhcpm1 $c15,($0+),126
+ shcpa $c0,($15+),126
+ lhcpa $c0,($15+),126
+ shcpm0 $c0,($15+),126
+ lhcpm0 $c0,($15+),126
+ shcpm1 $c0,($15+),126
+ lhcpm1 $c0,($15+),126
+ shcpa $c15,($15+),126
+ lhcpa $c15,($15+),126
+ shcpm0 $c15,($15+),126
+ lhcpm0 $c15,($15+),126
+ shcpm1 $c15,($15+),126
+ lhcpm1 $c15,($15+),126
+
+ swcpa $c0,($0+),-128
+ lwcpa $c0,($0+),-128
+ swcpm0 $c0,($0+),-128
+ lwcpm0 $c0,($0+),-128
+ swcpm1 $c0,($0+),-128
+ lwcpm1 $c0,($0+),-128
+ swcpa $c15,($0+),-128
+ lwcpa $c15,($0+),-128
+ swcpm0 $c15,($0+),-128
+ lwcpm0 $c15,($0+),-128
+ swcpm1 $c15,($0+),-128
+ lwcpm1 $c15,($0+),-128
+ swcpa $c0,($15+),-128
+ lwcpa $c0,($15+),-128
+ swcpm0 $c0,($15+),-128
+ lwcpm0 $c0,($15+),-128
+ swcpm1 $c0,($15+),-128
+ lwcpm1 $c0,($15+),-128
+ swcpa $c15,($15+),-128
+ lwcpa $c15,($15+),-128
+ swcpm0 $c15,($15+),-128
+ lwcpm0 $c15,($15+),-128
+ swcpm1 $c15,($15+),-128
+ lwcpm1 $c15,($15+),-128
+ swcpa $c0,($0+),124
+ lwcpa $c0,($0+),124
+ swcpm0 $c0,($0+),124
+ lwcpm0 $c0,($0+),124
+ swcpm1 $c0,($0+),124
+ lwcpm1 $c0,($0+),124
+ swcpa $c15,($0+),124
+ lwcpa $c15,($0+),124
+ swcpm0 $c15,($0+),124
+ lwcpm0 $c15,($0+),124
+ swcpm1 $c15,($0+),124
+ lwcpm1 $c15,($0+),124
+ swcpa $c0,($15+),124
+ lwcpa $c0,($15+),124
+ swcpm0 $c0,($15+),124
+ lwcpm0 $c0,($15+),124
+ swcpm1 $c0,($15+),124
+ lwcpm1 $c0,($15+),124
+ swcpa $c15,($15+),124
+ lwcpa $c15,($15+),124
+ swcpm0 $c15,($15+),124
+ lwcpm0 $c15,($15+),124
+ swcpm1 $c15,($15+),124
+ lwcpm1 $c15,($15+),124
+
+ smcpa $c0,($0+),-128
+ lmcpa $c0,($0+),-128
+ smcpm0 $c0,($0+),-128
+ lmcpm0 $c0,($0+),-128
+ smcpm1 $c0,($0+),-128
+ lmcpm1 $c0,($0+),-128
+ smcpa $c15,($0+),-128
+ lmcpa $c15,($0+),-128
+ smcpm0 $c15,($0+),-128
+ lmcpm0 $c15,($0+),-128
+ smcpm1 $c15,($0+),-128
+ lmcpm1 $c15,($0+),-128
+ smcpa $c0,($15+),-128
+ lmcpa $c0,($15+),-128
+ smcpm0 $c0,($15+),-128
+ lmcpm0 $c0,($15+),-128
+ smcpm1 $c0,($15+),-128
+ lmcpm1 $c0,($15+),-128
+ smcpa $c15,($15+),-128
+ lmcpa $c15,($15+),-128
+ smcpm0 $c15,($15+),-128
+ lmcpm0 $c15,($15+),-128
+ smcpm1 $c15,($15+),-128
+ lmcpm1 $c15,($15+),-128
+ smcpa $c0,($0+),120
+ lmcpa $c0,($0+),120
+ smcpm0 $c0,($0+),120
+ lmcpm0 $c0,($0+),120
+ smcpm1 $c0,($0+),120
+ lmcpm1 $c0,($0+),120
+ smcpa $c15,($0+),120
+ lmcpa $c15,($0+),120
+ smcpm0 $c15,($0+),120
+ lmcpm0 $c15,($0+),120
+ smcpm1 $c15,($0+),120
+ lmcpm1 $c15,($0+),120
+ smcpa $c0,($15+),120
+ lmcpa $c0,($15+),120
+ smcpm0 $c0,($15+),120
+ lmcpm0 $c0,($15+),120
+ smcpm1 $c0,($15+),120
+ lmcpm1 $c0,($15+),120
+ smcpa $c15,($15+),120
+ lmcpa $c15,($15+),120
+ smcpm0 $c15,($15+),120
+ lmcpm0 $c15,($15+),120
+ smcpm1 $c15,($15+),120
+ lmcpm1 $c15,($15+),120
+
+/*
+ cmov $c0,$0
+ cmov $c15,$0
+ cmov $c0,$15
+ cmov $c15,$15
+
+ cmov $0,$c0
+ cmov $15,$c0
+ cmov $0,$c15
+ cmov $15,$c15
+
+ cmovc $ccr0,$0
+ cmovc $ccr15,$0
+ cmovc $ccr0,$15
+ cmovc $ccr15,$15
+
+ cmovc $0,$ccr0
+ cmovc $15,$ccr0
+ cmovc $0,$ccr15
+ cmovc $15,$ccr15
+
+ cmovh $c0,$0
+ cmovh $c15,$0
+ cmovh $c0,$15
+ cmovh $c15,$15
+
+ cmovh $0,$c0
+ cmovh $15,$c0
+ cmovh $0,$c15
+ cmovh $15,$c15
+*/
+ bcpeq 0,.-65536+4
+ bcpne 0,.-65536+4
+ bcpat 0,.-65536+4
+ bcpaf 0,.-65536+4
+ bcpeq 15,.-65536+4
+ bcpne 15,.-65536+4
+ bcpat 15,.-65536+4
+ bcpaf 15,.-65536+4
+ bcpeq 0,.+32763+4
+ bcpne 0,.+32763+4
+ bcpat 0,.+32763+4
+ bcpaf 0,.+32763+4
+ bcpeq 15,.+32763+4
+ bcpne 15,.+32763+4
+ bcpat 15,.+32763+4
+ bcpaf 15,.+32763+4
+ bcpeq 0,symbol
+ bcpne 0,symbol
+ bcpat 0,symbol
+ bcpaf 0,symbol
+ bcpeq 15,symbol
+ bcpne 15,symbol
+ bcpat 15,symbol
+ bcpaf 15,symbol
+
+ synccp
+
+ jsrv $0
+ jsrv $15
+
+ bsrv .+4-0x800000
+ bsrv .+4+0x7ffffb
+ bsrv symbol
+
+
+ .byte symbol
+ .short symbol
+ .long symbol
+
+
--- /dev/null
+#as:
+#objdump: -dr
+#name: dj2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 07 88 sb \$7,\(\$8\)
+ 2: 05 98 sb \$5,\(\$9\)
--- /dev/null
+#as: -EL
+#objdump: -dr
+#source: dj2.s
+#name: dj2.le
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 88 07 sb \$7,\(\$8\)
+ 2: 98 05 sb \$5,\(\$9\)
--- /dev/null
+
+ .text
+ sb $7,($fp)
+ sb $5,($9)
+
--- /dev/null
+ .global main
+
+test:
+ mov $0,0
+
+# negative test from case 106708
+
+L1:
+ mov $1,1
+ mov $1,((L1 & 0x00007fff) | 0x00008000)
+ ret
+ mov $0,0
+main:
+ mov $0,0
+ ret
--- /dev/null
+junk1:
+ nop
+ nop
+ nop
+ nop
+ nop
+ .data
+foodata: .word 42
--- /dev/null
+junk2:
+ nop
+ nop
+ nop
+ nop
+ nop
+
\ No newline at end of file
--- /dev/null
+
+ .global main
+ .global foo
+ .global bar
+main:
+ nop
+ nop
+ lb $5, foo($3)
+ bsr foo
+ repeat $5, foo
+
+ nop
+ nop
+ lb $5, (-foo & 0xffff)($3)
+ bsr -foo
+ repeat $5, -foo
+
+ nop
+ nop
+ lb $5, (foo + bar)($3)
+ bsr (foo + bar)
+ repeat $5, (foo + bar)
+
+ jmp (foo << 3)
+ jmp (foo >> 3)
+ jmp (foo - bar) & 0x7fffff
+ jmp (foo - main) & 0x7fffff
+ jmp (.text - foo) & 0x7fffff
+ jmp (.data - foo) & 0x7fffff
+ jmp (foo - %sizeof(.text))
+ jmp (foo * 7)
+ jmp (foo / 7)
+ jmp (foo % 7)
+ jmp (foo ^ bar)
+ jmp (foo | bar)
+ jmp (foo & bar)
+ jmp (foo == bar) << 5
+ jmp (foo < bar) << 5
+ jmp (foo <= bar) << 5
+ jmp (foo > bar) << 5
+ jmp (foo >= bar) << 5
+ # jmp (foo != bar) # FIXME this appears to not work atm.
+ jmp (foo && bar) << 5
+ jmp (foo || bar) << 5
+
+ nop
+ nop
+ nop
+ nop
+
+ jmp %sizeof(.data) >> (((main ^ (bar + 0xf)) - ((foo | .text) << 2)) / 3)
+
+ nop
+ nop
+ nop
--- /dev/null
+ .global foo
+ .global bar
+ nop
+ nop
+ nop
+ nop
+foo:
+ nop
+ nop
+ nop
+ nop
+bar:
+ nop
+ nop
+ nop
+ nop
+ nop
+
\ No newline at end of file
--- /dev/null
+
+relocs.x: file format elf32-mep
+
+Contents of section .text:
+ 1000 00000000 00000000 00000000 00000000 ................
+ 1010 00000000 00000000 00000000 00000000 ................
+ 1020 00000000 00000000 00000000 00000000 ................
+ 1030 0000c53c 1012dee9 ffffe509 ffec0000 ...<............
+ 1040 0000c53c efeedd49 ffdfe509 efd20000 ...<...I........
+ 1050 0000c53c 202cdeb9 000fe509 07e9dc88 ...< ,..........
+ 1060 0080d818 0002dfc8 7fffdf28 7fffdf78 ...........\(...x
+ 1070 7fffdd98 0001da98 000fdbf8 0070da58 .............p.X
+ 1080 0002d828 0000d848 0000d8d8 0010d898 ...\(...H........
+ 1090 0010d808 0000d908 0000d908 0000d808 ................
+ 10a0 0000d808 0000d908 0000d908 00000000 ................
+ 10b0 00000000 0000d808 00000000 00000000 ................
+Contents of section .rostacktab:
+ 10c0 001ffff0 ....
+Contents of section .data:
+ 11c4 0000002a ...*
+Disassembly of section .text:
+
+00001000 <junk1>:
+ 1000: 00 00 nop
+ 1002: 00 00 nop
+ 1004: 00 00 nop
+ 1006: 00 00 nop
+ 1008: 00 00 nop
+ 100a: 00 00 nop
+ 100c: 00 00 nop
+ 100e: 00 00 nop
+ 1010: 00 00 nop
+
+00001012 <foo>:
+ 1012: 00 00 nop
+ 1014: 00 00 nop
+ 1016: 00 00 nop
+ 1018: 00 00 nop
+
+0000101a <bar>:
+ 101a: 00 00 nop
+ 101c: 00 00 nop
+ 101e: 00 00 nop
+ 1020: 00 00 nop
+ 1022: 00 00 nop
+
+00001024 <junk2>:
+ 1024: 00 00 nop
+ 1026: 00 00 nop
+ 1028: 00 00 nop
+ 102a: 00 00 nop
+ 102c: 00 00 nop
+
+0000102e <main>:
+ 102e: 00 00 nop
+ 1030: 00 00 nop
+ 1032: c5 3c 10 12 lb \$5,4114\(\$3\)
+ 1036: de e9 ff ff bsr 1012 <&:s3:foo:s3:bar>
+ 103a: e5 09 ff ec repeat \$5,1012 <&:s3:foo:s3:bar>
+ 103e: 00 00 nop
+ 1040: 00 00 nop
+ 1042: c5 3c ef ee lb \$5,-4114\(\$3\)
+ 1046: dd 49 ff df bsr ffffefee <0-:s3:foo>
+ 104a: e5 09 ef d2 repeat \$5,ffffefee <0-:s3:foo>
+ 104e: 00 00 nop
+ 1050: 00 00 nop
+ 1052: c5 3c 20 2c lb \$5,8236\(\$3\)
+ 1056: de b9 00 0f bsr 202c <\+:s3:foo:s3:bar>
+ 105a: e5 09 07 e9 repeat \$5,202c <\+:s3:foo:s3:bar>
+ 105e: dc 88 00 80 jmp 8090 <<<:s3:foo:#00000003>
+ 1062: d8 18 00 02 jmp 202 <>>:s3:foo:#00000003>
+ 1066: df c8 7f ff jmp 7ffff8 <&:-:s3:foo:s3:bar:#007fffff>
+ 106a: df 28 7f ff jmp 7fffe4 <&:-:s3:foo:s4:main:#007fffff>
+ 106e: df 78 7f ff jmp 7fffee <&:-:S5:.text:s3:foo:#007fffff>
+ 1072: dd 98 00 01 jmp 1b2 <&:-:S5:.data:s3:foo:#007fffff>
+ 1076: da 98 00 0f jmp f52 <-:s3:foo:\+:s9:.text.end:0-:S5:.text>
+ 107a: db f8 00 70 jmp 707e <\*:s3:foo:#00000007>
+ 107e: da 58 00 02 jmp 24a <>>:s3:foo:#00000003\+0x48>
+ 1082: d8 28 00 00 jmp 4 <__assert_based_size\+0x3>
+ 1086: d8 48 00 00 jmp 8 <\^:s3:foo:s3:bar>
+ 108a: d8 d8 00 10 jmp 101a <|:s3:foo:s3:bar>
+ 108e: d8 98 00 10 jmp 1012 <&:s3:foo:s3:bar>
+ 1092: d8 08 00 00 jmp 0 <<<:==:s3:foo:s3:bar:#00000005>
+ 1096: d9 08 00 00 jmp 20 <<<:&&:s3:foo:s3:bar:#00000005>
+ 109a: d9 08 00 00 jmp 20 <<<:&&:s3:foo:s3:bar:#00000005>
+ 109e: d8 08 00 00 jmp 0 <<<:==:s3:foo:s3:bar:#00000005>
+ 10a2: d8 08 00 00 jmp 0 <<<:==:s3:foo:s3:bar:#00000005>
+ 10a6: d9 08 00 00 jmp 20 <<<:&&:s3:foo:s3:bar:#00000005>
+ 10aa: d9 08 00 00 jmp 20 <<<:&&:s3:foo:s3:bar:#00000005>
+ 10ae: 00 00 nop
+ 10b0: 00 00 nop
+ 10b2: 00 00 nop
+ 10b4: 00 00 nop
+ 10b6: d8 08 00 00 jmp 0 <<<:==:s3:foo:s3:bar:#00000005>
+ 10ba: 00 00 nop
+ 10bc: 00 00 nop
+ 10be: 00 00 nop
+#pass
const struct cgen_insn *insn;
/* Target specific data, usually reloc number. */
int opinfo;
+ /* Which ifield this fixup applies to. */
+ struct cgen_maybe_multi_ifield * field;
+ /* is this field is the MSB field in a set? */
+ int msb_field_p;
} fx_cgen;
#endif
projects / platform / upstream / binutils.git / commitdiff