#include "clkc.h"
#include "gxbb.h"
-static DEFINE_SPINLOCK(clk_lock);
+static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_rate_table sys_pll_rate_table[] = {
PLL_RATE(24000000, 56, 1, 2),
.shift = 16,
.width = 2,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "fixed_pll",
.ops = &meson_clk_pll_ro_ops,
.shift = 22,
.width = 2,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll",
.ops = &meson_clk_pll_ro_ops,
},
.rate_table = sys_pll_rate_table,
.rate_count = ARRAY_SIZE(sys_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sys_pll",
.ops = &meson_clk_pll_ro_ops,
},
.rate_table = gxbb_gp0_pll_rate_table,
.rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
.ops = &meson_clk_pll_ops,
},
.rate_table = gxl_gp0_pll_rate_table,
.rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "gp0_pll",
.ops = &meson_clk_pll_ops,
.shift = 25,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll0",
.ops = &meson_clk_mpll_ops,
.shift = 14,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll1",
.ops = &meson_clk_mpll_ops,
.shift = 14,
.width = 1,
},
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpll2",
.ops = &meson_clk_mpll_ops,
.shift = 12,
.flags = CLK_MUX_READ_ONLY,
.table = mux_table_clk81,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_sel",
.ops = &clk_mux_ro_ops,
.reg = (void *)HHI_MPEG_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_clk81 = {
.reg = (void *)HHI_MPEG_CLK_CNTL,
.bit_idx = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "clk81",
.ops = &clk_gate_ops,
.reg = (void *)HHI_SAR_CLK_CNTL,
.mask = 0x3,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sar_adc_clk_sel",
.ops = &clk_mux_ops,
.reg = (void *)HHI_SAR_CLK_CNTL,
.shift = 0,
.width = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sar_adc_clk_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_sar_adc_clk = {
.reg = (void *)HHI_SAR_CLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sar_adc_clk",
.ops = &clk_gate_ops,
.mask = 0x7,
.shift = 9,
.table = mux_table_mali_0_1,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_0_sel",
.ops = &clk_mux_ops,
.reg = (void *)HHI_MALI_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_0_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_mali_0 = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_0",
.ops = &clk_gate_ops,
.mask = 0x7,
.shift = 25,
.table = mux_table_mali_0_1,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_1_sel",
.ops = &clk_mux_ops,
.reg = (void *)HHI_MALI_CLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_1_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_mali_1 = {
.reg = (void *)HHI_MALI_CLK_CNTL,
.bit_idx = 24,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali_1",
.ops = &clk_gate_ops,
.mask = 1,
.shift = 31,
.table = mux_table_mali,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "mali",
.ops = &clk_mux_ops,
.shift = 9,
/* Default parent unknown (register reset value: 0) */
.table = (u32[]){ 1, 2, 3 },
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_amclk_sel",
.ops = &clk_mux_ops,
.width = 8,
},
.flags = CLK_DIVIDER_ROUND_CLOSEST,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_amclk_div",
.ops = &meson_clk_audio_divider_ops,
static struct clk_gate gxbb_cts_amclk = {
.reg = (void *) HHI_AUD_CLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_amclk",
.ops = &clk_gate_ops,
.shift = 25,
/* Default parent unknown (register reset value: 0) */
.table = (u32[]){ 1, 2, 3 },
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_sel",
.ops = &clk_mux_ops,
.reg = (void *)HHI_AUD_CLK_CNTL2,
.shift = 16,
.width = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "cts_mclk_i958_div",
static struct clk_gate gxbb_cts_mclk_i958 = {
.reg = (void *)HHI_AUD_CLK_CNTL2,
.bit_idx = 24,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_mclk_i958",
.ops = &clk_gate_ops,
.reg = (void *)HHI_AUD_CLK_CNTL2,
.mask = 0x1,
.shift = 27,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "cts_i958",
.ops = &clk_mux_ops,
.reg = (void *)HHI_32K_CLK_CNTL,
.shift = 0,
.width = 14,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "32k_clk_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_32k_clk = {
.reg = (void *)HHI_32K_CLK_CNTL,
.bit_idx = 15,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "32k_clk",
.ops = &clk_gate_ops,
.reg = (void *)HHI_32K_CLK_CNTL,
.mask = 0x3,
.shift = 16,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "32k_clk_sel",
.ops = &clk_mux_ops,
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.mask = 0x7,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_sel",
.ops = &clk_mux_ops,
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_a_clk0_div",
static struct clk_gate gxbb_sd_emmc_a_clk0 = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.bit_idx = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_a_clk0",
.ops = &clk_gate_ops,
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.mask = 0x7,
.shift = 25,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_sel",
.ops = &clk_mux_ops,
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_b_clk0_div",
static struct clk_gate gxbb_sd_emmc_b_clk0 = {
.reg = (void *)HHI_SD_EMMC_CLK_CNTL,
.bit_idx = 23,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_b_clk0",
.ops = &clk_gate_ops,
.reg = (void *)HHI_NAND_CLK_CNTL,
.mask = 0x7,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_sel",
.ops = &clk_mux_ops,
.reg = (void *)HHI_NAND_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data) {
.name = "sd_emmc_c_clk0_div",
static struct clk_gate gxbb_sd_emmc_c_clk0 = {
.reg = (void *)HHI_NAND_CLK_CNTL,
.bit_idx = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "sd_emmc_c_clk0",
.ops = &clk_gate_ops,
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 0x3,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.table = mux_table_vpu,
.hw.init = &(struct clk_init_data){
.name = "vpu_0_sel",
.reg = (void *)HHI_VPU_CLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_0_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_vpu_0 = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vpu_0",
.ops = &clk_gate_ops,
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 0x3,
.shift = 25,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.table = mux_table_vpu,
.hw.init = &(struct clk_init_data){
.name = "vpu_1_sel",
.reg = (void *)HHI_VPU_CLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu_1_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_vpu_1 = {
.reg = (void *)HHI_VPU_CLK_CNTL,
.bit_idx = 24,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vpu_1",
.ops = &clk_gate_ops,
.reg = (void *)HHI_VPU_CLK_CNTL,
.mask = 1,
.shift = 31,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vpu",
.ops = &clk_mux_ops,
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 0x3,
.shift = 9,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.table = mux_table_vapb,
.hw.init = &(struct clk_init_data){
.name = "vapb_0_sel",
.reg = (void *)HHI_VAPBCLK_CNTL,
.shift = 0,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_0_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_vapb_0 = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 8,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vapb_0",
.ops = &clk_gate_ops,
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 0x3,
.shift = 25,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.table = mux_table_vapb,
.hw.init = &(struct clk_init_data){
.name = "vapb_1_sel",
.reg = (void *)HHI_VAPBCLK_CNTL,
.shift = 16,
.width = 7,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_1_div",
.ops = &clk_divider_ops,
static struct clk_gate gxbb_vapb_1 = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 24,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vapb_1",
.ops = &clk_gate_ops,
.reg = (void *)HHI_VAPBCLK_CNTL,
.mask = 1,
.shift = 31,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data){
.name = "vapb_sel",
.ops = &clk_mux_ops,
static struct clk_gate gxbb_vapb = {
.reg = (void *)HHI_VAPBCLK_CNTL,
.bit_idx = 30,
- .lock = &clk_lock,
+ .lock = &meson_clk_lock,
.hw.init = &(struct clk_init_data) {
.name = "vapb",
.ops = &clk_gate_ops,