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i2c: mlxcpld: Add capability register description to documentation
author
Michael Shych
<michaelsh@mellanox.com>
Tue, 27 Mar 2018 14:01:26 +0000
(14:01 +0000)
committer
Wolfram Sang
<wsa@the-dreams.de>
Mon, 30 Apr 2018 08:39:29 +0000
(10:39 +0200)
It adds capability register description to documentation.
Signed-off-by: Michael Shych <michaelsh@mellanox.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Documentation/i2c/busses/i2c-mlxcpld
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diff --git
a/Documentation/i2c/busses/i2c-mlxcpld
b/Documentation/i2c/busses/i2c-mlxcpld
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925904a
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--- a/
Documentation/i2c/busses/i2c-mlxcpld
+++ b/
Documentation/i2c/busses/i2c-mlxcpld
@@
-20,6
+20,10
@@
The next transaction types are supported:
- Write Byte/Block.
Registers:
+CPBLTY 0x0 - capability reg.
+ Bits [6:5] - transaction length. b01 - 72B is supported,
+ 36B in other case.
+ Bit 7 - SMBus block read support.
CTRL 0x1 - control reg.
Resets all the registers.
HALF_CYC 0x4 - cycle reg.