soundwire: intel: cleanup WakeEnable and WakeStatus
authorPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Tue, 23 Aug 2022 05:38:46 +0000 (13:38 +0800)
committerVinod Koul <vkoul@kernel.org>
Thu, 1 Sep 2022 08:59:15 +0000 (14:29 +0530)
Regroup offset and bitfield definitions.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Link: https://lore.kernel.org/r/20220823053846.2684635-12-yung-chuan.liao@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
include/linux/soundwire/sdw_intel.h

index 3a56fd5..2e9fd91 100644 (file)
 #define SDW_SHIM_IOCTL_CIBD            BIT(8)
 #define SDW_SHIM_IOCTL_DIBD            BIT(9)
 
+/* Wake Enable*/
 #define SDW_SHIM_WAKEEN                        0x190
+
+#define SDW_SHIM_WAKEEN_ENABLE         BIT(0)
+
+/* Wake Status */
 #define SDW_SHIM_WAKESTS               0x192
 
+#define SDW_SHIM_WAKESTS_STATUS                BIT(0)
+
 /* AC Timing control */
 #define SDW_SHIM_CTMCTL(x)             (0x06E + 0x60 * (x))
 
@@ -86,9 +93,6 @@
 #define SDW_SHIM_CTMCTL_DODS           BIT(1)
 #define SDW_SHIM_CTMCTL_DOAIS          GENMASK(4, 3)
 
-#define SDW_SHIM_WAKEEN_ENABLE         BIT(0)
-#define SDW_SHIM_WAKESTS_STATUS                BIT(0)
-
 /* Intel ALH Register definitions */
 #define SDW_ALH_STRMZCFG(x)            (0x000 + (0x4 * (x)))
 #define SDW_ALH_NUM_STREAMS            64