phy: phy-mtk-tphy: support new hardware version

The PHYA arch is updated, and doesn't support slew rate calibrate
anymore on 7nm or advanced process, add a new version number to
support it.
Note: the FreqMeter bank is not used but reserved.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/1627028562-23584-2-git-send-email-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 731c483..42a1174 100644 (file)
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -27,7 +27,8 @@
 #define SSUSB_SIFSLV_V1_U3PHYD         0x000
 #define SSUSB_SIFSLV_V1_U3PHYA         0x200
 
-/* version V2 sub-banks offset base address */
+/* version V2/V3 sub-banks offset base address */
+/* V3: U2FREQ is not used anymore, but reserved */
 /* u2 phy banks */
 #define SSUSB_SIFSLV_V2_MISC           0x000
 #define SSUSB_SIFSLV_V2_U2FREQ         0x100
@@ -270,6 +271,7 @@
 enum mtk_phy_version {
        MTK_PHY_V1 = 1,
        MTK_PHY_V2,
+       MTK_PHY_V3,
 };
 
 struct mtk_phy_pdata {
@@ -330,6 +332,10 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
        int fm_out;
        u32 tmp;
 
+       /* HW V3 doesn't support slew rate cal anymore */
+       if (tphy->pdata->version == MTK_PHY_V3)
+               return;
+
        /* use force value */
        if (instance->eye_src)
                return;
@@ -878,7 +884,7 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
                writel(tmp, com + U3P_U2PHYBC12C);
        }
 
-       if (instance->eye_src) {
+       if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) {
                tmp = readl(com + U3P_USBPHYACR5);
                tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
                tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
@@ -1042,11 +1048,15 @@ static struct phy *mtk_phy_xlate(struct device *dev,
                return ERR_PTR(-EINVAL);
        }
 
-       if (tphy->pdata->version == MTK_PHY_V1) {
+       switch (tphy->pdata->version) {
+       case MTK_PHY_V1:
                phy_v1_banks_init(tphy, instance);
-       } else if (tphy->pdata->version == MTK_PHY_V2) {
+               break;
+       case MTK_PHY_V2:
+       case MTK_PHY_V3:
                phy_v2_banks_init(tphy, instance);
-       } else {
+               break;
+       default:
                dev_err(dev, "phy version is not supported\n");
                return ERR_PTR(-EINVAL);
        }
@@ -1075,6 +1085,10 @@ static const struct mtk_phy_pdata tphy_v2_pdata = {
        .version = MTK_PHY_V2,
 };
 
+static const struct mtk_phy_pdata tphy_v3_pdata = {
+       .version = MTK_PHY_V3,
+};
+
 static const struct mtk_phy_pdata mt8173_pdata = {
        .avoid_rx_sen_degradation = true,
        .version = MTK_PHY_V1,
@@ -1086,6 +1100,7 @@ static const struct of_device_id mtk_tphy_id_table[] = {
        { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
        { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
        { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
+       { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
        { },
 };
 MODULE_DEVICE_TABLE(of, mtk_tphy_id_table);
@@ -1129,12 +1144,15 @@ static int mtk_tphy_probe(struct platform_device *pdev)
                }
        }
 
-       tphy->src_ref_clk = U3P_REF_CLK;
-       tphy->src_coef = U3P_SLEW_RATE_COEF;
-       /* update parameters of slew rate calibrate if exist */
-       device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
-               &tphy->src_ref_clk);
-       device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
+       if (tphy->pdata->version < MTK_PHY_V3) {
+               tphy->src_ref_clk = U3P_REF_CLK;
+               tphy->src_coef = U3P_SLEW_RATE_COEF;
+               /* update parameters of slew rate calibrate if exist */
+               device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
+                                        &tphy->src_ref_clk);
+               device_property_read_u32(dev, "mediatek,src-coef",
+                                        &tphy->src_coef);
+       }
 
        port = 0;
        for_each_child_of_node(np, child_np) {