drm/radeon: enable the async DMA rings in the CS ioctl

This enables the functionality added in the previous
patches.  Userspace acceleration drivers can use the
CS ioctl to submit command buffers to the async DMA
rings.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 1b32a5a..396baba 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -112,6 +112,18 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
                } else
                        p->ring = RADEON_RING_TYPE_GFX_INDEX;
                break;
+       case RADEON_CS_RING_DMA:
+               if (p->rdev->family >= CHIP_CAYMAN) {
+                       if (p->priority > 0)
+                               p->ring = R600_RING_TYPE_DMA_INDEX;
+                       else
+                               p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
+               } else if (p->rdev->family >= CHIP_R600) {
+                       p->ring = R600_RING_TYPE_DMA_INDEX;
+               } else {
+                       return -EINVAL;
+               }
+               break;
        }
        return 0;
 }

diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 5645a87..eeda917 100644 (file)
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -917,6 +917,7 @@ struct drm_radeon_gem_va {
 /* The second dword of RADEON_CHUNK_ID_FLAGS is a uint32 that sets the ring type */
 #define RADEON_CS_RING_GFX          0
 #define RADEON_CS_RING_COMPUTE      1
+#define RADEON_CS_RING_DMA          2
 /* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
 /* 0 = normal, + = higher priority, - = lower priority */