soc: mscc: ocelot: add MII registers description
authorMaxim Kochetkov <fido_max@inbox.ru>
Mon, 13 Jul 2020 16:57:02 +0000 (19:57 +0300)
committerDavid S. Miller <davem@davemloft.net>
Tue, 14 Jul 2020 00:40:01 +0000 (17:40 -0700)
Add the register definitions for the MSCC MIIM MDIO controller in
preparation for seville_vsc9959.c to create its accessors for the
internal MDIO bus.

Since we've introduced elements to ocelot_regfields that are not
instantiated by felix and ocelot, we need to define the size of the
regfields arrays explicitly, otherwise ocelot_regfields_init, which
iterates up to REGFIELD_MAX, will fault on the undefined regfield
entries (if we're lucky).

Signed-off-by: Maxim Kochetkov <fido_max@inbox.ru>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/dsa/ocelot/felix_vsc9959.c
drivers/net/ethernet/mscc/ocelot_vsc7514.c
include/soc/mscc/ocelot.h

index 0c54d67..b97c12a 100644 (file)
@@ -469,7 +469,7 @@ static const struct resource vsc9959_imdio_res = {
        .name           = "imdio",
 };
 
-static const struct reg_field vsc9959_regfields[] = {
+static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
        [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
        [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
        [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
index 63af145..83c17c6 100644 (file)
@@ -316,7 +316,7 @@ static const u32 *ocelot_regmap[TARGET_MAX] = {
        [DEV_GMII] = ocelot_dev_gmii_regmap,
 };
 
-static const struct reg_field ocelot_regfields[] = {
+static const struct reg_field ocelot_regfields[REGFIELD_MAX] = {
        [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
        [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
        [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
index c2a2d01..348fa26 100644 (file)
@@ -409,6 +409,9 @@ enum ocelot_reg {
        PTP_CLK_CFG_ADJ_CFG,
        PTP_CLK_CFG_ADJ_FREQ,
        GCB_SOFT_RST = GCB << TARGET_OFFSET,
+       GCB_MIIM_MII_STATUS,
+       GCB_MIIM_MII_CMD,
+       GCB_MIIM_MII_DATA,
        DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
        DEV_PORT_MISC,
        DEV_EVENTS,
@@ -496,6 +499,8 @@ enum ocelot_regfield {
        SYS_RESET_CFG_MEM_ENA,
        SYS_RESET_CFG_MEM_INIT,
        GCB_SOFT_RST_SWC_RST,
+       GCB_MIIM_MII_STATUS_PENDING,
+       GCB_MIIM_MII_STATUS_BUSY,
        REGFIELD_MAX
 };