drm/amdgpu: add function to program pbb mode for sienna cichlid

Add function for sienna_cichlid to force PBB workload mode to zero by
checking whether there have SE been harvested.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.9.x

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 9792ec7..f95a173 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -112,6 +112,22 @@
 #define mmCP_HYP_ME_UCODE_DATA                 0x5817
 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX                1
 
+//CC_GC_SA_UNIT_DISABLE
+#define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
+#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
+#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT       0x8
+#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK         0x0000FF00L
+//GC_USER_SA_UNIT_DISABLE
+#define mmGC_USER_SA_UNIT_DISABLE               0x0fea
+#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
+#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT     0x8
+#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK       0x0000FF00L
+//PA_SC_ENHANCE_3
+#define mmPA_SC_ENHANCE_3                       0x1085
+#define mmPA_SC_ENHANCE_3_BASE_IDX              0
+#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
+#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
+
 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -3188,6 +3204,8 @@ static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
+static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
+static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
 
 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 {
@@ -6950,6 +6968,9 @@ static int gfx_v10_0_hw_init(void *handle)
        if (r)
                return r;
 
+       if (adev->asic_type == CHIP_SIENNA_CICHLID)
+               gfx_v10_3_program_pbb_mode(adev);
+
        return r;
 }
 
@@ -8797,6 +8818,47 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
        return 0;
 }
 
+static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
+{
+       uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
+
+       efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
+       efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
+       efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
+
+       vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
+       vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
+       vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
+
+       max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
+                                               adev->gfx.config.max_shader_engines);
+       disabled_sa = efuse_setting | vbios_setting;
+       disabled_sa &= max_sa_mask;
+
+       return disabled_sa;
+}
+
+static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
+{
+       uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
+       uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
+
+       disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
+
+       max_sa_per_se = adev->gfx.config.max_sh_per_se;
+       max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
+       max_shader_engines = adev->gfx.config.max_shader_engines;
+
+       for (se_index = 0; max_shader_engines > se_index; se_index++) {
+               disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
+               disabled_sa_per_se &= max_sa_per_se_mask;
+               if (disabled_sa_per_se == max_sa_per_se_mask) {
+                       WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
+                       break;
+               }
+       }
+}
+
 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
 {
        .type = AMD_IP_BLOCK_TYPE_GFX,