if (key->fs.clip_plane_enable) {
NIR_PASS_V(s, nir_lower_clip_fs, key->fs.clip_plane_enable, false);
}
-
- memcpy(inputs.rt_formats, key->fs.rt_formats, sizeof(inputs.rt_formats));
} else if (s->info.stage == MESA_SHADER_VERTEX) {
inputs.fixed_varying_mask = fixed_varying_mask;
if (dev->arch <= 5 && s->info.stage == MESA_SHADER_FRAGMENT) {
NIR_PASS_V(s, pan_lower_framebuffer, key->fs.rt_formats,
- pan_raw_format_mask_midgard(key->fs.rt_formats), false,
+ pan_raw_format_mask_midgard(key->fs.rt_formats), 0,
dev->gpu_id < 0x700);
}
.fixed_sysval_ubo = -1,
};
- inputs.rt_formats[rt] = key.format;
+ enum pipe_format rt_formats[8] = {0};
+ rt_formats[rt] = key.format;
#if PAN_ARCH >= 6
inputs.blend.bifrost_blend_desc =
pan_shader_preprocess(nir, inputs.gpu_id);
#if PAN_ARCH >= 6
- NIR_PASS_V(nir, GENX(pan_inline_rt_conversion), dev, inputs.rt_formats);
+ NIR_PASS_V(nir, GENX(pan_inline_rt_conversion), dev, rt_formats);
+#else
+ NIR_PASS_V(nir, pan_lower_framebuffer, rt_formats,
+ pan_raw_format_mask_midgard(rt_formats), MAX2(key.nr_samples, 1),
+ dev->gpu_id < 0x700);
#endif
GENX(pan_shader_compile)(nir, &inputs, &variant->binary, &info);
assert(sem.location >= FRAG_RESULT_DATA0);
unsigned rt = sem.location - FRAG_RESULT_DATA0;
- unsigned nr_samples = MAX2(ctx->inputs->blend.nr_samples, 1);
- const struct util_format_description *desc =
- util_format_description(ctx->inputs->rt_formats[rt]);
-
- /* We have to split writeout in 128 bit chunks */
- unsigned blend_sample_iterations =
- DIV_ROUND_UP(desc->block.bits * nr_samples, 128);
-
- for (unsigned s = 0; s < blend_sample_iterations; s++) {
- emit_fragment_store(ctx, reg, ~0, ~0, rt + MIDGARD_COLOR_RT0, s);
- }
-
+ emit_fragment_store(ctx, reg, ~0, ~0, rt + MIDGARD_COLOR_RT0,
+ nir_intrinsic_base(instr));
break;
}
bool no_idvs;
bool no_ubo_to_push;
- enum pipe_format rt_formats[8];
-
/* Used on Valhall.
*
* Bit mask of special desktop-only varyings (e.g VARYING_SLOT_TEX0)
static void
pan_lower_fb_store(nir_builder *b, nir_intrinsic_instr *intr,
const struct util_format_description *desc,
- bool reorder_comps)
+ bool reorder_comps, unsigned nr_samples)
{
/* For stores, add conversion before */
nir_ssa_def *unpacked =
nir_ssa_def *packed = pan_pack(b, desc, unpacked);
- nir_store_raw_output_pan(b, packed,
- .io_semantics = nir_intrinsic_io_semantics(intr));
+ /* We have to split writeout in 128 bit chunks */
+ unsigned iterations = DIV_ROUND_UP(desc->block.bits * nr_samples, 128);
+
+ for (unsigned s = 0; s < iterations; ++s) {
+ nir_store_raw_output_pan(b, packed,
+ .io_semantics = nir_intrinsic_io_semantics(intr),
+ .base = s);
+ }
}
static nir_ssa_def *
uint8_t raw_fmt_mask;
bool is_blend;
bool broken_ld_special;
+ unsigned nr_samples;
};
static bool
if (is_store) {
b->cursor = nir_before_instr(instr);
- pan_lower_fb_store(b, intr, desc, reorder_comps);
+ pan_lower_fb_store(b, intr, desc, reorder_comps, inputs->nr_samples);
} else {
b->cursor = nir_after_instr(instr);
pan_lower_fb_load(b, intr, desc, reorder_comps, sample);
bool
pan_lower_framebuffer(nir_shader *shader, const enum pipe_format *rt_fmts,
- uint8_t raw_fmt_mask, bool is_blend,
+ uint8_t raw_fmt_mask, unsigned blend_shader_nr_samples,
bool broken_ld_special)
{
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
&(struct inputs){
.rt_fmts = rt_fmts,
.raw_fmt_mask = raw_fmt_mask,
- .is_blend = is_blend,
+ .nr_samples = blend_shader_nr_samples,
+ .is_blend = blend_shader_nr_samples > 0,
.broken_ld_special = broken_ld_special,
});
}
pan_unpacked_type_for_format(const struct util_format_description *desc);
bool pan_lower_framebuffer(nir_shader *shader, const enum pipe_format *rt_fmts,
- uint8_t raw_fmt_mask, bool is_blend,
+ uint8_t raw_fmt_mask,
+ unsigned blend_shader_nr_samples,
bool broken_ld_special);
#endif