pan/lower_framebuffer: Lower MSAA blend shaders
authorAlyssa Rosenzweig <alyssa@collabora.com>
Tue, 7 Feb 2023 04:38:12 +0000 (23:38 -0500)
committerMarge Bot <emma+marge@anholt.net>
Thu, 23 Mar 2023 23:53:46 +0000 (23:53 +0000)
Do it explicitly in NIR rather than implicitly in the Midgard compiler. This
avoids a nasty sideband input for the render target formats and sample count,
for blend shaders on midgard only.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20906>

src/gallium/drivers/panfrost/pan_shader.c
src/panfrost/lib/pan_blend.c
src/panfrost/midgard/midgard_compile.c
src/panfrost/util/pan_ir.h
src/panfrost/util/pan_lower_framebuffer.c
src/panfrost/util/pan_lower_framebuffer.h

index 08b5676..8997cd2 100644 (file)
@@ -108,8 +108,6 @@ panfrost_shader_compile(struct panfrost_screen *screen, const nir_shader *ir,
       if (key->fs.clip_plane_enable) {
          NIR_PASS_V(s, nir_lower_clip_fs, key->fs.clip_plane_enable, false);
       }
-
-      memcpy(inputs.rt_formats, key->fs.rt_formats, sizeof(inputs.rt_formats));
    } else if (s->info.stage == MESA_SHADER_VERTEX) {
       inputs.fixed_varying_mask = fixed_varying_mask;
 
@@ -122,7 +120,7 @@ panfrost_shader_compile(struct panfrost_screen *screen, const nir_shader *ir,
 
    if (dev->arch <= 5 && s->info.stage == MESA_SHADER_FRAGMENT) {
       NIR_PASS_V(s, pan_lower_framebuffer, key->fs.rt_formats,
-                 pan_raw_format_mask_midgard(key->fs.rt_formats), false,
+                 pan_raw_format_mask_midgard(key->fs.rt_formats), 0,
                  dev->gpu_id < 0x700);
    }
 
index e36506a..63be4b0 100644 (file)
@@ -871,7 +871,8 @@ GENX(pan_blend_get_shader_locked)(const struct panfrost_device *dev,
       .fixed_sysval_ubo = -1,
    };
 
-   inputs.rt_formats[rt] = key.format;
+   enum pipe_format rt_formats[8] = {0};
+   rt_formats[rt] = key.format;
 
 #if PAN_ARCH >= 6
    inputs.blend.bifrost_blend_desc =
@@ -882,7 +883,11 @@ GENX(pan_blend_get_shader_locked)(const struct panfrost_device *dev,
    pan_shader_preprocess(nir, inputs.gpu_id);
 
 #if PAN_ARCH >= 6
-   NIR_PASS_V(nir, GENX(pan_inline_rt_conversion), dev, inputs.rt_formats);
+   NIR_PASS_V(nir, GENX(pan_inline_rt_conversion), dev, rt_formats);
+#else
+   NIR_PASS_V(nir, pan_lower_framebuffer, rt_formats,
+              pan_raw_format_mask_midgard(rt_formats), MAX2(key.nr_samples, 1),
+              dev->gpu_id < 0x700);
 #endif
 
    GENX(pan_shader_compile)(nir, &inputs, &variant->binary, &info);
index 2081c40..50a49b5 100644 (file)
@@ -2060,18 +2060,8 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
       assert(sem.location >= FRAG_RESULT_DATA0);
       unsigned rt = sem.location - FRAG_RESULT_DATA0;
 
-      unsigned nr_samples = MAX2(ctx->inputs->blend.nr_samples, 1);
-      const struct util_format_description *desc =
-         util_format_description(ctx->inputs->rt_formats[rt]);
-
-      /* We have to split writeout in 128 bit chunks */
-      unsigned blend_sample_iterations =
-         DIV_ROUND_UP(desc->block.bits * nr_samples, 128);
-
-      for (unsigned s = 0; s < blend_sample_iterations; s++) {
-         emit_fragment_store(ctx, reg, ~0, ~0, rt + MIDGARD_COLOR_RT0, s);
-      }
-
+      emit_fragment_store(ctx, reg, ~0, ~0, rt + MIDGARD_COLOR_RT0,
+                          nir_intrinsic_base(instr));
       break;
    }
 
index 97df6eb..3731b1b 100644 (file)
@@ -183,8 +183,6 @@ struct panfrost_compile_inputs {
    bool no_idvs;
    bool no_ubo_to_push;
 
-   enum pipe_format rt_formats[8];
-
    /* Used on Valhall.
     *
     * Bit mask of special desktop-only varyings (e.g VARYING_SLOT_TEX0)
index 07df4eb..b30f26a 100644 (file)
@@ -505,7 +505,7 @@ static nir_ssa_def *pan_pack(nir_builder *b,
 static void
 pan_lower_fb_store(nir_builder *b, nir_intrinsic_instr *intr,
                    const struct util_format_description *desc,
-                   bool reorder_comps)
+                   bool reorder_comps, unsigned nr_samples)
 {
    /* For stores, add conversion before */
    nir_ssa_def *unpacked =
@@ -518,8 +518,14 @@ pan_lower_fb_store(nir_builder *b, nir_intrinsic_instr *intr,
 
    nir_ssa_def *packed = pan_pack(b, desc, unpacked);
 
-   nir_store_raw_output_pan(b, packed,
-                            .io_semantics = nir_intrinsic_io_semantics(intr));
+   /* We have to split writeout in 128 bit chunks */
+   unsigned iterations = DIV_ROUND_UP(desc->block.bits * nr_samples, 128);
+
+   for (unsigned s = 0; s < iterations; ++s) {
+      nir_store_raw_output_pan(b, packed,
+                               .io_semantics = nir_intrinsic_io_semantics(intr),
+                               .base = s);
+   }
 }
 
 static nir_ssa_def *
@@ -572,6 +578,7 @@ struct inputs {
    uint8_t raw_fmt_mask;
    bool is_blend;
    bool broken_ld_special;
+   unsigned nr_samples;
 };
 
 static bool
@@ -611,7 +618,7 @@ lower(nir_builder *b, nir_instr *instr, void *data)
 
    if (is_store) {
       b->cursor = nir_before_instr(instr);
-      pan_lower_fb_store(b, intr, desc, reorder_comps);
+      pan_lower_fb_store(b, intr, desc, reorder_comps, inputs->nr_samples);
    } else {
       b->cursor = nir_after_instr(instr);
       pan_lower_fb_load(b, intr, desc, reorder_comps, sample);
@@ -623,7 +630,7 @@ lower(nir_builder *b, nir_instr *instr, void *data)
 
 bool
 pan_lower_framebuffer(nir_shader *shader, const enum pipe_format *rt_fmts,
-                      uint8_t raw_fmt_mask, bool is_blend,
+                      uint8_t raw_fmt_mask, unsigned blend_shader_nr_samples,
                       bool broken_ld_special)
 {
    assert(shader->info.stage == MESA_SHADER_FRAGMENT);
@@ -633,7 +640,8 @@ pan_lower_framebuffer(nir_shader *shader, const enum pipe_format *rt_fmts,
       &(struct inputs){
          .rt_fmts = rt_fmts,
          .raw_fmt_mask = raw_fmt_mask,
-         .is_blend = is_blend,
+         .nr_samples = blend_shader_nr_samples,
+         .is_blend = blend_shader_nr_samples > 0,
          .broken_ld_special = broken_ld_special,
       });
 }
index 96f711a..bf65091 100644 (file)
@@ -34,7 +34,8 @@ nir_alu_type
 pan_unpacked_type_for_format(const struct util_format_description *desc);
 
 bool pan_lower_framebuffer(nir_shader *shader, const enum pipe_format *rt_fmts,
-                           uint8_t raw_fmt_mask, bool is_blend,
+                           uint8_t raw_fmt_mask,
+                           unsigned blend_shader_nr_samples,
                            bool broken_ld_special);
 
 #endif