[PowerPC] add tests for hoisting bitwise logic; NFC

llvm-svn: 348516

diff --git a/llvm/test/CodeGen/PowerPC/hoist-logic.ll b/llvm/test/CodeGen/PowerPC/hoist-logic.ll
new file mode 100644 (file)
index 0000000..8c9f86b
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/hoist-logic.ll
@@ -0,0 +1,72 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
+
+; This is good - eliminate an op by hoisting logic.
+
+define i32 @lshr_or(i32 %x, i32 %y, i32 %z, i32* %p1, i32* %p2) {
+; CHECK-LABEL: lshr_or:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or 3, 3, 4
+; CHECK-NEXT:    srw 3, 3, 5
+; CHECK-NEXT:    blr
+  %xt = lshr i32 %x, %z
+  %yt = lshr i32 %y, %z
+  %r = or i32 %xt, %yt
+  ret i32 %r
+}
+
+; This is questionable - hoisting doesn't eliminate anything.
+
+define i32 @lshr_or_multiuse1(i32 %x, i32 %y, i32 %z, i32* %p1, i32* %p2) {
+; CHECK-LABEL: lshr_or_multiuse1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or 4, 3, 4
+; CHECK-NEXT:    srw 4, 4, 5
+; CHECK-NEXT:    srw 5, 3, 5
+; CHECK-NEXT:    mr 3, 4
+; CHECK-NEXT:    stw 5, 0(6)
+; CHECK-NEXT:    blr
+  %xt = lshr i32 %x, %z
+  %yt = lshr i32 %y, %z
+  store i32 %xt, i32* %p1
+  %r = or i32 %xt, %yt
+  ret i32 %r
+}
+
+; This is questionable - hoisting doesn't eliminate anything.
+
+define i32 @lshr_multiuse2(i32 %x, i32 %y, i32 %z, i32* %p1, i32* %p2) {
+; CHECK-LABEL: lshr_multiuse2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or 3, 3, 4
+; CHECK-NEXT:    srw 3, 3, 5
+; CHECK-NEXT:    srw 4, 4, 5
+; CHECK-NEXT:    stw 4, 0(7)
+; CHECK-NEXT:    blr
+  %xt = lshr i32 %x, %z
+  %yt = lshr i32 %y, %z
+  store i32 %yt, i32* %p2
+  %r = or i32 %xt, %yt
+  ret i32 %r
+}
+
+; FIXME: This is not profitable to hoist. We need an extra shift instruction.
+
+define i32 @lshr_multiuse3(i32 %x, i32 %y, i32 %z, i32* %p1, i32* %p2) {
+; CHECK-LABEL: lshr_multiuse3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    or 8, 3, 4
+; CHECK-NEXT:    srw 3, 3, 5
+; CHECK-NEXT:    stw 3, 0(6)
+; CHECK-NEXT:    srw 3, 8, 5
+; CHECK-NEXT:    srw 4, 4, 5
+; CHECK-NEXT:    stw 4, 0(7)
+; CHECK-NEXT:    blr
+  %xt = lshr i32 %x, %z
+  %yt = lshr i32 %y, %z
+  store i32 %xt, i32* %p1
+  store i32 %yt, i32* %p2
+  %r = or i32 %xt, %yt
+  ret i32 %r
+}
+