ROOTDIR = $(CURDIR)
-.PHONY: clean all test doc pylint cpplint lint\
+.PHONY: clean all test doc pylint cpplint scalalint lint\
cython cython2 cython3 web runtime vta
ifndef DMLC_CORE_PATH
jnilint:
python3 3rdparty/dmlc-core/scripts/lint.py tvm4j-jni cpp jvm/native/src
-lint: cpplint pylint jnilint
+scalalint:
+ make -C vta/hardware/chisel lint
+
+lint: cpplint pylint jnilint scalalint
doc:
doxygen docs/Doxyfile
# Rebuild cython
make cython3
+# Reset default fsim simulation
+cp vta/config/fsim_sample.json vta/config/vta_config.json
+
# Run unit tests in functional/fast simulator
echo "Running unittest in fsim..."
python3 -m pytest -v vta/tests/python/unittest
# Run unit tests in functional/fast simulator
echo "Running integration test in fsim..."
python3 -m pytest -v vta/tests/python/integration
-
-# # Build VTA chisel design and verilator simulator
-# (make -C vta/hardware/chisel/)
-
-# # Set default VTA config to use TSIM cycle accurate sim
-# cp vta/config/tsim_sample.json vta/config/vta_config.json
-
-# # Run unit tests in cycle accurate simulator
-# echo "Running unittest in tsim..."
-# python3 -m pytest -v vta/tests/python/unittest
-
-# # Run unit tests in cycle accurate simulator
-# echo "Running integration test in tsim..."
-# python3 -m pytest -v vta/tests/python/integration
-
-# # Reset default fsim simulation
-# cp vta/config/fsim_sample.json vta/config/vta_config.json
# Rebuild cython
make cython3
+# Reset default fsim simulation
+cp vta/config/fsim_sample.json vta/config/vta_config.json
+
# Run unit tests in functional/fast simulator
echo "Running unittest in fsim..."
python3 -m pytest -v vta/tests/python/unittest
# Run unit tests in functional/fast simulator
echo "Running integration test in fsim..."
python3 -m pytest -v vta/tests/python/integration
-
-# # Build VTA chisel design and verilator simulator
-# (make -C vta/hardware/chisel/)
-
-# # Set default VTA config to use TSIM cycle accurate sim
-# cp vta/config/tsim_sample.json vta/config/vta_config.json
-
-# # Run unit tests in cycle accurate simulator
-# echo "Running unittest in tsim..."
-# python3 -m pytest -v vta/tests/python/unittest
-
-# # Run unit tests in cycle accurate simulator
-# echo "Running integration test in tsim..."
-# python3 -m pytest -v vta/tests/python/integration
-
-# # Reset default fsim simulation
-# cp vta/config/fsim_sample.json vta/config/vta_config.json
# Rebuild cython
make cython3
-# Run unit tests in functional/fast simulator
-echo "Running unittest in fsim..."
-python3 -m pytest -v vta/tests/python/unittest
-
-# Run unit tests in functional/fast simulator
-echo "Running integration test in fsim..."
-python3 -m pytest -v vta/tests/python/integration
+# Set default VTA config to use TSIM cycle accurate sim
+cp vta/config/tsim_sample.json vta/config/vta_config.json
-# # Build VTA chisel design and verilator simulator
-# (make -C vta/hardware/chisel/)
+# Check style of scala code
+echo "Check style of scala code..."
+make -C vta/hardware/chisel lint
-# # Set default VTA config to use TSIM cycle accurate sim
-# cp vta/config/tsim_sample.json vta/config/vta_config.json
+# Build VTA chisel design and verilator simulator
+echo "Building VTA chisel design..."
+make -C vta/hardware/chisel cleanall
+make -C vta/hardware/chisel USE_THREADS=0 lib
-# # Run unit tests in cycle accurate simulator
-# echo "Running unittest in tsim..."
-# python3 -m pytest -v vta/tests/python/unittest
+# Run unit tests in cycle accurate simulator
+echo "Running unittest in tsim..."
+python3 -m pytest -v vta/tests/python/unittest
-# # Run unit tests in cycle accurate simulator
-# echo "Running integration test in tsim..."
-# python3 -m pytest -v vta/tests/python/integration
+# Run unit tests in cycle accurate simulator
+echo "Running integration test in tsim..."
+python3 -m pytest -v vta/tests/python/integration
-# # Reset default fsim simulation
-# cp vta/config/fsim_sample.json vta/config/vta_config.json
+# Reset default fsim simulation
+cp vta/config/fsim_sample.json vta/config/vta_config.json
endif
ifneq ($(USE_THREADS), 0)
- verilator_opt += -threads $(USE_THREADS)
+ verilator_opt += --threads $(USE_THREADS)
cxx_flags += -DVL_THREADED
cxx_objs += $(verilator_build_dir)/verilated_threads.o
endif
val xmax = (1 << mp.lenBits).U
val xmax_bytes = ((1 << mp.lenBits) * mp.dataBits / 8).U
- val offsetIsEven = (dec.sram_offset % 2.U) === 0.U
+ val dram_even = (dec.dram_offset % 2.U) === 0.U
+ val sram_even = (dec.sram_offset % 2.U) === 0.U
val sizeIsEven = (dec.xsize % 2.U) === 0.U
val sIdle :: sReadCmd :: sReadData :: Nil = Enum(3)
// read-from-dram
val maskOffset = VecInit(Seq.fill(M_DRAM_OFFSET_BITS)(true.B)).asUInt
when(state === sIdle) {
- when(offsetIsEven) {
+ when(dram_even) {
raddr := io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))
}.otherwise {
- raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(
- uopBytes)))) - uopBytes.U
+ raddr := (io.baddr | (maskOffset & (dec.dram_offset << log2Ceil(uopBytes)))) - uopBytes.U
}
}.elsewhen(state === sReadData && xcnt === xlen && xrem =/= 0.U) {
raddr := raddr + xmax_bytes
val mem = SyncReadMem(uopDepth, chiselTypeOf(wdata))
val wmask = Reg(Vec(numUop, Bool()))
- when(offsetIsEven) {
+ when(sram_even) {
when(sizeIsEven) {
wmask := "b_11".U.asTypeOf(wmask)
}.elsewhen(io.vme_rd.cmd.fire()) {
}
wdata := io.vme_rd.data.bits.asTypeOf(wdata)
+ when(dram_even === false.B && sram_even) {
+ wdata(0) := io.vme_rd.data.bits.asTypeOf(wdata)(1)
+ }.elsewhen(sram_even === false.B && dram_even) {
+ wdata(1) := io.vme_rd.data.bits.asTypeOf(wdata)(0)
+ }
+
when(io.vme_rd.data.fire()) {
mem.write(waddr, wdata, wmask)
}
tfp->dump(static_cast<vluint64_t>(trace_count * 2 + 1));
#endif
trace_count++;
+ if ((trace_count % 1000000) == 1)
+ fprintf(stderr, "[traced %dM cycles]\n", trace_count / 1000000);
while (top->sim_wait) {
top->clock = 0;
std::this_thread::sleep_for(std::chrono::milliseconds(100));
# Download test image
image_url = 'https://homes.cs.washington.edu/~moreau/media/vta/cat.jpg'
-response = requests.get(image_url)
+image_fn = 'cat.png'
+download.download(image_url, image_fn)
# Prepare test image for inference
-image = Image.open(BytesIO(response.content)).resize((224, 224))
+image = Image.open(image_fn).resize((224, 224))
plt.imshow(image)
plt.show()
image = np.array(image) - np.array([123., 117., 104.])