hdmitx: add VPP_POSTBLEND_H_SIZE config

PD#138714: add VPP_POSTBLEND_H_SIZE config

Change-Id: I8e203690b12cae712c7c18f2fd601fc6d3fe0d40
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index 39e45b2..e295be2 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -1796,6 +1796,7 @@ static void set_tmds_clk_div40(unsigned int div40)
 static int hdmitx_set_dispmode(struct hdmitx_dev *hdev)
 {
        unsigned char rx_ver = 0;
+       struct hdmi_format_para *para = NULL;
 
        if (hdev->cur_video_param == NULL) /* disable HDMI */
                return 0;
@@ -1872,7 +1873,15 @@ static int hdmitx_set_dispmode(struct hdmitx_dev *hdev)
        if (hdev->flag_3dfp)
                set_vmode_3dfp_enc_hw(hdev->cur_video_param->VIC);
        else
-       set_vmode_enc_hw(hdev->cur_video_param->VIC);
+               set_vmode_enc_hw(hdev->cur_video_param->VIC);
+       para = hdmi_get_fmt_paras(hdev->cur_video_param->VIC);
+       if (para == NULL) {
+               pr_info("error at %s[%d] vic = %d\n", __func__, __LINE__,
+                       hdev->cur_video_param->VIC);
+       } else {
+               hd_write_reg(P_VPP_POSTBLEND_H_SIZE, para->hdmitx_vinfo.width);
+       }
+
        if (hdev->flag_3dfp) {
                hd_write_reg(P_VPU_HDMI_SETTING, 0x8e);
                goto next;

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
index 3836e22..2adffd8 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/mach_reg.h
@@ -787,6 +787,9 @@ void init_reg_map(void);
 #define ENCP_SYNC_TO_PIXEL 0x1c47      /* register.h:8399 */
 #define P_ENCP_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCP_SYNC_TO_PIXEL)
 
+#define VPP_POSTBLEND_H_SIZE 0x1d21
+#define P_VPP_POSTBLEND_H_SIZE VCBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE)
+
 /* [3:2] cntl_viu2_sel_venc: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. */
 /* [1:0] cntl_viu1_sel_venc: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT. */
 #define VPU_VIU_VENC_MUX_CTRL 0x271a   /* register.h:9214 */