Production Tigerlake and DG1 hardware shouldn't need this workaround.
It was only needed on the very first steppings which never went public.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16575>
0, NULL, 0, 0);
}
- /* Wa_1409226450, Wait for EU to be idle before pipe control which
- * invalidates the instruction cache
- */
- if (GFX_VER == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) {
- iris_emit_raw_pipe_control(batch,
- "workaround: CS stall before instruction "
- "cache invalidate",
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_STALL_AT_SCOREBOARD, bo, offset,
- imm);
- }
-
if (GFX_VER == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*
bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
}
- /* Wa_1409226450, Wait for EU to be idle before pipe control which
- * invalidates the instruction cache
- */
- if (GFX_VER == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT))
- bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
-
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*
* "PIPECONTROL command with “Command Streamer Stall Enable” must be