arm64: dts: mediatek: add OPP support for mt8365 SoC

In order to have cpufreq support, this patch adds generic Operating
Performance Points support.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Link: https://lore.kernel.org/r/20230203-evk-board-support-v8-8-7019f3fd0adf@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index bb45aab..cfe0c67 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -20,6 +20,91 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
+       cluster0_opp: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-850000000 {
+                       opp-hz = /bits/ 64 <850000000>;
+                       opp-microvolt = <650000>;
+               };
+
+               opp-918000000 {
+                       opp-hz = /bits/ 64 <918000000>;
+                       opp-microvolt = <668750>;
+               };
+
+               opp-987000000 {
+                       opp-hz = /bits/ 64 <987000000>;
+                       opp-microvolt = <687500>;
+               };
+
+               opp-1056000000 {
+                       opp-hz = /bits/ 64 <1056000000>;
+                       opp-microvolt = <706250>;
+               };
+
+               opp-1125000000 {
+                       opp-hz = /bits/ 64 <1125000000>;
+                       opp-microvolt = <725000>;
+               };
+
+               opp-1216000000 {
+                       opp-hz = /bits/ 64 <1216000000>;
+                       opp-microvolt = <750000>;
+               };
+
+               opp-1308000000 {
+                       opp-hz = /bits/ 64 <1308000000>;
+                       opp-microvolt = <775000>;
+               };
+
+               opp-1400000000 {
+                       opp-hz = /bits/ 64 <1400000000>;
+                       opp-microvolt = <800000>;
+               };
+
+               opp-1466000000 {
+                       opp-hz = /bits/ 64 <1466000000>;
+                       opp-microvolt = <825000>;
+               };
+
+               opp-1533000000 {
+                       opp-hz = /bits/ 64 <1533000000>;
+                       opp-microvolt = <850000>;
+               };
+
+               opp-1633000000 {
+                       opp-hz = /bits/ 64 <1633000000>;
+                       opp-microvolt = <887500>;
+               };
+
+               opp-1700000000 {
+                       opp-hz = /bits/ 64 <1700000000>;
+                       opp-microvolt = <912500>;
+               };
+
+               opp-1767000000 {
+                       opp-hz = /bits/ 64 <1767000000>;
+                       opp-microvolt = <937500>;
+               };
+
+               opp-1834000000 {
+                       opp-hz = /bits/ 64 <1834000000>;
+                       opp-microvolt = <962500>;
+               };
+
+               opp-1917000000 {
+                       opp-hz = /bits/ 64 <1917000000>;
+                       opp-microvolt = <993750>;
+               };
+
+               opp-2001000000 {
+                       opp-hz = /bits/ 64 <2001000000>;
+                       opp-microvolt = <1025000>;
+               };
+       };
+
                cpu-map {
                        cluster0 {
                                core0 {
@@ -50,6 +135,10 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&l2>;
+                       clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu1: cpu@1 {
@@ -65,6 +154,10 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&l2>;
+                       clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate", "armpll";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu2: cpu@2 {
@@ -80,6 +173,10 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&l2>;
+                       clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate", "armpll";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                cpu3: cpu@3 {
@@ -95,6 +192,10 @@
                        d-cache-line-size = <64>;
                        d-cache-sets = <256>;
                        next-level-cache = <&l2>;
+                       clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+                                <&apmixedsys CLK_APMIXED_MAINPLL>;
+                       clock-names = "cpu", "intermediate", "armpll";
+                       operating-points-v2 = <&cluster0_opp>;
                };
 
                l2: l2-cache {