85xx: Add support for setting IVORs to fixed offset defaults

In future Book-E implementations IVORs will most likely go away and be
replaced with fixed offsets.  The IVPR will continue to exist to allow
for relocation of the interrupt vectors.

This code adds support to setup the IVORs as their fixed offset values
per the ISA 2.06 spec when we transition from u-boot to another OS
either via 'bootm' or a cpu release.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index c4d1a9d..a54cf5d 100644 (file)
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -375,3 +375,10 @@ int cpu_init_r(void)
 #endif
        return 0;
 }
+
+extern void setup_ivors(void);
+
+void arch_preboot_os(void)
+{
+       setup_ivors();
+}

diff --git a/cpu/mpc85xx/fixed_ivor.S b/cpu/mpc85xx/fixed_ivor.S
new file mode 100644 (file)
index 0000000..dc725c9
--- /dev/null
+++ b/cpu/mpc85xx/fixed_ivor.S
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Kumar Gala <kumar.gala@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is intended to be included by other asm code since
+ * we will want to execute this on both the primary core when
+ * it does a bootm and the secondary core's that get released
+ * out of the spin table */
+
+#define SET_IVOR(vector_number, vector_offset) \
+       li      r3,vector_offset@l;             \
+       mtspr   SPRN_IVOR##vector_number,r3;
+
+#define SET_GIVOR(vector_number, vector_offset)        \
+       li      r3,vector_offset@l;             \
+       mtspr   SPRN_GIVOR##vector_number,r3;
+
+        SET_IVOR(0, 0x020) /* Critical Input */
+        SET_IVOR(1, 0x000) /* Machine Check */
+        SET_IVOR(2, 0x060) /* Data Storage */
+        SET_IVOR(3, 0x080) /* Instruction Storage */
+        SET_IVOR(4, 0x0a0) /* External Input */
+        SET_IVOR(5, 0x0c0) /* Alignment */
+        SET_IVOR(6, 0x0e0) /* Program */
+        SET_IVOR(7, 0x100) /* FP Unavailable */
+        SET_IVOR(8, 0x120) /* System Call */
+        SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
+        SET_IVOR(10, 0x160) /* Decrementer */
+        SET_IVOR(11, 0x180) /* Fixed Interval Timer */
+        SET_IVOR(12, 0x1a0) /* Watchdog Timer */
+        SET_IVOR(13, 0x1c0) /* Data TLB Error */
+        SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
+        SET_IVOR(15, 0x040) /* Debug */
+
+/* e500v1 & e500v2 only */
+#ifndef CONFIG_E500MC
+       SET_IVOR(32, 0x200) /* SPE Unavailable */
+       SET_IVOR(33, 0x220) /* Embedded FP Data */
+       SET_IVOR(34, 0x240) /* Embedded FP Round */
+#endif
+
+        SET_IVOR(35, 0x260) /* Performance monitor */
+
+/* e500mc only */
+#ifdef CONFIG_E500MC
+        SET_IVOR(36, 0x280) /* Processor doorbell */
+        SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
+        SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
+        SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */
+        SET_IVOR(40, 0x300) /* Hypervisor system call */
+        SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
+
+        SET_GIVOR(2, 0x060) /* Guest Data Storage */
+        SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
+        SET_GIVOR(4, 0x0a0) /* Guest External Input */
+        SET_GIVOR(8, 0x120) /* Guest System Call */
+        SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
+        SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
+#endif

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 2d4f219..074b056 100644 (file)
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -168,6 +168,9 @@ __secondary_start_page:
        bne     2b
        isync
 
+       /* setup IVORs to match fixed offsets */
+#include "fixed_ivor.S"
+
        /* get the upper bits of the addr */
        lwz     r11,ENTRY_ADDR_UPPER(r10)
 

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 4f7236f..e21a4eb 100644 (file)
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1122,3 +1122,9 @@ flush_dcache:
        isync
 
        blr
+
+.globl setup_ivors
+setup_ivors:
+
+#include "fixed_ivor.S"
+       blr

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index dcaf8c0..78ef418 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -468,6 +468,16 @@
 #define SPRN_IVOR13    0x19d   /* Interrupt Vector Offset Register 13 */
 #define SPRN_IVOR14    0x19e   /* Interrupt Vector Offset Register 14 */
 #define SPRN_IVOR15    0x19f   /* Interrupt Vector Offset Register 15 */
+#define SPRN_IVOR38    0x1b0   /* Interrupt Vector Offset Register 38 */
+#define SPRN_IVOR39    0x1b1   /* Interrupt Vector Offset Register 39 */
+#define SPRN_IVOR40    0x1b2   /* Interrupt Vector Offset Register 40 */
+#define SPRN_IVOR41    0x1b3   /* Interrupt Vector Offset Register 41 */
+#define SPRN_GIVOR2    0x1b8   /* Guest Interrupt Vector Offset Register 2 */
+#define SPRN_GIVOR3    0x1b9   /* Guest Interrupt Vector Offset Register 3 */
+#define SPRN_GIVOR4    0x1ba   /* Guest Interrupt Vector Offset Register 4 */
+#define SPRN_GIVOR8    0x1bb   /* Guest Interrupt Vector Offset Register 8 */
+#define SPRN_GIVOR13   0x1bc   /* Guest Interrupt Vector Offset Register 13 */
+#define SPRN_GIVOR14   0x1bd   /* Guest Interrupt Vector Offset Register 14 */
 
 /* e500 definitions */
 #define SPRN_L1CFG0    0x203   /* L1 Cache Configuration Register 0 */
@@ -513,6 +523,8 @@
 #define SPRN_IVOR33    0x211   /* Interrupt Vector Offset Register 33 */
 #define SPRN_IVOR34    0x212   /* Interrupt Vector Offset Register 34 */
 #define SPRN_IVOR35    0x213   /* Interrupt Vector Offset Register 35 */
+#define SPRN_IVOR36    0x214   /* Interrupt Vector Offset Register 36 */
+#define SPRN_IVOR37    0x215   /* Interrupt Vector Offset Register 37 */
 #define SPRN_SPEFSCR   0x200   /* SPE & Embedded FP Status & Control */
 
 #define SPRN_MCSRR0    0x23a   /* Machine Check Save and Restore Register 0 */