drm/amdgpu: drop ih reroute function from psp v11

For all the ASICs that integrate psp v11, vega20
doesn't support ih reroute. arcturus and later will
allow kernel driver to program ih_cfg_index/data
through mmio directly. navi1x and onwards will only
support grb_ih_set command in sriov configuration.

psp_v11_0_reroute_ih is not needed any more.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index bd4248c93c49ff5a59d2f255a1a543524805bd66..a738a7d7e38394e5b41f3b0c9c6be6d18504216b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -392,37 +392,6 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
        return ret;
 }
 
-static void psp_v11_0_reroute_ih(struct psp_context *psp)
-{
-       struct amdgpu_device *adev = psp->adev;
-       uint32_t tmp;
-
-       /* Change IH ring for VMC */
-       tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
-       tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
-       tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
-
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
-
-       mdelay(20);
-       psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                    0x80000000, 0x8000FFFF, false);
-
-       /* Change IH ring for UMC */
-       tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
-       tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
-
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
-       WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
-
-       mdelay(20);
-       psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                    0x80000000, 0x8000FFFF, false);
-}
-
 static int psp_v11_0_ring_init(struct psp_context *psp,
                              enum psp_ring_type ring_type)
 {
@@ -430,11 +399,6 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
        struct psp_ring *ring;
        struct amdgpu_device *adev = psp->adev;
 
-       if ((!amdgpu_sriov_vf(adev)) &&
-           !(adev->asic_type >= CHIP_SIENNA_CICHLID &&
-           adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
-               psp_v11_0_reroute_ih(psp);
-
        ring = &psp->km_ring;
 
        ring->ring_type = ring_type;