[SVE] Add patterns for MUL immediate instruction.

Summary: Add the missing MUL pattern for integer immediate instructions.

Reviewers: sdesmalen, huntergr, efriedma, c-rhodes, kmclaughlin

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits, amehsan

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72654

diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 82af6dc00746af1a2fa02f5dc0e39f0bf22ccfe9..a4d0ac89e8476d1dc107f3d8686649560858e162 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -135,7 +135,7 @@ let Predicates = [HasSVE] in {
   defm UMAX_ZI   : sve_int_arith_imm1_unsigned<0b01, "umax", umax>;
   defm UMIN_ZI   : sve_int_arith_imm1_unsigned<0b11, "umin", umin>;
 
-  defm MUL_ZI    : sve_int_arith_imm2<"mul">;
+  defm MUL_ZI    : sve_int_arith_imm2<"mul", mul>;
   defm MUL_ZPmZ   : sve_int_bin_pred_arit_2<0b000, "mul", int_aarch64_sve_mul>;
   defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", int_aarch64_sve_smulh>;
   defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh", int_aarch64_sve_umulh>;

diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 385d1267be2b56b442bdeab13c90cd303fb860f5..a172b8d7e6b0a2497d5cb3622136b1bf656e5002 100644 (file)
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -3537,11 +3537,16 @@ multiclass sve_int_arith_imm1_unsigned<bits<2> opc, string asm, SDPatternOperato
   def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithUImmPat, !cast<Instruction>(NAME # _D)>;
 }
 
-multiclass sve_int_arith_imm2<string asm> {
+multiclass sve_int_arith_imm2<string asm, SDPatternOperator op> {
   def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8,  simm8>;
   def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>;
   def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>;
   def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>;
+
+  def : SVE_1_Op_Imm_Arith_Pat<nxv16i8, op, ZPR8, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _B)>;
+  def : SVE_1_Op_Imm_Arith_Pat<nxv8i16, op, ZPR16, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _H)>;
+  def : SVE_1_Op_Imm_Arith_Pat<nxv4i32, op, ZPR32, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _S)>;
+  def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithSImmPat, !cast<Instruction>(NAME # _D)>;
 }
 
 //===----------------------------------------------------------------------===//

diff --git a/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll b/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
index ec87c27e8d8bbe9e44425c89f7c35d68df75f43e..451ddbbd87658ed612edff58ff8a135fadb4b9f0 100644 (file)
--- a/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
+++ b/llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
@@ -363,3 +363,86 @@ define <vscale x 2 x i64> @umin_i64_large(<vscale x 2 x i64> %a) {
   %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
   ret <vscale x 2 x i64> %res
 }
+
+;
+; MUL
+;
+define <vscale x 16 x i8> @mul_i8_neg(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: mul_i8_neg
+; CHECK: mul z0.b, z0.b, #-17
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 16 x i8> undef, i8 -17, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %res = mul <vscale x 16 x i8> %a, %splat
+  ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 16 x i8> @mul_i8_pos(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: mul_i8_pos
+; CHECK: mul z0.b, z0.b, #105
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 16 x i8> undef, i8 105, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %res = mul <vscale x 16 x i8> %a, %splat
+  ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @mul_i16_neg(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: mul_i16_neg
+; CHECK: mul z0.h, z0.h, #-17
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 8 x i16> undef, i16 -17, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %res = mul <vscale x 8 x i16> %a, %splat
+  ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 8 x i16> @mul_i16_pos(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: mul_i16_pos
+; CHECK: mul z0.h, z0.h, #105
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 8 x i16> undef, i16 105, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %res = mul <vscale x 8 x i16> %a, %splat
+  ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @mul_i32_neg(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: mul_i32_neg
+; CHECK: mul z0.s, z0.s, #-17
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 4 x i32> undef, i32 -17, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %res = mul <vscale x 4 x i32> %a, %splat
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 4 x i32> @mul_i32_pos(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: mul_i32_pos
+; CHECK: mul z0.s, z0.s, #105
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 4 x i32> undef, i32 105, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %res = mul <vscale x 4 x i32> %a, %splat
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @mul_i64_neg(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: mul_i64_neg
+; CHECK: mul z0.d, z0.d, #-17
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 2 x i64> undef, i64 -17, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %res = mul <vscale x 2 x i64> %a, %splat
+  ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 2 x i64> @mul_i64_pos(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: mul_i64_pos
+; CHECK: mul z0.d, z0.d, #105
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 2 x i64> undef, i64 105, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %res = mul <vscale x 2 x i64> %a, %splat
+  ret <vscale x 2 x i64> %res
+}

diff --git a/llvm/test/CodeGen/AArch64/sve-neg-int-arith-imm-2.ll b/llvm/test/CodeGen/AArch64/sve-neg-int-arith-imm-2.ll
new file mode 100644 (file)
index 0000000..56d6542
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-neg-int-arith-imm-2.ll
@@ -0,0 +1,12 @@
+; RUN: not llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s
+
+; Numbers smaller than -127 and greater than or equal to 127 are not allowed.
+; This should get lowered to a regular vector multiply and these tests should
+; be updated when those patterns are added.
+
+define <vscale x 2 x i64> @mul_i64_neg_1(<vscale x 2 x i64> %a) {
+  %elt = insertelement <vscale x 2 x i64> undef, i64 255, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %res = mul <vscale x 2 x i64> %a, %splat
+  ret <vscale x 2 x i64> %res
+}

diff --git a/llvm/test/CodeGen/AArch64/sve-neg-int-arith-imm.ll b/llvm/test/CodeGen/AArch64/sve-neg-int-arith-imm.ll
new file mode 100644 (file)
index 0000000..992b158
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-neg-int-arith-imm.ll
@@ -0,0 +1,11 @@
+; RUN: not llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s
+
+; Numbers smaller than -127 and greater than or equal to 127 allowed for imm mul.
+; This should get lowered to a regular vector multiply and these tests should
+; be updated when those patterns are added.
+define <vscale x 2 x i64> @mul_i64_neg_1(<vscale x 2 x i64> %a) {
+  %elt = insertelement <vscale x 2 x i64> undef, i64 -130, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %res = mul <vscale x 2 x i64> %a, %splat
+  ret <vscale x 2 x i64> %res
+}