[InstCombine] auto-generate checks; NFC

llvm-svn: 292682

diff --git a/llvm/test/Transforms/InstCombine/2009-03-20-AShrOverShift.ll b/llvm/test/Transforms/InstCombine/2009-03-20-AShrOverShift.ll
deleted file mode 100644 (file)
index 4d47977..0000000
--- a/llvm/test/Transforms/InstCombine/2009-03-20-AShrOverShift.ll
+++ /dev/null
@@ -1,9 +0,0 @@
-; RUN: opt < %s -instcombine -S | grep "ashr i32 %val, 31"
-; PR3851
-
-define i32 @foo2(i32 %val) nounwind {
-entry:
-       %shr = ashr i32 %val, 15                ; <i32> [#uses=3]
-       %shr4 = ashr i32 %shr, 17               ; <i32> [#uses=1]
-        ret i32 %shr4
- }

diff --git a/llvm/test/Transforms/InstCombine/shift-sra.ll b/llvm/test/Transforms/InstCombine/shift-sra.ll
index 7523550..ebb6ab2 100644 (file)
--- a/llvm/test/Transforms/InstCombine/shift-sra.ll
+++ b/llvm/test/Transforms/InstCombine/shift-sra.ll
@@ -1,26 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 
 define i32 @test1(i32 %X, i8 %A) {
-        %shift.upgrd.1 = zext i8 %A to i32              ; <i32> [#uses=1]
-        ; can be logical shift.
-        %Y = ashr i32 %X, %shift.upgrd.1                ; <i32> [#uses=1]
-        %Z = and i32 %Y, 1              ; <i32> [#uses=1]
-        ret i32 %Z
 ; CHECK-LABEL: @test1(
-; CHECK: lshr i32 %X, %shift.upgrd.1 
+; CHECK-NEXT:    [[SHIFT_UPGRD_1:%.*]] = zext i8 %A to i32
+; CHECK-NEXT:    [[Y1:%.*]] = lshr i32 %X, [[SHIFT_UPGRD_1]]
+; CHECK-NEXT:    [[Z:%.*]] = and i32 [[Y1]], 1
+; CHECK-NEXT:    ret i32 [[Z]]
+;
+  %shift.upgrd.1 = zext i8 %A to i32
+  ; can be logical shift.
+  %Y = ashr i32 %X, %shift.upgrd.1
+  %Z = and i32 %Y, 1
+  ret i32 %Z
 }
 
 define i32 @test2(i8 %tmp) {
-        %tmp3 = zext i8 %tmp to i32             ; <i32> [#uses=1]
-        %tmp4 = add i32 %tmp3, 7                ; <i32> [#uses=1]
-        %tmp5 = ashr i32 %tmp4, 3               ; <i32> [#uses=1]
-        ret i32 %tmp5
 ; CHECK-LABEL: @test2(
-; CHECK: lshr i32 %tmp4, 3
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i8 %tmp to i32
+; CHECK-NEXT:    [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 7
+; CHECK-NEXT:    [[TMP51:%.*]] = lshr i32 [[TMP4]], 3
+; CHECK-NEXT:    ret i32 [[TMP51]]
+;
+  %tmp3 = zext i8 %tmp to i32
+  %tmp4 = add i32 %tmp3, 7
+  %tmp5 = ashr i32 %tmp4, 3
+  ret i32 %tmp5
 }
 
 define i64 @test3(i1 %X, i64 %Y, i1 %Cond) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    br i1 %Cond, label %T, label %F
+; CHECK:       T:
+; CHECK-NEXT:    [[X2:%.*]] = sext i1 %X to i64
+; CHECK-NEXT:    br label %C
+; CHECK:       F:
+; CHECK-NEXT:    [[Y2:%.*]] = ashr i64 %Y, 63
+; CHECK-NEXT:    br label %C
+; CHECK:       C:
+; CHECK-NEXT:    [[P:%.*]] = phi i64 [ [[X2]], %T ], [ [[Y2]], %F ]
+; CHECK-NEXT:    ret i64 [[P]]
+;
   br i1 %Cond, label %T, label %F
 T:
   %X2 = sext i1 %X to i64
@@ -29,16 +50,24 @@ F:
   %Y2 = ashr i64 %Y, 63
   br label %C
 C:
-  %P = phi i64 [%X2, %T], [%Y2, %F] 
+  %P = phi i64 [%X2, %T], [%Y2, %F]
   %S = ashr i64 %P, 12
   ret i64 %S
-  
-; CHECK-LABEL: @test3(
-; CHECK: %P = phi i64
-; CHECK-NEXT: ret i64 %P
 }
 
 define i64 @test4(i1 %X, i64 %Y, i1 %Cond) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    br i1 %Cond, label %T, label %F
+; CHECK:       T:
+; CHECK-NEXT:    [[X2:%.*]] = sext i1 %X to i64
+; CHECK-NEXT:    br label %C
+; CHECK:       F:
+; CHECK-NEXT:    [[Y2:%.*]] = ashr i64 %Y, 63
+; CHECK-NEXT:    br label %C
+; CHECK:       C:
+; CHECK-NEXT:    [[P:%.*]] = phi i64 [ [[X2]], %T ], [ [[Y2]], %F ]
+; CHECK-NEXT:    ret i64 [[P]]
+;
   br i1 %Cond, label %T, label %F
 T:
   %X2 = sext i1 %X to i64
@@ -47,18 +76,29 @@ F:
   %Y2 = ashr i64 %Y, 63
   br label %C
 C:
-  %P = phi i64 [%X2, %T], [%Y2, %F] 
+  %P = phi i64 [%X2, %T], [%Y2, %F]
   %R = shl i64 %P, 12
   %S = ashr i64 %R, 12
   ret i64 %S
-  
-; CHECK-LABEL: @test4(
-; CHECK: %P = phi i64
-; CHECK-NEXT: ret i64 %P
 }
 
 ; rdar://7732987
 define i32 @test5(i32 %Y) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:    br i1 undef, label %A, label %C
+; CHECK:       A:
+; CHECK-NEXT:    br i1 undef, label %B, label %D
+; CHECK:       B:
+; CHECK-NEXT:    br label %D
+; CHECK:       C:
+; CHECK-NEXT:    br i1 undef, label %D, label %E
+; CHECK:       D:
+; CHECK-NEXT:    [[P:%.*]] = phi i32 [ 0, %A ], [ 0, %B ], [ %Y, %C ]
+; CHECK-NEXT:    [[S:%.*]] = ashr i32 [[P]], 16
+; CHECK-NEXT:    ret i32 [[S]]
+; CHECK:       E:
+; CHECK-NEXT:    ret i32 0
+;
   br i1 undef, label %A, label %C
 A:
   br i1 undef, label %B, label %D
@@ -67,12 +107,22 @@ B:
 C:
   br i1 undef, label %D, label %E
 D:
-  %P = phi i32 [0, %A], [0, %B], [%Y, %C] 
+  %P = phi i32 [0, %A], [0, %B], [%Y, %C]
   %S = ashr i32 %P, 16
   ret i32 %S
-; CHECK-LABEL: @test5(
-; CHECK: %P = phi i32
-; CHECK-NEXT: ashr i32 %P, 16
 E:
   ret i32 0
 }
+
+; PR3851
+
+define i32 @ashr_overshift(i32 %val) {
+; CHECK-LABEL: @ashr_overshift(
+; CHECK-NEXT:    [[SHR4:%.*]] = ashr i32 %val, 31
+; CHECK-NEXT:    ret i32 [[SHR4]]
+;
+  %shr = ashr i32 %val, 15
+  %shr4 = ashr i32 %shr, 17
+  ret i32 %shr4
+}
+