platform/x86: intel_pmc_core: Update Kconfig

The intel_pmc_core driver is mostly used as a debugging driver for Intel
platforms that support SLPS0 (S0ix). But the driver may also be used to
communicate actions to the PMC in order to ensure transition to SLPS0 on
some systems and architectures. As such the driver should be built on all
platforms it supports. Indicate this in the Kconfig. Also update the list
of supported features.

Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Suggested-by: Mario Limonciello <mario.limonciello@dell.com>
Link: https://lore.kernel.org/r/20210319201844.3305399-1-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index ad4e630e73e26b8cc689a5f36628370e72cfd0e5..461ec61530ebf2a12883899f4734d85da62c42a8 100644 (file)
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1173,15 +1173,20 @@ config INTEL_PMC_CORE
        depends on PCI
        help
          The Intel Platform Controller Hub for Intel Core SoCs provides access
-         to Power Management Controller registers via a PCI interface. This
+         to Power Management Controller registers via various interfaces. This
          driver can utilize debugging capabilities and supported features as
-         exposed by the Power Management Controller.
+         exposed by the Power Management Controller. It also may perform some
+         tasks in the PMC in order to enable transition into the SLPS0 state.
+         It should be selected on all Intel platforms supported by the driver.
 
          Supported features:
                - SLP_S0_RESIDENCY counter
                - PCH IP Power Gating status
-               - LTR Ignore
+               - LTR Ignore / LTR Show
                - MPHY/PLL gating status (Sunrisepoint PCH only)
+               - SLPS0 Debug registers (Cannonlake/Icelake PCH)
+               - Low Power Mode registers (Tigerlake and beyond)
+               - PMC quirks as needed to enable SLPS0/S0ix
 
 config INTEL_PMT_CLASS
        tristate