PREFETCHWT1 instruction's CPUID was TBD before.
Now it has its new CPUID bit : PREFETCHWT1
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
VSCATTERPF1DPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c6 /6 ] AVX512PF,FUTURE
VSCATTERPF1QPD zmem64|mask [m:t1s: vsibz evex.512.66.0f38.w1 c7 /6 ] AVX512PF,FUTURE
VSCATTERPF1QPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c7 /6 ] AVX512PF,FUTURE
-PREFETCHWT1 mem8 [m: 0f 0d /2 ] FUTURE
+PREFETCHWT1 mem8 [m: 0f 0d /2 ] PREFETCHWT1,FUTURE
; MPX instructions
BNDMK bndreg,mem32 [rm: o32 f3 0f 1b /r ] MPX,SD,FUTURE
#define IF_AVX512PF (UINT64_C(0x1800000000)|IF_AVX512) /* AVX-512 Prefetch instructions */
#define IF_MPX UINT64_C(0x1900000000) /* MPX instructions */
#define IF_SHA UINT64_C(0x1A00000000) /* SHA instructions */
+#define IF_PREFETCHWT1 UINT64_C(0x1F00000000) /* PREFETCHWT1 instructions */
#define IF_INSMASK UINT64_C(0xFF00000000) /* the mask for instruction set types */
#define IF_PMASK UINT64_C(0xFF000000) /* the mask for processor types */
#define IF_PLEVEL UINT64_C(0x0F000000) /* the mask for processor instr. level */