def LO64 : RegisterWithSubRegs<"lo", [LO]>;
}
- // Status flags register
- def FCR31 : Register<"31">;
+ // FP control registers.
+ foreach I = 0-31 in
+ def FCR#I : MipsReg<#I, ""#I>;
// fcc0 register
def FCC0 : MipsReg<0, "fcc0">;
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
-// Condition Register for floating point operations
-def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable;
+// FP control registers.
+def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
+ Unallocatable;
+
+// FP condition code registers.
+def FCC : RegisterClass<"Mips", [i32], 32, (add FCC0)>, Unallocatable;
// Hi/Lo Registers
def LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>;