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clk: sifive: Fix the wrong bit field shift
author
Zong Li
<zong.li@sifive.com>
Wed, 9 Dec 2020 09:49:15 +0000
(17:49 +0800)
committer
Stephen Boyd
<sboyd@kernel.org>
Wed, 16 Dec 2020 20:23:12 +0000
(12:23 -0800)
The clk enable bit should be 31 instead of 24.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Link:
https://lore.kernel.org/r/20201209094916.17383-5-zong.li@sifive.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/sifive/sifive-prci.h
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diff --git
a/drivers/clk/sifive/sifive-prci.h
b/drivers/clk/sifive/sifive-prci.h
index
7e509df
..
88493f3
100644
(file)
--- a/
drivers/clk/sifive/sifive-prci.h
+++ b/
drivers/clk/sifive/sifive-prci.h
@@
-59,7
+59,7
@@
/* DDRPLLCFG1 */
#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT
24
+#define PRCI_DDRPLLCFG1_CKE_SHIFT
31
#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
/* GEMGXLPLLCFG0 */
@@
-81,7
+81,7
@@
/* GEMGXLPLLCFG1 */
#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT
24
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT
31
#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
/* CORECLKSEL */