shift_shift,lui_movf"
(const_string "unknown"))
+(define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
+ (const_string "unknown"))
+
;; Main data type used by the insn
(define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
(const_string "unknown"))
(cond [(eq_attr "jal" "!unset") (const_string "call")
(eq_attr "got" "load") (const_string "load")
+ (eq_attr "alu_type" "add,sub") (const_string "arith")
+
+ (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
+
;; If a doubleword move uses these expensive instructions,
;; it is usually better to schedule them in the same way
;; as the singleword form, rather than as "multi".
"@
<d>addu\t%0,%1,%2
<d>addiu\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "add")
(set_attr "mode" "<MODE>")])
(define_insn "*add<mode>3_mips16"
<d>addiu\t%0,%2
<d>addiu\t%0,%1,%2
<d>addu\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "add")
(set_attr "mode" "<MODE>")
(set_attr_alternative "length"
[(if_then_else (match_operand 2 "m16_simm8_8")
"@
addu\t%0,%1,%2
addiu\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "add")
(set_attr "mode" "SI")])
;; Split this insn so that the addiu splitters can have a crack at it.
"&& reload_completed"
[(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
{ operands[3] = gen_lowpart (SImode, operands[0]); }
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "add")
(set_attr "mode" "SI")
(set_attr "extended_mips16" "yes")])
(match_operand:SI 2 "register_operand" "d")) 3)))]
"ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
"baddu\\t%0,%1,%2"
- [(set_attr "type" "arith")])
+ [(set_attr "alu_type" "add")])
(define_insn "*baddu_si_el"
[(set (match_operand:SI 0 "register_operand" "=d")
(match_operand:SI 2 "register_operand" "d")) 0)))]
"ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
"baddu\\t%0,%1,%2"
- [(set_attr "type" "arith")])
+ [(set_attr "alu_type" "add")])
(define_insn "*baddu_di<mode>"
[(set (match_operand:GPR 0 "register_operand" "=d")
(match_operand:DI 2 "register_operand" "d")))))]
"ISA_HAS_BADDU && TARGET_64BIT"
"baddu\\t%0,%1,%2"
- [(set_attr "type" "arith")])
+ [(set_attr "alu_type" "add")])
\f
;;
;; ....................
(match_operand:GPR 2 "register_operand" "d")))]
""
"<d>subu\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "sub")
(set_attr "mode" "<MODE>")])
(define_insn "*subsi3_extended"
(match_operand:SI 2 "register_operand" "d"))))]
"TARGET_64BIT"
"subu\t%0,%1,%2"
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "sub")
(set_attr "mode" "DI")])
\f
;;
else
return "subu\t%0,%.,%1";
}
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "sub")
(set_attr "mode" "SI")])
(define_insn "negdi2"
(neg:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && !TARGET_MIPS16"
"dsubu\t%0,%.,%1"
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "sub")
(set_attr "mode" "DI")])
;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
else
return "nor\t%0,%.,%1";
}
- [(set_attr "type" "logical")
+ [(set_attr "alu_type" "not")
(set_attr "mode" "<MODE>")])
\f
;;
"@
or\t%0,%1,%2
ori\t%0,%1,%x2"
- [(set_attr "type" "logical")
+ [(set_attr "alu_type" "or")
(set_attr "mode" "<MODE>")])
(define_insn "*ior<mode>3_mips16"
(match_operand:GPR 2 "register_operand" "d")))]
"TARGET_MIPS16"
"or\t%0,%2"
- [(set_attr "type" "logical")
+ [(set_attr "alu_type" "or")
(set_attr "mode" "<MODE>")])
(define_expand "xor<mode>3"
"@
xor\t%0,%1,%2
xori\t%0,%1,%x2"
- [(set_attr "type" "logical")
+ [(set_attr "alu_type" "xor")
(set_attr "mode" "<MODE>")])
(define_insn ""
xor\t%0,%2
cmpi\t%1,%2
cmp\t%1,%2"
- [(set_attr "type" "logical,arith,arith")
+ [(set_attr "alu_type" "xor")
(set_attr "mode" "<MODE>")
(set_attr_alternative "length"
[(const_int 4)
(not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
"!TARGET_MIPS16"
"nor\t%0,%1,%2"
- [(set_attr "type" "logical")
+ [(set_attr "alu_type" "nor")
(set_attr "mode" "<MODE>")])
\f
;;
operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
return "andi\t%0,%1,%x2";
}
- [(set_attr "type" "logical")
+ [(set_attr "alu_type" "and")
(set_attr "mode" "<GPR:MODE>")])
(define_insn "*zero_extendhi_truncqi"
(truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
"TARGET_64BIT && !TARGET_MIPS16"
"andi\t%0,%1,0xff"
- [(set_attr "type" "logical")
+ [(set_attr "alu_type" "and")
(set_attr "mode" "HI")])
\f
;;
(match_operand:P 2 "immediate_operand" "")))]
"!TARGET_MIPS16"
"<d>addiu\t%0,%1,%R2"
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "add")
(set_attr "mode" "<MODE>")])
(define_insn "*low<mode>_mips16"
(match_operand:P 2 "immediate_operand" "")))]
"TARGET_MIPS16"
"<d>addiu\t%0,%R2"
- [(set_attr "type" "arith")
+ [(set_attr "alu_type" "add")
(set_attr "mode" "<MODE>")
(set_attr "extended_mips16" "yes")])