+2005-08-19 Eric Christopher <echristo@apple.com>
+
+ * optabs.h: Change CTI_ to COI_.
+ * optabs.c: Ditto.
+
2005-08-19 James E Wilson <wilson@specifix.com>
* builtins.c (expand_builtin_return_addr): Set
block or not.
(if_convertible_loop_p): Supply exit block itself to
if_convertible_bb_p.
-
+
2005-08-19 Richard Earnshaw <richard.earnshaw@arm.com>
PR target/23473
* arm.md (arm_load_pic_register): Change argument to the mask of
- saved registers. Call thumb_find_work_register if we need a
+ saved registers. Call thumb_find_work_register if we need a
scratch register on Thumb.
- (arm_expand_prologue): Pass empty register set to
+ (arm_expand_prologue): Pass empty register set to
arm_load_pic_register.
(thumb_expand_prologue): Pass live_regs_mask directly to
arm_load_pic_register.
(plus_gtu<mode>): Same.
2005-08-17 Erik Christiansen <erik@dd.nec.com.au>
-
+
* config/v850/lib1funcs.asm (callt_save_interrupt): Fix comment typos.
Move call_table_data to end. Delete spurious .text.
(callt_save_all_interrupt): Fix comment typo.
* config.gcc: Added z9-109 switch.
* config/s390/2084.md ("x_int", "x_agen", "x_lr", "x_la", "x_larl",
"x_load", "x_store", "x_branch", "x_call", "x_mul_hi", "x_mul_sidi",
- "x_div", "x_sem", "x_cs", "x_vs", "x_stm", "x_lm", "x_other",
- "x_fsimpdf", "x_fsimpsf", "x_fdivdf", "x_fdivsf", "x_floaddf",
+ "x_div", "x_sem", "x_cs", "x_vs", "x_stm", "x_lm", "x_other",
+ "x_fsimpdf", "x_fsimpsf", "x_fdivdf", "x_fdivsf", "x_floaddf",
"x_floadsf", "x_fstore_df", "x_fstoresf", "x_ftoi", "x_itof"): Enable
for "z9_109" cpu attribute.
* config/s390/s390.c (z9_109_cost): New processor cost structure.
(CONSTRAINT_LEN): Added length of O constraint.
(CLZ_DEFINED_VALUE_AT_ZERO): Definition added.
* config/s390/s390.md ("cpu"): New value z9_109 added.
- ("*tstdi_extimm", "*tstdi_ccconly_extimm", "*tstsi_extimm",
+ ("*tstdi_extimm", "*tstdi_ccconly_extimm", "*tstsi_extimm",
"*tstsi_cconly_extimm", "*movdi_64extimm", "*extendhidi2_extimm",
"*extendqidi2_extimm", "*extendhisi2_extimm", "*extendqisi2_extimm",
"*zero_extend<mode>si2_extimm", "*anddi3_extimm", "*iordi3_extimm",
"*addsi3_carry1_cc", "*addsi3_carry2_cc", "*addsi3_cc", "addsi3",
"*andsi3_cc", "*andsi3_cconly", "*andsi3_zarch", "*iorsi3_cc",
"*iorsi3_cconly", "*iorsi3_zarch", "*xorsi3_cc", "*xorsi3_cconly",
- "*xorsi3", "*xorhi3", "*xorqi3"): Added instruction using extended
+ "*xorsi3", "*xorhi3", "*xorqi3"): Added instruction using extended
immediates.
("extend<mode>di2", "extend<mode>si2", "zero_extend<mode>di2",
"zero_extend<mode>si2"): Allow memory operands and don't manually emit
2005-08-15 Richard Earnshaw <richard.earnshaw@arm.com>
PR target/23355
- * arm.c (thumb_compute_save_reg_mask): Use similar logic to
+ * arm.c (thumb_compute_save_reg_mask): Use similar logic to
arm_compure_save_reg0_reg12_mask to determine when the PIC register
must be saved.
* aclocal.m4 (gcc_AC_FUNC_PRINTF_PTR): Delete.
* configure.ac: Don't call gcc_AC_FUNC_PRINTF_PTR.
* system.h (HOST_PTR_PRINTF): Don't define, poison it.
-
+
* bitmap.c, c-decl.c, config/i386/i386-interix.h,
config/iq2000/iq2000.c, mips-tfile.c, print-rtl.c, print-tree.c:
Delete HOST_PTR_PRINTF.
PR 23386
* tree-data-ref.c (estimate_niter_from_size_of_data): When
step is negative compute the estimation from init downwards to zero.
-
+
2005-08-14 James A. Morrison <phython@gcc.gnu.org>
* fold-const (fold_binary): Call fold_build2 instead of fold (build.
2005-08-14 Daniel Berlin <dberlin@dberlin.org>
Fix PR tree-optimization/22615
-
+
* tree-ssa-structalias.c (solution_set_add): Handle
- first_vi_for_offset returning NULL.
+ first_vi_for_offset returning NULL.
(do_da_constraint): Ditto.
(do_sd_constraint): Ditto.
(do_ds_constraint): Ditto
(build_constraint_graph): RHS is allowed be ANYTHING.
(first_vi_for_offset): Return NULL if we couldn't find anything at
the offset.
-
+
2005-08-14 Ulrich Weigand <uweigand@de.ibm.com>
* config/s390/s390.c (s390_canonicalize_comparison): Prefer register
2005-08-14 Ira Rosen <irar@il.ibm.com>
PR tree-optimization/23320
- * tree-data-ref.c (base_addr_differ_p): Add comment. Check
- data-refs' types instead of base object nullness. Add check for
- pointer type data-refs before first location comparison. Remove
+ * tree-data-ref.c (base_addr_differ_p): Add comment. Check
+ data-refs' types instead of base object nullness. Add check for
+ pointer type data-refs before first location comparison. Remove
assert.
2005-08-14 Andreas Schwab <schwab@suse.de>
* tree-flow-inline.h (single_ssa_tree_operand, single_ssa_use_operand,
single_ssa_def_operand, zero_ssa_operands): Fix documentation.
* tree-flow.h (scev_probably_wraps_p): Declare with an extra parameter.
- * tree-scalar-evolution.c (instantiate_parameters_1): Factor entry
+ * tree-scalar-evolution.c (instantiate_parameters_1): Factor entry
condition.
* tree-ssa-loop-ivcanon.c: Fix documentation.
* tree-ssa-loop-ivopts.c (idx_find_step): Add a fixme note.
2005-08-12 Gerald Pfeifer <gerald@pfeifer.com>
- * doc/invoke.texi (C++ Dialect Options): Add dynamic_cast to
+ * doc/invoke.texi (C++ Dialect Options): Add dynamic_cast to
description of -Wold-style-casts.
2005-08-12 Andreas Krebbel <krebbel1@de.ibm.com>
2005-08-12 Andreas Krebbel <krebbel1@de.ibm.com>
- * config/s390/s390.c (s390_split_branches, s390_init_frame_layout):
+ * config/s390/s390.c (s390_split_branches, s390_init_frame_layout):
Don't set save_return_addr_p.
(s390_register_info): Make clobbered_regs not depending on
save_return_addr_p.
rtx libfunc_table[LTI_MAX];
/* Tables of patterns for converting one mode to another. */
-convert_optab convert_optab_table[CTI_MAX];
+convert_optab convert_optab_table[COI_MAX];
/* Contains the optab used for each rtx code. */
optab code_to_optab[NUM_RTX_CODE + 1];
this may or may not be TARGET. */
rtx
-expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0,
- rtx op1, rtx op2, rtx target, int unsignedp)
+expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0,
+ rtx op1, rtx op2, rtx target, int unsignedp)
{
int icode = (int) ternary_optab->handlers[(int) mode].insn_code;
enum machine_mode mode0 = insn_data[icode].operand[1].mode;
if (GET_MODE (op0) != mode0 && mode0 != VOIDmode)
xop0 = convert_modes (mode0,
GET_MODE (op0) != VOIDmode
- ? GET_MODE (op0)
+ ? GET_MODE (op0)
: mode,
xop0, unsignedp);
/* Now, if insn's predicates don't allow our operands, put them into
pseudo regs. */
-
+
if (!insn_data[icode].operand[1].predicate (xop0, mode0)
- && mode0 != VOIDmode)
+ && mode0 != VOIDmode)
xop0 = copy_to_mode_reg (mode0, xop0);
-
+
if (!insn_data[icode].operand[2].predicate (xop1, mode1)
&& mode1 != VOIDmode)
xop1 = copy_to_mode_reg (mode1, xop1);
-
+
if (!insn_data[icode].operand[3].predicate (xop2, mode2)
&& mode2 != VOIDmode)
xop2 = copy_to_mode_reg (mode2, xop2);
-
+
pat = GEN_FCN (icode) (temp, xop0, xop1, xop2);
-
+
emit_insn (pat);
- return temp;
+ return temp;
}
return 0;
}
-/* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
+/* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
conditions, VAL may already be a SUBREG against which we cannot generate
a further SUBREG. In this case, we expect forcing the value into a
register will work around the situation. */
{
rtx targ_piece = operand_subword (target, i, 1, mode);
rtx op0_piece = operand_subword_force (op0, i, mode);
-
+
if (i == word)
{
temp = expand_binop (imode, code == ABS ? and_optab : xor_optab,
{
rtx targ_piece = operand_subword (target, i, 1, mode);
rtx op0_piece = operand_subword_force (op0, i, mode);
-
+
if (i == word)
{
if (!op0_is_abs)
return target;
}
-/* Expand the C99 copysign operation. OP0 and OP1 must be the same
+/* Expand the C99 copysign operation. OP0 and OP1 must be the same
scalar floating point mode. Return NULL if we do not know how to
expand the operation inline. */
}
/* Dump the conversion optabs. */
- for (i = 0; i < (int) CTI_MAX; ++i)
+ for (i = 0; i < (int) COI_MAX; ++i)
for (j = 0; j < NUM_MACHINE_MODES; ++j)
for (k = 0; k < NUM_MACHINE_MODES; ++k)
{
case GE_EXPR:
code = unsignedp ? GEU : GE;
break;
-
+
case UNORDERED_EXPR:
code = UNORDERED;
break;
ensures that condition is a relational operation. */
gcc_assert (COMPARISON_CLASS_P (cond));
- rcode = get_rtx_code (TREE_CODE (cond), unsignedp);
+ rcode = get_rtx_code (TREE_CODE (cond), unsignedp);
t_op0 = TREE_OPERAND (cond, 0);
t_op1 = TREE_OPERAND (cond, 1);
-
+
/* Expand operands. */
rtx_op0 = expand_expr (t_op0, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op0)), 1);
rtx_op1 = expand_expr (t_op1, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op1)), 1);
if (!insn_data[icode].operand[4].predicate (rtx_op0, GET_MODE (rtx_op0))
&& GET_MODE (rtx_op0) != VOIDmode)
rtx_op0 = force_reg (GET_MODE (rtx_op0), rtx_op0);
-
+
if (!insn_data[icode].operand[5].predicate (rtx_op1, GET_MODE (rtx_op1))
&& GET_MODE (rtx_op1) != VOIDmode)
rtx_op1 = force_reg (GET_MODE (rtx_op1), rtx_op1);
}
/* Return insn code for VEC_COND_EXPR EXPR. */
-
-static inline enum insn_code
+
+static inline enum insn_code
get_vcond_icode (tree expr, enum machine_mode mode)
{
enum insn_code icode = CODE_FOR_nothing;
target = gen_reg_rtx (mode);
/* Get comparison rtx. First expand both cond expr operands. */
- comparison = vector_compare_rtx (TREE_OPERAND (vec_cond_expr, 0),
+ comparison = vector_compare_rtx (TREE_OPERAND (vec_cond_expr, 0),
unsignedp, icode);
cc_op0 = XEXP (comparison, 0);
cc_op1 = XEXP (comparison, 1);
rtx_op2 = force_reg (mode, rtx_op2);
/* Emit instruction! */
- emit_insn (GEN_FCN (icode) (target, rtx_op1, rtx_op2,
+ emit_insn (GEN_FCN (icode) (target, rtx_op1, rtx_op2,
comparison, cc_op0, cc_op1));
return target;
}
}
- /* Without an appropriate setcc instruction, use a set of branches to
- get 1 and 0 stored into target. Presumably if the target has a
+ /* Without an appropriate setcc instruction, use a set of branches to
+ get 1 and 0 stored into target. Presumably if the target has a
STORE_FLAG_VALUE that isn't 1, then this will get cleaned up by ifcvt. */
label0 = gen_label_rtx ();
}
/* This function generates the atomic operation MEM CODE= VAL. In this
- case, we do not care about any resulting value. Returns NULL if we
+ case, we do not care about any resulting value. Returns NULL if we
cannot generate the operation. */
rtx
val = convert_modes (mode, GET_MODE (val), val, 1);
if (!insn_data[icode].operand[1].predicate (val, mode))
val = force_reg (mode, val);
-
+
insn = GEN_FCN (icode) (mem, val);
if (insn)
{
/* This function generates the atomic operation MEM CODE= VAL. In this
case, we do care about the resulting value: if AFTER is true then
- return the value MEM holds after the operation, if AFTER is false
+ return the value MEM holds after the operation, if AFTER is false
then return the value MEM holds before the operation. TARGET is an
optional place for the result value to be stored. */
val = convert_modes (mode, GET_MODE (val), val, 1);
if (!insn_data[icode].operand[2].predicate (val, mode))
val = force_reg (mode, val);
-
+
insn = GEN_FCN (icode) (target, mem, val);
if (insn)
{
/* This function expands a test-and-set operation. Ideally we atomically
store VAL in MEM and return the previous value in MEM. Some targets
may not support this operation and only support VAL with the constant 1;
- in this case while the return value will be 0/1, but the exact value
+ in this case while the return value will be 0/1, but the exact value
stored in MEM is target defined. TARGET is an option place to stick
the return value. */
/* Conversion optabs have their own table and indexes. */
enum convert_optab_index
{
- CTI_sext,
- CTI_zext,
- CTI_trunc,
+ COI_sext,
+ COI_zext,
+ COI_trunc,
- CTI_sfix,
- CTI_ufix,
+ COI_sfix,
+ COI_ufix,
- CTI_sfixtrunc,
- CTI_ufixtrunc,
+ COI_sfixtrunc,
+ COI_ufixtrunc,
- CTI_sfloat,
- CTI_ufloat,
+ COI_sfloat,
+ COI_ufloat,
- CTI_MAX
+ COI_MAX
};
-extern GTY(()) convert_optab convert_optab_table[CTI_MAX];
+extern GTY(()) convert_optab convert_optab_table[COI_MAX];
-#define sext_optab (convert_optab_table[CTI_sext])
-#define zext_optab (convert_optab_table[CTI_zext])
-#define trunc_optab (convert_optab_table[CTI_trunc])
-#define sfix_optab (convert_optab_table[CTI_sfix])
-#define ufix_optab (convert_optab_table[CTI_ufix])
-#define sfixtrunc_optab (convert_optab_table[CTI_sfixtrunc])
-#define ufixtrunc_optab (convert_optab_table[CTI_ufixtrunc])
-#define sfloat_optab (convert_optab_table[CTI_sfloat])
-#define ufloat_optab (convert_optab_table[CTI_ufloat])
+#define sext_optab (convert_optab_table[COI_sext])
+#define zext_optab (convert_optab_table[COI_zext])
+#define trunc_optab (convert_optab_table[COI_trunc])
+#define sfix_optab (convert_optab_table[COI_sfix])
+#define ufix_optab (convert_optab_table[COI_ufix])
+#define sfixtrunc_optab (convert_optab_table[COI_sfixtrunc])
+#define ufixtrunc_optab (convert_optab_table[COI_ufixtrunc])
+#define sfloat_optab (convert_optab_table[COI_sfloat])
+#define ufloat_optab (convert_optab_table[COI_ufloat])
/* These arrays record the insn_code of insns that may be needed to
perform input and output reloads of special objects. They provide a
/* Define functions given in optabs.c. */
-extern rtx expand_ternary_op (enum machine_mode mode, optab ternary_optab,
- rtx op0, rtx op1, rtx op2, rtx target,
+extern rtx expand_ternary_op (enum machine_mode mode, optab ternary_optab,
+ rtx op0, rtx op1, rtx op2, rtx target,
int unsignedp);
/* Expand a binary operation given optab and rtx operands. */
projects / platform / upstream / linaro-gcc.git / commitdiff