drm/msm/dp: set stream_pixel rate directly
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 17 Feb 2022 05:55:27 +0000 (08:55 +0300)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Mon, 4 Jul 2022 18:05:28 +0000 (21:05 +0300)
The only clock for which we set the rate is the "stream_pixel". Rather
than storing the rate and then setting it by looping over all the
clocks, set the clock rate directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/474714/
Link: https://lore.kernel.org/r/20220217055529.499829-4-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
drivers/gpu/drm/msm/dp/dp_clk_util.c
drivers/gpu/drm/msm/dp/dp_clk_util.h
drivers/gpu/drm/msm/dp/dp_ctrl.c
drivers/gpu/drm/msm/dp/dp_parser.c
drivers/gpu/drm/msm/dp/dp_power.c

index 44a4fc5..85abed3 100644 (file)
@@ -51,39 +51,6 @@ error:
        return rc;
 }
 
-int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk)
-{
-       int i, rc = 0;
-
-       for (i = 0; i < num_clk; i++) {
-               if (clk_arry[i].clk) {
-                       if (clk_arry[i].type != DSS_CLK_AHB) {
-                               DEV_DBG("%pS->%s: '%s' rate %ld\n",
-                                       __builtin_return_address(0), __func__,
-                                       clk_arry[i].clk_name,
-                                       clk_arry[i].rate);
-                               rc = clk_set_rate(clk_arry[i].clk,
-                                       clk_arry[i].rate);
-                               if (rc) {
-                                       DEV_ERR("%pS->%s: %s failed. rc=%d\n",
-                                               __builtin_return_address(0),
-                                               __func__,
-                                               clk_arry[i].clk_name, rc);
-                                       break;
-                               }
-                       }
-               } else {
-                       DEV_ERR("%pS->%s: '%s' is not available\n",
-                               __builtin_return_address(0), __func__,
-                               clk_arry[i].clk_name);
-                       rc = -EPERM;
-                       break;
-               }
-       }
-
-       return rc;
-}
-
 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable)
 {
        int i, rc = 0;
index 067bf87..c3d59b5 100644 (file)
 #define DEV_WARN(fmt, args...)  pr_warn(fmt, ##args)
 #define DEV_ERR(fmt, args...)   pr_err(fmt, ##args)
 
-enum dss_clk_type {
-       DSS_CLK_AHB, /* no set rate. rate controlled through rpm */
-       DSS_CLK_PCLK,
-};
-
 struct dss_clk {
        struct clk *clk; /* clk handle */
        char clk_name[32];
-       enum dss_clk_type type;
-       unsigned long rate;
-       unsigned long max_rate;
 };
 
 struct dss_module_power {
@@ -33,6 +25,5 @@ struct dss_module_power {
 
 int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
 void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
-int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
 int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
 #endif /* __DP_CLK_UTIL_H__ */
index 4a9e4f0..7483396 100644 (file)
@@ -1332,7 +1332,7 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
                                                rate, name);
 
        if (num)
-               cfg->rate = rate;
+               clk_set_rate(cfg->clk, rate);
        else
                DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
                                name, rate);
index 8f9fed9..fc3d88c 100644 (file)
@@ -237,14 +237,12 @@ static int dp_parser_clock(struct dp_parser *parser)
                        struct dss_clk *clk =
                                &core_power->clk_config[core_clk_index];
                        strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
-                       clk->type = DSS_CLK_AHB;
                        core_clk_index++;
                } else if (dp_parser_check_prefix("stream", clk_name) &&
                                stream_clk_index < stream_clk_count) {
                        struct dss_clk *clk =
                                &stream_power->clk_config[stream_clk_index];
                        strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
-                       clk->type = DSS_CLK_PCLK;
                        stream_clk_index++;
                } else if (dp_parser_check_prefix("ctrl", clk_name) &&
                           ctrl_clk_index < ctrl_clk_count) {
@@ -252,11 +250,6 @@ static int dp_parser_clock(struct dp_parser *parser)
                                &ctrl_power->clk_config[ctrl_clk_index];
                        strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
                        ctrl_clk_index++;
-                       if (dp_parser_check_prefix("ctrl_link", clk_name) ||
-                           dp_parser_check_prefix("stream_pixel", clk_name))
-                               clk->type = DSS_CLK_PCLK;
-                       else
-                               clk->type = DSS_CLK_AHB;
                }
        }
 
index ccb7c42..ffb84ed 100644 (file)
@@ -157,16 +157,6 @@ static int dp_power_clk_set_rate(struct dp_power_private *power,
        int rc = 0;
        struct dss_module_power *mp = &power->parser->mp[module];
 
-       if (module != DP_CTRL_PM) {
-               if (enable) {
-                       rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
-                       if (rc) {
-                               DRM_ERROR("failed to set clks rate\n");
-                               return rc;
-                       }
-               }
-       }
-
        rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable);
        if (rc) {
                DRM_ERROR("failed to %d clks, err: %d\n", enable, rc);