void
fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
{
- brw_inst *insn;
-
- /* WaClearTDRRegBeforeEOTForNonPS.
- *
- * WA: Clear tdr register before send EOT in all non-PS shader kernels
- *
- * mov(8) tdr0:ud 0x0:ud {NoMask}"
- */
- if (inst->eot && p->devinfo->gen == 10) {
- brw_push_insn_state(p);
- brw_set_default_mask_control(p, BRW_MASK_DISABLE);
- brw_MOV(p, brw_tdr_reg(), brw_imm_uw(0));
- brw_pop_insn_state(p);
- }
-
- insn = brw_next_insn(p, BRW_OPCODE_SEND);
+ brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, insn, brw_null_reg());
brw_set_src0(p, insn, payload);
case 7: return devinfo->is_haswell ? GEN75 : GEN7;
case 8: return GEN8;
case 9: return GEN9;
- case 10: return GEN10;
case 11: return GEN11;
case 12: return GEN12;
default:
/* URB entry sizes are stored as a multiple of 64 bytes. */
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
- /* On Cannonlake software shall not program an allocation size that
- * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
- */
- if (devinfo->gen == 10 &&
- prog_data->base.urb_entry_size % 3 == 0)
- prog_data->base.urb_entry_size++;
-
prog_data->base.urb_read_length = 0;
STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 8);
} else {
prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4);
- /* On Cannonlake software shall not program an allocation size that
- * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
- */
- if (compiler->devinfo->gen == 10 &&
- prog_data->base.urb_entry_size % 3 == 0)
- prog_data->base.urb_entry_size++;
}
if (INTEL_DEBUG & DEBUG_VS) {
*/
if (compiler->devinfo->gen >= 7) {
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
- /* On Cannonlake software shall not program an allocation size that
- * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
- */
- if (compiler->devinfo->gen == 10 &&
- prog_data->base.urb_entry_size % 3 == 0)
- prog_data->base.urb_entry_size++;
} else {
prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 128) / 128;
}
/* URB entry sizes are stored as a multiple of 64 bytes. */
vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
- /* On Cannonlake software shall not program an allocation size that
- * specifies a size that is a multiple of 3 64B (512-bit) cachelines.
- */
- if (devinfo->gen == 10 &&
- vue_prog_data->urb_entry_size % 3 == 0)
- vue_prog_data->urb_entry_size++;
-
/* HS does not use the usual payload pushing from URB to GRFs,
* because we don't have enough registers for a full-size payload, and
* the hardware is broken on Haswell anyway.
}
int
-main(int argc, char **argv)
+main(UNUSED int argc, UNUSED char **argv)
{
struct gen_device_info *devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
bool fail = false;
for (devinfo->gen = 5; devinfo->gen <= 12; devinfo->gen++) {
+ if (devinfo->gen == 10)
+ continue;
+
fail |= run_tests(devinfo);
}
{ "glk", },
{ "cfl", },
{ "whl", },
- { "cnl", },
{ "icl", },
{ "tgl", },
};
/* There are no ternary instructions that can operate on B-type sources
* on Gen11-12. Src1/Src2 cannot be B-typed either.
*/
- { BRW_REGISTER_TYPE_B, E(INT), devinfo.gen == 10 },
- { BRW_REGISTER_TYPE_UB, E(INT), devinfo.gen == 10 },
+ { BRW_REGISTER_TYPE_B, E(INT), false },
+ { BRW_REGISTER_TYPE_UB, E(INT), false },
};
/* Initially assume all hardware encodings are invalid */