intel/compiler: Lower integer division on XeHP.

It has been removed from the hardware.

[jordan.l.justen@intel.com: Move to brw_postprocess_nir]

v2: Switch to nir_lower_idiv_precise (Rhys).
v3: Fix for interface changes of nir_lower_idiv.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>

diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index f3799b1..447f17b 100644 (file)
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -2260,6 +2260,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
       case SHADER_OPCODE_INT_QUOTIENT:
       case SHADER_OPCODE_INT_REMAINDER:
       case SHADER_OPCODE_POW:
+         assert(devinfo->verx10 < 125);
          assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
          if (devinfo->ver >= 6) {
             assert(inst->mlen == 0);

diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 2f0cc63..1dd8d5e 100644 (file)
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -1100,6 +1100,14 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
       OPT(nir_opt_algebraic_before_ffma);
    } while (progress);
 
+   if (devinfo->verx10 >= 125) {
+      const nir_lower_idiv_options options = {
+         .imprecise_32bit_lowering = false,
+         .allow_fp16 = false
+      };
+      OPT(nir_lower_idiv, &options);
+   }
+
    brw_nir_optimize(nir, compiler, is_scalar, false);
 
    if (is_scalar && nir_shader_has_local_variables(nir)) {