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clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
author
Dario Binacchi
<dario.binacchi@amarulasolutions.com>
Thu, 17 Nov 2022 11:36:37 +0000
(12:36 +0100)
committer
Abel Vesa
<abel.vesa@linaro.org>
Fri, 25 Nov 2022 09:18:33 +0000
(11:18 +0200)
According to the "Clock Root" table of the reference manual (document
IMX8MNRM Rev 2, 07/2022):
Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX])
... ... ...
ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK
001 - SYSTEM_PLL2_DIV20
010 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL2_DIV2
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
111 - AUDIO_PLL2_CLK
... ... ...
while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
source select bits 101b.
Fixes:
96d6392b54dbb
("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link:
https://lore.kernel.org/r/20221117113637.1978703-6-dario.binacchi@amarulasolutions.com
drivers/clk/imx/clk-imx8mn.c
patch
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diff --git
a/drivers/clk/imx/clk-imx8mn.c
b/drivers/clk/imx/clk-imx8mn.c
index
37128c3
..
2afea90
100644
(file)
--- a/
drivers/clk/imx/clk-imx8mn.c
+++ b/
drivers/clk/imx/clk-imx8mn.c
@@
-140,8
+140,8
@@
static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m"
"clk_ext4", "video_pll_out", };
static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
- "sys_pll2_200m", "sys_pll2_500m", "
video_pll
_out",
- "audio_pll2_out", };
+ "sys_pll2_200m", "sys_pll2_500m", "
audio_pll1
_out",
+ "
video_pll_out", "
audio_pll2_out", };
static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",