drm/i915/psr: Use intel_de_rmw()

Replace some hand rolled RMW stuff with intel_de_rmw().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230411191429.29895-5-ville.syrjala@linux.intel.com
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 04bac99..05cb65b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -232,13 +232,11 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir)
                            transcoder_name(cpu_transcoder));
 
                if (DISPLAY_VER(dev_priv) >= 9) {
-                       u32 val = intel_de_read(dev_priv,
-                                               PSR_EVENT(cpu_transcoder));
-                       bool psr2_enabled = intel_dp->psr.psr2_enabled;
+                       u32 val;
 
-                       intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder),
-                                      val);
-                       psr_event_print(dev_priv, val, psr2_enabled);
+                       val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0);
+
+                       psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);
                }
        }
 
@@ -493,9 +491,8 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
        if (DISPLAY_VER(dev_priv) >= 8)
                val |= EDP_PSR_CRC_ENABLE;
 
-       val |= (intel_de_read(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder)) &
-               EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK);
-       intel_de_write(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder), val);
+       intel_de_rmw(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder),
+                    ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val);
 }
 
 static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
@@ -1342,19 +1339,16 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 
        if (intel_dp->psr.psr2_enabled) {
                tgl_disallow_dc3co_on_psr2_exit(intel_dp);
-               val = intel_de_read(dev_priv,
-                                   EDP_PSR2_CTL(intel_dp->psr.transcoder));
+
+               val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(intel_dp->psr.transcoder),
+                                  EDP_PSR2_ENABLE, 0);
+
                drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE));
-               val &= ~EDP_PSR2_ENABLE;
-               intel_de_write(dev_priv,
-                              EDP_PSR2_CTL(intel_dp->psr.transcoder), val);
        } else {
-               val = intel_de_read(dev_priv,
-                                   EDP_PSR_CTL(intel_dp->psr.transcoder));
+               val = intel_de_rmw(dev_priv, EDP_PSR_CTL(intel_dp->psr.transcoder),
+                                  EDP_PSR_ENABLE, 0);
+
                drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE));
-               val &= ~EDP_PSR_ENABLE;
-               intel_de_write(dev_priv,
-                              EDP_PSR_CTL(intel_dp->psr.transcoder), val);
        }
        intel_dp->psr.active = false;
 }