freedreno/ir3: put the conversion back for half const to the right place.

The previous commit leads to match immed values unexpectedly.

This makes constlen for each shader including bvert wrong.
Also fixes atan2 for mediump deqp tests.

Fixes: cbd1f47433b ("freedreno/ir3: convert back to 32-bit values for half constant registers.")

v2: Move conversion up above fabs/fneg modifier handling as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3737>

diff --git a/src/freedreno/ir3/ir3_cp.c b/src/freedreno/ir3/ir3_cp.c
index b7fb86e..efcefae 100644 (file)
--- a/src/freedreno/ir3/ir3_cp.c
+++ b/src/freedreno/ir3/ir3_cp.c
@@ -305,6 +305,12 @@ lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags
 
        reg = ir3_reg_clone(ctx->shader, reg);
 
+       /* Half constant registers seems to handle only 32-bit values
+        * within floating-point opcodes. So convert back to 32-bit values.
+        */
+       if (f_opcode && (new_flags & IR3_REG_HALF))
+               reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
+
        /* in some cases, there are restrictions on (abs)/(neg) plus const..
         * so just evaluate those and clear the flags:
         */
@@ -350,12 +356,6 @@ lower_immed(struct ir3_cp_ctx *ctx, struct ir3_register *reg, unsigned new_flags
                swiz = i % 4;
                idx  = i / 4;
 
-               /* Half constant registers seems to handle only 32-bit values
-                * within floating-point opcodes. So convert back to 32-bit values. */
-               if (f_opcode && (new_flags & IR3_REG_HALF)) {
-                       reg->uim_val = fui(_mesa_half_to_float(reg->uim_val));
-               }
-
                const_state->immediates[idx].val[swiz] = reg->uim_val;
                const_state->immediates_count = idx + 1;
                const_state->immediate_idx++;