drm/i915/dg1: Define MOCS table for DG1

DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).

Bspec: 45101

v2: Reword the comment to state that the last few entries are reserved
    instead of "the last two". DG1 reserves four instead of two from
    previous platforms (from Matt Roper)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201007002210.3678024-3-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 632e08a4592b2caff85a7bed5141e06f30c0e2b9..8d0614d547bf34c02e5540b96b19ecb87e48751d 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -109,7 +109,7 @@ struct drm_i915_mocs_table {
  * they will be initialized to PTE. Gen >= 12 onwards don't have a setting for
  * PTE and will be initialized to an invalid value.
  *
- * The last two entries are reserved by the hardware. For ICL+ they
+ * The last few entries are reserved by the hardware. For ICL+ they
  * should be initialized according to bspec and never used, for older
  * platforms they should never be written to.
  *
@@ -280,6 +280,39 @@ static const struct drm_i915_mocs_entry icl_mocs_table[] = {
        GEN11_MOCS_ENTRIES
 };
 
+static const struct drm_i915_mocs_entry dg1_mocs_table[] = {
+       /* Error */
+       MOCS_ENTRY(0, 0, L3_0_DIRECT),
+
+       /* UC */
+       MOCS_ENTRY(1, 0, L3_1_UC),
+
+       /* Reserved */
+       MOCS_ENTRY(2, 0, L3_0_DIRECT),
+       MOCS_ENTRY(3, 0, L3_0_DIRECT),
+       MOCS_ENTRY(4, 0, L3_0_DIRECT),
+
+       /* WB - L3 */
+       MOCS_ENTRY(5, 0, L3_3_WB),
+       /* WB - L3 50% */
+       MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
+       /* WB - L3 25% */
+       MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
+       /* WB - L3 12.5% */
+       MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
+
+       /* HDC:L1 + L3 */
+       MOCS_ENTRY(48, 0, L3_3_WB),
+       /* HDC:L1 */
+       MOCS_ENTRY(49, 0, L3_1_UC),
+
+       /* HW Reserved */
+       MOCS_ENTRY(60, 0, L3_1_UC),
+       MOCS_ENTRY(61, 0, L3_1_UC),
+       MOCS_ENTRY(62, 0, L3_1_UC),
+       MOCS_ENTRY(63, 0, L3_1_UC),
+};
+
 enum {
        HAS_GLOBAL_MOCS = BIT(0),
        HAS_ENGINE_MOCS = BIT(1),
@@ -306,7 +339,11 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
 {
        unsigned int flags;
 
-       if (INTEL_GEN(i915) >= 12) {
+       if (IS_DG1(i915)) {
+               table->size = ARRAY_SIZE(dg1_mocs_table);
+               table->table = dg1_mocs_table;
+               table->n_entries = GEN11_NUM_MOCS_ENTRIES;
+       } else if (INTEL_GEN(i915) >= 12) {
                table->size  = ARRAY_SIZE(tgl_mocs_table);
                table->table = tgl_mocs_table;
                table->n_entries = GEN11_NUM_MOCS_ENTRIES;