nvc0: recognise ga10x chipsets
authorBen Skeggs <bskeggs@redhat.com>
Wed, 3 Nov 2021 23:50:42 +0000 (09:50 +1000)
committerMarge Bot <emma+marge@anholt.net>
Wed, 9 Nov 2022 21:21:22 +0000 (21:21 +0000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17633>

src/gallium/drivers/nouveau/nv_object.xml.h
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c

index 6cfc269..7931096 100644 (file)
@@ -197,6 +197,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GP102_3D_CLASS                                         0x0000c197
 #define GV100_3D_CLASS                                         0x0000c397
 #define TU102_3D_CLASS                                         0x0000c597
+#define GA102_3D_CLASS                                         0x0000c797
 #define NV50_2D_CLASS                                          0x0000502d
 #define NVC0_2D_CLASS                                          0x0000902d
 #define NV50_COMPUTE_CLASS                                     0x000050c0
@@ -211,6 +212,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define GP104_COMPUTE_CLASS                                    0x0000c1c0
 #define GV100_COMPUTE_CLASS                                    0x0000c3c0
 #define TU102_COMPUTE_CLASS                                    0x0000c5c0
+#define GA102_COMPUTE_CLASS                                    0x0000c7c0
 #define NV84_CRYPT_CLASS                                       0x000074c1
 #define BLOB_NVC0_PCOPY1_CLASS                                 0x000090b8
 #define BLOB_NVC0_PCOPY0_CLASS                                 0x000090b5
@@ -220,6 +222,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define PASCAL_DMA_COPY_B                                      0x0000c1b5
 #define VOLTA_DMA_COPY_A                                       0x0000c3b5
 #define TURING_DMA_COPY_A                                      0x0000c5b5
+#define AMPERE_DMA_COPY_A                                      0x0000c6b5
+#define AMPERE_DMA_COPY_B                                      0x0000c7b5
 #define NVE4_P2MF_CLASS                                                0x0000a040
 #define NVF0_P2MF_CLASS                                                0x0000a140
 #define NV31_MPEG_CLASS                                                0x00003174
index f949c32..8bafc09 100644 (file)
@@ -883,6 +883,7 @@ static int
 nvc0_screen_init_compute(struct nvc0_screen *screen)
 {
    const struct nouveau_mclass computes[] = {
+      { GA102_COMPUTE_CLASS, -1 },
       { TU102_COMPUTE_CLASS, -1 },
       { GV100_COMPUTE_CLASS, -1 },
       { GP104_COMPUTE_CLASS, -1 },
@@ -1073,6 +1074,7 @@ nvc0_screen_create(struct nouveau_device *dev)
    case 0x130:
    case 0x140:
    case 0x160:
+   case 0x170:
       break;
    default:
       return NULL;
@@ -1171,6 +1173,8 @@ nvc0_screen_create(struct nouveau_device *dev)
 
    if (screen->m2mf->oclass >= NVE4_P2MF_CLASS) {
       const struct nouveau_mclass copys[] = {
+         {  AMPERE_DMA_COPY_B, -1 },
+         {  AMPERE_DMA_COPY_A, -1 },
          {  TURING_DMA_COPY_A, -1 },
          {   VOLTA_DMA_COPY_A, -1 },
          {  PASCAL_DMA_COPY_B, -1 },
@@ -1219,6 +1223,7 @@ nvc0_screen_create(struct nouveau_device *dev)
    PUSH_DATA (push, screen->fence.bo->offset + 16);
 
    const struct nouveau_mclass threeds[] = {
+      { GA102_3D_CLASS, -1 },
       { TU102_3D_CLASS, -1 },
       { GV100_3D_CLASS, -1 },
       { GP102_3D_CLASS, -1 },
index e717fc1..3df4a67 100644 (file)
@@ -107,6 +107,7 @@ nouveau_drm_screen_create(int fd)
        case 0x130:
        case 0x140:
        case 0x160:
+       case 0x170:
                init = nvc0_screen_create;
                break;
        default: