&& getOperand(1).isImm();
}
- bool isPHI() const {
- return getOpcode() == TargetOpcode::PHI ||
- getOpcode() == TargetOpcode::G_PHI;
- }
+ bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
let hasSideEffects = 0;
}
-def G_TYPE : Instruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins unknown:$imm);
- let hasSideEffects = 0;
-}
-
//------------------------------------------------------------------------------
// Binary ops.
//------------------------------------------------------------------------------
let mayStore = 1;
}
-// PHI node bearing an LLT.
-def G_PHI : Instruction {
- let OutOperandList = (outs type0:$dst);
- let InOperandList = (ins variable_ops);
- let hasSideEffects = 0;
-}
-
//------------------------------------------------------------------------------
// Branches.
//------------------------------------------------------------------------------
/// Generic unsigned-int to float conversion
HANDLE_TARGET_OPCODE(G_UITOFP)
-/// Generic type specifier for untyped registers.
-HANDLE_TARGET_OPCODE(G_TYPE)
-
-/// Generic PHI node (so that the type of the vreg can be set).
-HANDLE_TARGET_OPCODE(G_PHI)
-
/// Generic BRANCH instruction. This is an unconditional branch.
HANDLE_TARGET_OPCODE(G_BR)
bool IRTranslator::translatePHI(const User &U) {
const PHINode &PI = cast<PHINode>(U);
- auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI);
+ auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
MIB.addDef(getOrCreateVReg(PI));
PendingPHIs.emplace_back(&PI, MIB.getInstr());
DefaultActions[TargetOpcode::G_ANYEXT] = Legal;
DefaultActions[TargetOpcode::G_TRUNC] = Legal;
- // G_TYPE and G_PHI are essentially an annotated COPY/PHI instructions so
- // they're always legal.
- DefaultActions[TargetOpcode::G_TYPE] = Legal;
- DefaultActions[TargetOpcode::G_PHI] = Legal;
-
DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;
bool CompleteMapping = true;
// For copies we want to walk over the operands and try to find one
// that has a register bank.
- bool isCopyLike =
- MI.isCopy() || MI.isPHI() || MI.getOpcode() == TargetOpcode::G_TYPE;
+ bool isCopyLike = MI.isCopy() || MI.isPHI();
// Remember the register bank for reuse for copy-like instructions.
const RegisterBank *RegBank = nullptr;
// Remember the size of the register for reuse for copy-like instructions.
}
// Generic opcodes must not have physical register operands.
- if (isPreISelGenericOpcode(MCID.getOpcode()) &&
- MCID.getOpcode() != TargetOpcode::G_TYPE) {
+ if (isPreISelGenericOpcode(MCID.getOpcode())) {
for (auto &Op : MI->operands()) {
if (Op.isReg() && TargetRegisterInfo::isPhysicalRegister(Op.getReg()))
report("Generic instruction cannot have physical register", MI);
return true;
}
- case TargetOpcode::G_TYPE: {
- I.setDesc(TII.get(TargetOpcode::COPY));
- return true;
- }
-
- case TargetOpcode::G_PHI: {
- I.setDesc(TII.get(TargetOpcode::PHI));
- return true;
- }
-
case TargetOpcode::G_FRAME_INDEX: {
// allocas and G_FRAME_INDEX are only supported in addrspace(0).
if (Ty != LLT::pointer(0)) {
; CHECK: [[FALSE]]:
; CHECK: [[RES2:%[0-9]+]](s32) = G_LOAD
-; CHECK: [[RES:%[0-9]+]](s32) = G_PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
+; CHECK: [[RES:%[0-9]+]](s32) = PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
; CHECK: %w0 = COPY [[RES]]
define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
br i1 %tst, label %true, label %false
; CHECK-LABEL: name: test_scalar_and_small
; CHECK: %4(s8) = G_AND %2, %3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x1
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_AND %2, %3
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- %0(s64) = G_TYPE %x0
+ %0(s64) = COPY %x0
; CHECK: %1(s1) = G_TRUNC %0
; CHECK: %2(s8) = G_TRUNC %0
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x0
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x0
%2(s32) = G_TRUNC %0
%3(s32) = G_TRUNC %1
bb.0:
liveins: %x0
; CHECK-LABEL: name: test_copy
- ; CHECK: %0(s64) = G_TYPE %x0
+ ; CHECK: %0(s64) = COPY %x0
; CHECK-NEXT: %x0 = COPY %0
- %0(s64) = G_TYPE %x0
+ %0(s64) = COPY %x0
%x0 = COPY %0
...
; CHECK-LABEL: name: test_scalar_mul_small
; CHECK: %4(s8) = G_MUL %2, %3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x1
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_MUL %2, %3
; CHECK-LABEL: name: test_scalar_or_small
; CHECK: %4(s8) = G_OR %2, %3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x1
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_OR %2, %3
; CHECK-LABEL: name: test_scalar_xor_small
; CHECK: %4(s8) = G_XOR %2, %3
- %0(s64) = G_TYPE %x0
- %1(s64) = G_TYPE %x1
+ %0(s64) = COPY %x0
+ %1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
%4(s8) = G_XOR %2, %3
...
---
# CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function ***
-# CHECK: instruction: %vreg0<def>(s64) = G_TYPE
+# CHECK: instruction: %vreg0<def>(s64) = COPY
# CHECK: operand 0: %vreg0<def>
name: test
regBankSelected: true
body: |
bb.0:
liveins: %x0
- %0(s64) = G_TYPE %x0
+ %0(s64) = COPY %x0
...
body: |
bb.0:
liveins: %x0
- %0 = G_TYPE %x0
+ %0 = COPY %x0
; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function ***
; CHECK: instruction: %vreg1<def> = G_ADD