GlobalISel: remove G_TYPE and G_PHI

These instructions were only necessary when type information was stored in the
MachineInstr (because only generic MachineInstrs possessed a type). Now that
it's in MachineRegisterInfo, COPY and PHI work fine.

llvm-svn: 281037

diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index e487f94..aefb40e 100644 (file)
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -779,10 +779,7 @@ public:
       && getOperand(1).isImm();
   }
 
-  bool isPHI() const {
-    return getOpcode() == TargetOpcode::PHI ||
-           getOpcode() == TargetOpcode::G_PHI;
-  }
+  bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
   bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
   bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
   bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }

diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index b9ce8a8..8bdf8e0 100644 (file)
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -85,12 +85,6 @@ def G_FCONSTANT : Instruction {
   let hasSideEffects = 0;
 }
 
-def G_TYPE : Instruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins unknown:$imm);
-  let hasSideEffects = 0;
-}
-
 //------------------------------------------------------------------------------
 // Binary ops.
 //------------------------------------------------------------------------------
@@ -415,13 +409,6 @@ def G_INTRINSIC_W_SIDE_EFFECTS : Instruction {
   let mayStore = 1;
 }
 
-// PHI node bearing an LLT.
-def G_PHI : Instruction {
-  let OutOperandList = (outs type0:$dst);
-  let InOperandList = (ins variable_ops);
-  let hasSideEffects = 0;
-}
-
 //------------------------------------------------------------------------------
 // Branches.
 //------------------------------------------------------------------------------

diff --git a/llvm/include/llvm/Target/TargetOpcodes.def b/llvm/include/llvm/Target/TargetOpcodes.def
index cc54d6c..c50a7aa 100644 (file)
--- a/llvm/include/llvm/Target/TargetOpcodes.def
+++ b/llvm/include/llvm/Target/TargetOpcodes.def
@@ -333,12 +333,6 @@ HANDLE_TARGET_OPCODE(G_SITOFP)
 /// Generic unsigned-int to float conversion
 HANDLE_TARGET_OPCODE(G_UITOFP)
 
-/// Generic type specifier for untyped registers.
-HANDLE_TARGET_OPCODE(G_TYPE)
-
-/// Generic PHI node (so that the type of the vreg can be set).
-HANDLE_TARGET_OPCODE(G_PHI)
-
 /// Generic BRANCH instruction. This is an unconditional branch.
 HANDLE_TARGET_OPCODE(G_BR)
 

diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 5a8f519..6650a1e 100644 (file)
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -385,7 +385,7 @@ bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
 
 bool IRTranslator::translatePHI(const User &U) {
   const PHINode &PI = cast<PHINode>(U);
-  auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI);
+  auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
   MIB.addDef(getOrCreateVReg(PI));
 
   PendingPHIs.emplace_back(&PI, MIB.getInstr());

diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
index 786decc..9844dbb 100644 (file)
--- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizer.cpp
@@ -33,11 +33,6 @@ MachineLegalizer::MachineLegalizer() : TablesInitialized(false) {
   DefaultActions[TargetOpcode::G_ANYEXT] = Legal;
   DefaultActions[TargetOpcode::G_TRUNC] = Legal;
 
-  // G_TYPE and G_PHI are essentially an annotated COPY/PHI instructions so
-  // they're always legal.
-  DefaultActions[TargetOpcode::G_TYPE] = Legal;
-  DefaultActions[TargetOpcode::G_PHI] = Legal;
-
   DefaultActions[TargetOpcode::G_INTRINSIC] = Legal;
   DefaultActions[TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS] = Legal;
 

diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 7198526..1f342ee 100644 (file)
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -224,8 +224,7 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
   bool CompleteMapping = true;
   // For copies we want to walk over the operands and try to find one
   // that has a register bank.
-  bool isCopyLike =
-      MI.isCopy() || MI.isPHI() || MI.getOpcode() == TargetOpcode::G_TYPE;
+  bool isCopyLike = MI.isCopy() || MI.isPHI();
   // Remember the register bank for reuse for copy-like instructions.
   const RegisterBank *RegBank = nullptr;
   // Remember the size of the register for reuse for copy-like instructions.

diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index f063942..808f81a 100644 (file)
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -908,8 +908,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   }
 
   // Generic opcodes must not have physical register operands.
-  if (isPreISelGenericOpcode(MCID.getOpcode()) &&
-      MCID.getOpcode() != TargetOpcode::G_TYPE) {
+  if (isPreISelGenericOpcode(MCID.getOpcode())) {
     for (auto &Op : MI->operands()) {
       if (Op.isReg() && TargetRegisterInfo::isPhysicalRegister(Op.getReg()))
         report("Generic instruction cannot have physical register", MI);

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 489f9ab..66c2ef3 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -230,16 +230,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
     return true;
   }
 
-  case TargetOpcode::G_TYPE: {
-    I.setDesc(TII.get(TargetOpcode::COPY));
-    return true;
-  }
-
-   case TargetOpcode::G_PHI: {
-     I.setDesc(TII.get(TargetOpcode::PHI));
-     return true;
-   }
-
   case TargetOpcode::G_FRAME_INDEX: {
     // allocas and G_FRAME_INDEX are only supported in addrspace(0).
     if (Ty != LLT::pointer(0)) {

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index 0a660e3..e462400 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -325,7 +325,7 @@ define void @intrinsics(i32 %cur, i32 %bits) {
 ; CHECK: [[FALSE]]:
 ; CHECK:     [[RES2:%[0-9]+]](s32) = G_LOAD
 
-; CHECK:     [[RES:%[0-9]+]](s32) = G_PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
+; CHECK:     [[RES:%[0-9]+]](s32) = PHI [[RES1]], %[[TRUE]], [[RES2]], %[[FALSE]]
 ; CHECK:     %w0 = COPY [[RES]]
 define i32 @test_phi(i32* %addr1, i32* %addr2, i1 %tst) {
   br i1 %tst, label %true, label %false

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
index 0dae823..0c4ce1a 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
@@ -24,8 +24,8 @@ body: |
     ; CHECK-LABEL: name: test_scalar_and_small
     ; CHECK: %4(s8) = G_AND %2, %3
 
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_AND %2, %3

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
index ba87b97..3037cd4 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
@@ -34,7 +34,7 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    %0(s64) = G_TYPE %x0
+    %0(s64) = COPY %x0
 
     ; CHECK: %1(s1) = G_TRUNC %0
     ; CHECK: %2(s8) = G_TRUNC %0

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
index 498d903..7218ff8 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
@@ -21,8 +21,8 @@ registers:
 body: |
   bb.0.entry:
     liveins: %x0, %x1, %x2, %x3
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x0
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x0
 
     %2(s32) = G_TRUNC %0
     %3(s32) = G_TRUNC %1

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
index 308f8cc..55a12e1 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ignore-non-generic.mir
@@ -15,10 +15,10 @@ body: |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: test_copy
-    ; CHECK: %0(s64) = G_TYPE %x0
+    ; CHECK: %0(s64) = COPY %x0
     ; CHECK-NEXT: %x0 = COPY %0
 
-    %0(s64) = G_TYPE %x0
+    %0(s64) = COPY %x0
     %x0 = COPY %0
 ...
 

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index 25a34eb..b4a0549 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -24,8 +24,8 @@ body: |
     ; CHECK-LABEL: name: test_scalar_mul_small
     ; CHECK: %4(s8) = G_MUL %2, %3
 
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_MUL %2, %3

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
index b85f195..a15ad4c 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
@@ -24,8 +24,8 @@ body: |
     ; CHECK-LABEL: name: test_scalar_or_small
     ; CHECK: %4(s8) = G_OR %2, %3
 
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_OR %2, %3

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
index 168c618..f626033 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
@@ -24,8 +24,8 @@ body: |
     ; CHECK-LABEL: name: test_scalar_xor_small
     ; CHECK: %4(s8) = G_XOR %2, %3
 
-    %0(s64) = G_TYPE %x0
-    %1(s64) = G_TYPE %x1
+    %0(s64) = COPY %x0
+    %1(s64) = COPY %x1
     %2(s8) = G_TRUNC %0
     %3(s8) = G_TRUNC %1
     %4(s8) = G_XOR %2, %3

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir b/llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
index 69b8347..9a2f7f7 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/verify-regbankselected.mir
@@ -9,7 +9,7 @@
 ...
 ---
 # CHECK: *** Bad machine code: Generic virtual register must have a bank in a RegBankSelected function ***
-# CHECK: instruction: %vreg0<def>(s64) = G_TYPE
+# CHECK: instruction: %vreg0<def>(s64) = COPY
 # CHECK: operand 0: %vreg0<def>
 name:            test
 regBankSelected: true
@@ -18,5 +18,5 @@ registers:
 body: |
   bb.0:
    liveins: %x0
-   %0(s64) = G_TYPE %x0
+   %0(s64) = COPY %x0
 ...

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir b/llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
index 54fd078..2149903 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/verify-selected.mir
@@ -19,7 +19,7 @@ registers:
 body: |
   bb.0:
    liveins: %x0
-   %0 = G_TYPE %x0
+   %0 = COPY %x0
 
    ; CHECK: *** Bad machine code: Unexpected generic instruction in a Selected function ***
    ; CHECK: instruction: %vreg1<def> = G_ADD