drm/msm/dsi: Add a PHY op that initializes version specific stuff

Create an init() op for dsi_phy which sets up things specific to
a given DSI PHY.

The dsi_phy driver probe expects every DSI version to get a
"dsi_phy_regulator" mmio base. This isn't the case for 8x96.
Creating an init() op will allow us to accommodate such
differences.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index f39386e..03a3549 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -295,6 +295,24 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy)
        return -EINVAL;
 }
 
+int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
+{
+       struct platform_device *pdev = phy->pdev;
+       int ret = 0;
+
+       phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
+                               "DSI_PHY_REG");
+       if (IS_ERR(phy->reg_base)) {
+               dev_err(&pdev->dev, "%s: failed to map phy regulator base\n",
+                       __func__);
+               ret = -ENOMEM;
+               goto fail;
+       }
+
+fail:
+       return ret;
+}
+
 static int dsi_phy_driver_probe(struct platform_device *pdev)
 {
        struct msm_dsi_phy *phy;
@@ -331,15 +349,6 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
                goto fail;
        }
 
-       phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
-                               "DSI_PHY_REG");
-       if (IS_ERR(phy->reg_base)) {
-               dev_err(dev, "%s: failed to map phy regulator base\n",
-                       __func__);
-               ret = -ENOMEM;
-               goto fail;
-       }
-
        ret = dsi_phy_regulator_init(phy);
        if (ret) {
                dev_err(dev, "%s: failed to init regulator\n", __func__);
@@ -353,6 +362,12 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
                goto fail;
        }
 
+       if (phy->cfg->ops.init) {
+               ret = phy->cfg->ops.init(phy);
+               if (ret)
+                       goto fail;
+       }
+
        /* PLL init will call into clk_register which requires
         * register access, so we need to enable power and ahb clock.
         */

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f24a854..b9d7d02 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -22,6 +22,7 @@
 #define dsi_phy_write(offset, data) msm_writel((data), (offset))
 
 struct msm_dsi_phy_ops {
+       int (*init) (struct msm_dsi_phy *phy);
        int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
                const unsigned long bit_rate, const unsigned long esc_rate);
        void (*disable)(struct msm_dsi_phy *phy);
@@ -87,6 +88,7 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
        const unsigned long bit_rate, const unsigned long esc_rate);
 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
                                u32 bit_mask);
+int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
 
 #endif /* __DSI_PHY_H__ */
 

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index c757e20..c4a7be5 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -145,6 +145,7 @@ const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs = {
        .ops = {
                .enable = dsi_20nm_phy_enable,
                .disable = dsi_20nm_phy_disable,
+               .init = msm_dsi_phy_init_common,
        },
        .io_start = { 0xfd998300, 0xfd9a0300 },
        .num_dsi_phy = 2,

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 63d7fba..ea740c5 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -144,6 +144,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs = {
        .ops = {
                .enable = dsi_28nm_phy_enable,
                .disable = dsi_28nm_phy_disable,
+               .init = msm_dsi_phy_init_common,
        },
        .io_start = { 0xfd922b00, 0xfd923100 },
        .num_dsi_phy = 2,
@@ -161,6 +162,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = {
        .ops = {
                .enable = dsi_28nm_phy_enable,
                .disable = dsi_28nm_phy_disable,
+               .init = msm_dsi_phy_init_common,
        },
        .io_start = { 0x1a98500 },
        .num_dsi_phy = 1,

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 7bdb9de..9aff0ba 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -191,6 +191,7 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs = {
        .ops = {
                .enable = dsi_28nm_phy_enable,
                .disable = dsi_28nm_phy_disable,
+               .init = msm_dsi_phy_init_common,
        },
        .io_start = { 0x4700300, 0x5800300 },
        .num_dsi_phy = 2,