s5pc110: timers: s5pc110 timer support

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

diff --git a/cpu/arm_cortexa8/s5pc1xx/timer.c b/cpu/arm_cortexa8/s5pc1xx/timer.c
index cda6680..9dfbef9 100644 (file)
--- a/cpu/arm_cortexa8/s5pc1xx/timer.c
+++ b/cpu/arm_cortexa8/s5pc1xx/timer.c
@@ -45,14 +45,24 @@ static unsigned long lastdec;               /* Last decremneter snapshot */
 /* macro to read the 16 bit timer */
 static inline unsigned long READ_TIMER(void)
 {
-       const s5pc1xx_timers_t *timers = (s5pc1xx_timers_t *)S5P_TIMER_BASE;
+       s5pc1xx_timers_t *timers;
+
+       if (cpu_is_s5pc110())
+               timers = (s5pc1xx_timers_t *) S5PC110_TIMER_BASE;
+       else
+               timers = (s5pc1xx_timers_t *) S5PC100_TIMER_BASE;
 
        return timers->TCNTO4;
 }
 
 int timer_init(void)
 {
-       s5pc1xx_timers_t *timers = (s5pc1xx_timers_t *)S5P_TIMER_BASE;
+       s5pc1xx_timers_t *timers;
+
+       if (cpu_is_s5pc110())
+               timers = (s5pc1xx_timers_t *) S5PC110_TIMER_BASE;
+       else
+               timers = (s5pc1xx_timers_t *) S5PC100_TIMER_BASE;
 
        /*
         * @ PWM Timer 4
@@ -81,11 +91,11 @@ int timer_init(void)
 
        /* auto reload & manual update */
        timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) |
-               S5P_TCON4_AUTO_RELOAD | S5P_TCON4_UPDATE;
+               S5PC1XX_TCON4_AUTO_RELOAD | S5PC1XX_TCON4_UPDATE;
 
        /* start PWM timer 4 */
        timers->TCON = (timers->TCON & ~(0x07 << TCON_TIMER4_SHIFT)) |
-               S5P_TCON4_AUTO_RELOAD | S5P_TCON4_ON;
+               S5PC1XX_TCON4_AUTO_RELOAD | S5PC1XX_TCON4_START;
 
        timestamp = 0;
 

diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h
index b3a42ed..f49d024 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/cpu.h
+++ b/include/asm-arm/arch-s5pc1xx/cpu.h
@@ -38,7 +38,6 @@
 #define S5P_PA_VIC2            S5P_ADDR(0x04200000)    /* Vector Interrupt Controller 2 */
 #define S5P_PA_DMC             S5P_ADDR(0x06000000)    /* Dram Memory Controller */
 #define S5P_PA_SROMC           S5P_ADDR(0x07000000)    /* SROM Controller */
-#define S5P_PA_PWMTIMER                S5P_ADDR(0x0a000000)    /* PWM Timer */
 
 /* Note that write the macro by address order */
 #define S5PC100_VIC0_BASE      0xE4000000

diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h
index ab7163b..8520efc 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/pwm.h
+++ b/include/asm-arm/arch-s5pc1xx/pwm.h
@@ -1,7 +1,6 @@
 /*
- * (C) Copyright 2009
- * Samsung Electronics, <www.samsung.com/sec>
- * Heungjun Kim <riverful.kim@samsung.com>
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
  * Minkyu Kang <mk7.kang@samsung.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -18,7 +17,6 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *
  */
 
 #ifndef __ASM_ARM_ARCH_PWM_H_
@@ -27,10 +25,15 @@
 /*
  * PWM Timer
  */
-#define S5P_PWMTIMER_BASE(x)   (S5P_PA_PWMTIMER + (x))
+#define S5PC100_PWMTIMER_BASE  0xEA000000
+#define S5PC110_PWMTIMER_BASE  0xE2500000
+
+/* PWM timer addressing */
+#define S5PC100_TIMER_BASE     S5PC100_PWMTIMER_BASE
+#define S5PC110_TIMER_BASE     S5PC110_PWMTIMER_BASE
 
 /* PWM timer offset */
-#define PWM_TCFG0_OFFSET       0x0
+#define PWM_TCFG0_OFFSET       0x00
 #define PWM_TCFG1_OFFSET       0x04
 #define PWM_TCON_OFFSET                0x08
 #define PWM_TCNTB0_OFFSET      0x0c
@@ -48,33 +51,12 @@
 #define PWM_TCNTO4_OFFSET      0x40
 #define PWM_TINT_CSTAT_OFFSET  0x44
 
-/* PWM timer register */
-#define S5P_PWM_TCFG0          S5P_PWMTIMER_BASE(PWM_TCFG0_OFFSET)
-#define S5P_PWM_TCFG1          S5P_PWMTIMER_BASE(PWM_TCFG1_OFFSET)
-#define S5P_PWM_TCON           S5P_PWMTIMER_BASE(PWM_TCON_OFFSET)
-#define S5P_PWM_TCNTB0         S5P_PWMTIMER_BASE(PWM_TCNTB0_OFFSET)
-#define S5P_PWM_TCMPB0         S5P_PWMTIMER_BASE(PWM_TCMPB0_OFFSET)
-#define S5P_PWM_TCNTO0         S5P_PWMTIMER_BASE(PWM_TCNTO0_OFFSET)
-#define S5P_PWM_TCNTB1         S5P_PWMTIMER_BASE(PWM_TCNTB1_OFFSET)
-#define S5P_PWM_TCMPB1         S5P_PWMTIMER_BASE(PWM_TCMPB1_OFFSET)
-#define S5P_PWM_TCNTO1         S5P_PWMTIMER_BASE(PWM_TCNTO1_OFFSET)
-#define S5P_PWM_TCNTB2         S5P_PWMTIMER_BASE(PWM_TCNTB2_OFFSET)
-#define S5P_PWM_TCMPB2         S5P_PWMTIMER_BASE(PWM_TCMPB2_OFFSET)
-#define S5P_PWM_TCNTO2         S5P_PWMTIMER_BASE(PWM_TCNTO2_OFFSET)
-#define S5P_PWM_TCNTB3         S5P_PWMTIMER_BASE(PWM_TCNTB3_OFFSET)
-#define S5P_PWM_TCNTO3         S5P_PWMTIMER_BASE(PWM_TCNTO3_OFFSET)
-#define S5P_PWM_TCNTB4         S5P_PWMTIMER_BASE(PWM_TCNTB4_OFFSET)
-#define S5P_PWM_TCNTO4         S5P_PWMTIMER_BASE(PWM_TCNTO4_OFFSET)
-#define S5P_PWM_TINT_CSTAT     S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET)
-
-/* PWM timer addressing */
-#define S5P_TIMER_BASE         S5P_PWMTIMER_BASE(0x0)
-
-/* PWM timer value */
-#define S5P_TCON4_AUTO_RELOAD  (1 << 22)
-                               /* Interval mode(Auto Reload) of PWM Timer 4 */
-#define S5P_TCON4_UPDATE       (1 << 21)  /* Update TCNTB4 */
-#define S5P_TCON4_ON           (1 << 20)  /* start bit of PWM Timer 4 */
+/* Interval mode(Auto Reload) of PWM Timer 4 */
+#define S5PC1XX_TCON4_AUTO_RELOAD      (1 << 22)
+/* Update TCNTB4 */
+#define S5PC1XX_TCON4_UPDATE           (1 << 21)
+/* start bit of PWM Timer 4 */
+#define S5PC1XX_TCON4_START            (1 << 20)
 
 #ifndef __ASSEMBLY__
 typedef struct s5pc1xx_timer {