phy: uniphier-pcie: Set VCOPLL clamp mode in PHY register
authorKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Fri, 29 Oct 2021 10:39:04 +0000 (19:39 +0900)
committerVinod Koul <vkoul@kernel.org>
Tue, 23 Nov 2021 05:51:53 +0000 (11:21 +0530)
Set VCOPLL clamp mode to mode 0 to avoid hardware unstable issue.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1635503947-18250-6-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/socionext/phy-uniphier-pcie.c

index fde8aac..2bd8df6 100644 (file)
@@ -51,6 +51,9 @@
 #define PCL_PHY_R26            26
 #define   VCO_CTRL             GENMASK(7, 4)   /* Tx VCO adjustment value */
 #define   VCO_CTRL_INIT_VAL    5
+#define PCL_PHY_R28            28
+#define   VCOPLL_CLMP          GENMASK(3, 2)   /* Tx VCOPLL clamp mode */
+#define   VCOPLL_CLMP_VAL      0
 
 struct uniphier_pciephy_priv {
        void __iomem *base;
@@ -158,6 +161,8 @@ static int uniphier_pciephy_init(struct phy *phy)
                                   FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));
        uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL,
                                   FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));
+       uniphier_pciephy_set_param(priv, PCL_PHY_R28, VCOPLL_CLMP,
+                                  FIELD_PREP(VCOPLL_CLMP, VCOPLL_CLMP_VAL));
        usleep_range(1, 10);
 
        uniphier_pciephy_deassert(priv);