phy: qcom-qmp: split allegedly 4.20 and 5.20 PCS registers

Split registers definitions belonging allegedly to 4.20 and 5.20 QMP
PHYs. They are used for the PCIe QMP PHYs, which have no good open
source reference.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-20-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
new file mode 100644 (file)
index 0000000..af27360
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v4_20.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
+
+#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1                 0x0a0
+#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME           0x0f0
+#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME           0x0f4
+#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2              0x0fc
+#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5              0x108
+#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2            0x824
+#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2            0x828
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
new file mode 100644 (file)
index 0000000..1eedf50
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
+#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
+
+/* Only for QMP V5_20 PHY - PCIe PCS registers */
+#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE      0x01c
+#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS           0x090
+#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1                 0x0a0
+#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5              0x108
+#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN                        0x15c
+#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3       0x184
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
new file mode 100644 (file)
index 0000000..08c3dd1
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v4_20.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V4_20_H_
+#define QCOM_PHY_QMP_PCS_V4_20_H_
+
+/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
+#define QPHY_V4_20_PCS_RX_SIGDET_LVL                   0x188
+#define QPHY_V4_20_PCS_EQ_CONFIG2                      0x1d8
+#define QPHY_V4_20_PCS_EQ_CONFIG4                      0x1e0
+#define QPHY_V4_20_PCS_EQ_CONFIG5                      0x1e4
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 1f8684c..cdbbcf6 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -32,11 +32,16 @@
 #include "phy-qcom-qmp-pcs-usb-v4.h"
 #include "phy-qcom-qmp-pcs-ufs-v4.h"
 
+#include "phy-qcom-qmp-pcs-v4_20.h"
+#include "phy-qcom-qmp-pcs-pcie-v4_20.h"
+
 #include "phy-qcom-qmp-pcs-v5.h"
 #include "phy-qcom-qmp-pcs-pcie-v5.h"
 #include "phy-qcom-qmp-pcs-usb-v5.h"
 #include "phy-qcom-qmp-pcs-ufs-v5.h"
 
+#include "phy-qcom-qmp-pcs-pcie-v5_20.h"
+
 #include "phy-qcom-qmp-pcie-qhp.h"
 
 /* Only for QMP V3 & V4 PHY - DP COM registers */
@@ -121,12 +126,6 @@
 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS         0x0d8
 #define QSERDES_V4_DP_PHY_STATUS                       0x0dc
 
-/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
-#define QPHY_V4_20_PCS_RX_SIGDET_LVL                   0x188
-#define QPHY_V4_20_PCS_EQ_CONFIG2                      0x1d8
-#define QPHY_V4_20_PCS_EQ_CONFIG4                      0x1e0
-#define QPHY_V4_20_PCS_EQ_CONFIG5                      0x1e4
-
 /* Only for QMP V4 PHY - PCS_MISC registers */
 #define QPHY_V4_PCS_MISC_TYPEC_CTRL                    0x00
 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL              0x04
@@ -135,20 +134,4 @@
 #define QPHY_V4_PCS_MISC_TYPEC_STATUS                  0x10
 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS            0x14
 
-#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1                 0x0a0
-#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME           0x0f0
-#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME           0x0f4
-#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2              0x0fc
-#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5              0x108
-#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2            0x824
-#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2            0x828
-
-/* Only for QMP V5_20 PHY - PCIe PCS registers */
-#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE      0x01c
-#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS           0x090
-#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1                 0x0a0
-#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5              0x108
-#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN                        0x15c
-#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3       0x184
-
 #endif