emmc: run hs400 200M on sm1 [1/1]
authorRuixuan Li <ruixuan.li@amlogic.com>
Thu, 8 Aug 2019 02:08:32 +0000 (10:08 +0800)
committerTao Zeng <tao.zeng@amlogic.com>
Fri, 23 Aug 2019 05:54:12 +0000 (22:54 -0700)
PD#SWPL-12424

Problem:
run hs400 166M on sm1 now

Solution:
modify dts

Verify:
passed on sm1_ac200

Change-Id: I28f5f8da3481c9f2a19e27bc8e430a3379ec6b2a
Signed-off-by: Ruixuan Li <ruixuan.li@amlogic.com>
15 files changed:
arch/arm/boot/dts/amlogic/sm1_s905d3_ac200.dts
arch/arm/boot/dts/amlogic/sm1_s905d3_ac200_buildroot.dts
arch/arm/boot/dts/amlogic/sm1_s905d3_ac200_drm_buildroot.dts
arch/arm/boot/dts/amlogic/sm1_s905d3_ac202.dts
arch/arm/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
arch/arm/boot/dts/amlogic/sm1_s905x3_ac213.dts
arch/arm/boot/dts/amlogic/sm1_s905x3_ac213_buildroot.dts
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200_buildroot.dts
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200_drm_buildroot.dts
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202.dts
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac202_1g.dts
arch/arm64/boot/dts/amlogic/sm1_s905x3_ac213.dts
arch/arm64/boot/dts/amlogic/sm1_s905x3_ac213_buildroot.dts
drivers/amlogic/mmc/aml_sd_emmc_v3.c

index 5c4e664..4a82f62 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index 2ec713e..45559f2 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index c89d87e..926640e 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index f9dd311..08c47b7 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index ebd2879..51824c0 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index e251947..8c072c9 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index e9e056d..aecc964 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index b9b3460..eac0870 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index 1890095..cdff1ae 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index c90fee1..ab6b50b 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index b5e8557..23386a6 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index 6c8aa3e..03ab4d2 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index e7eb21b..ea7010f 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index f3d4c84..473d95e 100644 (file)
                         "MMC_CAP_DRIVER_TYPE_D";
                caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
-               f_max = <166666666>;
+               f_max = <200000000>;
        };
 };
 
index e7dd78e..67be738 100644 (file)
@@ -156,6 +156,21 @@ int meson_mmc_clk_init_v3(struct amlsd_host *host)
 
        return ret;
 }
+/**************************
+ *   select clock source
+ * ************************
+ * HS200 200M -> HS400 200M
+ *
+ * G12B: 800M -> 800M
+ *
+ * TL1 : 792M -> 792M
+ *
+ * SM1 :  1G  -> 800M
+ *
+ * TM2 :  1G  -> 800M
+ *
+ * TXLX:  1G  -> 400M
+ **************************/
 
 static int meson_mmc_clk_set_rate_v3(struct mmc_host *mmc,
                unsigned long clk_ios)
@@ -2276,8 +2291,7 @@ int aml_mmc_execute_tuning_v3(struct mmc_host *mmc, u32 opcode)
                intf3 |= (1<<22);
                writel(intf3, (host->base + SD_EMMC_INTF3));
                pdata->intf3 = intf3;
-               if ((host->data->chip_type >= MMC_CHIP_TL1)
-                       || (host->data->chip_type == MMC_CHIP_G12B))
+               if (host->data->chip_type == MMC_CHIP_G12B)
                        aml_emmc_hs200_tl1(mmc);
                err = 0;
        }