arm: dts: add pwm support for MediaTek SoCs
authorSam Shih <sam.shih@mediatek.com>
Fri, 21 Feb 2020 13:01:47 +0000 (21:01 +0800)
committerTom Rini <trini@konsulko.com>
Fri, 17 Apr 2020 16:32:36 +0000 (12:32 -0400)
This patch add pwm support for mt7622, mt7623 and mt7629 SoCs

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
arch/arm/dts/mt7622.dtsi
arch/arm/dts/mt7623.dtsi
arch/arm/dts/mt7629.dtsi

index 1e8ec9b..f9ce0c6 100644 (file)
                #clock-cells = <1>;
        };
 
+       pwm: pwm@11006000 {
+               compatible = "mediatek,mt7622-pwm";
+               reg = <0x11006000 0x1000>;
+               #clock-cells = <1>;
+               #pwm-cells = <2>;
+               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                        <&pericfg CLK_PERI_PWM_PD>,
+                        <&pericfg CLK_PERI_PWM1_PD>,
+                        <&pericfg CLK_PERI_PWM2_PD>,
+                        <&pericfg CLK_PERI_PWM3_PD>,
+                        <&pericfg CLK_PERI_PWM4_PD>,
+                        <&pericfg CLK_PERI_PWM5_PD>,
+                        <&pericfg CLK_PERI_PWM6_PD>;
+               clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
+                             "pwm5", "pwm6";
+               status = "disabled";
+       };
+
 };
index 1f45dea..0452889 100644 (file)
                mediatek,ethsys = <&ethsys>;
                status = "disabled";
        };
+
+       pwm: pwm@11006000 {
+               compatible = "mediatek,mt7623-pwm";
+               reg = <0x11006000 0x1000>;
+               #clock-cells = <1>;
+               #pwm-cells = <2>;
+               clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                        <&pericfg CLK_PERI_PWM>,
+                        <&pericfg CLK_PERI_PWM1>,
+                        <&pericfg CLK_PERI_PWM2>,
+                        <&pericfg CLK_PERI_PWM3>,
+                        <&pericfg CLK_PERI_PWM4>,
+                        <&pericfg CLK_PERI_PWM5>;
+               clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
+                             "pwm5";
+               status = "disabled";
+       };
 };
index a33a74a..644d2da 100644 (file)
                reg = <0x1b130000 0x1000>;
                #clock-cells = <1>;
        };
+
+       pwm: pwm@11006000 {
+               compatible = "mediatek,mt7629-pwm";
+               reg = <0x11006000 0x1000>;
+               #clock-cells = <1>;
+               #pwm-cells = <2>;
+               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                        <&pericfg CLK_PERI_PWM_PD>,
+                        <&pericfg CLK_PERI_PWM1_PD>;
+               clock-names = "top", "main", "pwm1";
+               assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
+               assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL2_D4>;
+               status = "disabled";
+       };
+
 };