#include <linux/io.h>
/* This is all the chips recognized by this library */
-typedef enum _logical_chip_type_t
-{
+typedef enum _logical_chip_type_t {
SM_UNKNOWN,
SM718,
SM750,
logical_chip_type_t;
-typedef enum _clock_type_t
-{
+typedef enum _clock_type_t {
MXCLK_PLL,
PRIMARY_PLL,
SECONDARY_PLL,
}
clock_type_t;
-typedef struct _pll_value_t
-{
+typedef struct _pll_value_t {
clock_type_t clockType;
unsigned long inputFreq; /* Input clock frequency to the PLL */
pll_value_t;
/* input struct to initChipParam() function */
-typedef struct _initchip_param_t
-{
+typedef struct _initchip_param_t {
unsigned short powerMode; /* Use power mode 0 or 1 */
unsigned short chipClock; /**
* Speed of main chip clock in MHz unit
cnt = 0;
/* Set the primary display control */
- if (!ctrl)
- {
+ if (!ctrl) {
ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL);
/* Turn on/off the Panel display control */
- if (dispState)
- {
+ if (dispState) {
/* Timing should be enabled first before enabling the plane
* because changing at the same time does not guarantee that
* the plane will also enabled or disabled.
* until a few delay. Need to write
* and read it a couple times
*/
- do
- {
+ do {
cnt++;
POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
} while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) !=
(ulDisplayCtrlReg & ~ulReservedBits));
printk("Set Panel Plane enbit:after tried %d times\n", cnt);
- }
- else
- {
+ } else {
/* When turning off, there is no rule on the programming
* sequence since whenever the clock is off, then it does not
* matter whether the plane is enabled or disabled.
POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
}
- }
- /* Set the secondary display control */
- else
- {
+ } else {
+ /* Set the secondary display control */
ulDisplayCtrlReg = PEEK32(CRT_DISPLAY_CTRL);
- if (dispState)
- {
+ if (dispState) {
/* Timing should be enabled first before enabling the plane because changing at the
same time does not guarantee that the plane will also enabled or disabled.
*/
FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) |
FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE);
- do
- {
+ do {
cnt++;
POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
} while ((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) !=
(ulDisplayCtrlReg & ~ulReservedBits));
printk("Set Crt Plane enbit:after tried %d times\n", cnt);
- }
- else
- {
+ } else {
/* When turning off, there is no rule on the programming
* sequence since whenever the clock is off, then it does not
* matter whether the plane is enabled or disabled.
if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
PANEL_PLL_CTRL_POWER_OFF) ||
(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
- PANEL_DISPLAY_CTRL_TIMING_DISABLE))
- {
+ PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
return;
}
- while (delay-- > 0)
- {
+ while (delay-- > 0) {
/* Wait for end of vsync. */
- do
- {
+ do {
status = FIELD_GET(PEEK32(SYSTEM_CTRL),
SYSTEM_CTRL,
PANEL_VSYNC);
while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
/* Wait for start of vsync. */
- do
- {
+ do {
status = FIELD_GET(PEEK32(SYSTEM_CTRL),
SYSTEM_CTRL,
PANEL_VSYNC);
if ((FIELD_GET(PEEK32(CRT_PLL_CTRL), CRT_PLL_CTRL, POWER) ==
CRT_PLL_CTRL_POWER_OFF) ||
(FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) ==
- CRT_DISPLAY_CTRL_TIMING_DISABLE))
- {
+ CRT_DISPLAY_CTRL_TIMING_DISABLE)) {
return;
}
- while (delay-- > 0)
- {
+ while (delay-- > 0) {
/* Wait for end of vsync. */
- do
- {
+ do {
status = FIELD_GET(PEEK32(SYSTEM_CTRL),
SYSTEM_CTRL,
CRT_VSYNC);
while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE);
/* Wait for start of vsync. */
- do
- {
+ do {
status = FIELD_GET(PEEK32(SYSTEM_CTRL),
SYSTEM_CTRL,
CRT_VSYNC);
1, /* Enable continuous Sync */
1, /* Enable PLL Filter */
4 /* Use the recommended value for PLL Filter value */
- ) != 0) && (dviGetVendorID() != 0x0000) && (dviGetDeviceID() != 0x0000))
- {
+ ) != 0) && (dviGetVendorID() != 0x0000) && (dviGetDeviceID() != 0x0000)) {
return (-1);
}
CRT means crt path DSUB
*/
#if 0
-typedef enum _disp_output_t
-{
+typedef enum _disp_output_t {
NO_DISPLAY = DPMS_OFF,
LCD1_PRI = PNL_2_PRI|PRI_TP_ON|PNL_SEQ_ON|DPMS_OFF|DAC_ON,
/* This global variable contains all the supported driver and its corresponding
function API. Please set the function pointer to NULL whenever the function
is not supported. */
-static dvi_ctrl_device_t g_dcftSupportedDviController[] =
-{
+static dvi_ctrl_device_t g_dcftSupportedDviController[] = {
#ifdef DVI_CTRL_SII164
{
.pfnInit = sii164InitChip,
{
dvi_ctrl_device_t *pCurrentDviCtrl;
pCurrentDviCtrl = g_dcftSupportedDviController;
- if (pCurrentDviCtrl->pfnInit != NULL)
- {
+ if (pCurrentDviCtrl->pfnInit != NULL) {
return pCurrentDviCtrl->pfnInit(edgeSelect, busSelect, dualEdgeClkSelect, hsyncEnable,
vsyncEnable, deskewEnable, deskewSetting, continuousSyncEnable,
pllFilterEnable, pllFilterValue);
* Note:
* Only 16 byte can be accessed per i2c start instruction.
*/
- do
- {
+ do {
/* Reset I2C by writing 0 to I2C_RESET register to clear the previous status. */
POKE32(I2C_RESET, 0);
* Note:
* Only 16 byte can be accessed per i2c start instruction.
*/
- do
- {
+ do {
/* Reset I2C by writing 0 to I2C_RESET register to clear all the status. */
POKE32(I2C_RESET, 0);
int ret = 0;
int cnt = 0;
unsigned int ulTmpValue, ulReg;
- if (pll->clockType == SECONDARY_PLL)
- {
+ if (pll->clockType == SECONDARY_PLL) {
/* programe secondary pixel clock */
POKE32(CRT_PLL_CTRL, formatPllReg(pll));
POKE32(CRT_HORIZONTAL_TOTAL,
POKE32(CRT_DISPLAY_CTRL, ulTmpValue|ulReg);
}
- }
- else if (pll->clockType == PRIMARY_PLL)
- {
+ } else if (pll->clockType == PRIMARY_PLL) {
unsigned int ulReservedBits;
POKE32(PANEL_PLL_CTRL, formatPllReg(pll));
POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg);
#if 1
- while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg))
- {
+ while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) != (ulTmpValue|ulReg)) {
cnt++;
if (cnt > 1000)
break;
POKE32(PANEL_DISPLAY_CTRL, ulTmpValue|ulReg);
}
#endif
- }
- else {
+ } else {
ret = -1;
}
return ret;
#include "ddk750_chip.h"
-typedef enum _spolarity_t
-{
+typedef enum _spolarity_t {
POS = 0, /* positive */
NEG, /* negative */
}
spolarity_t;
-typedef struct _mode_parameter_t
-{
+typedef struct _mode_parameter_t {
/* Horizontal timing. */
unsigned long horizontal_total;
unsigned long horizontal_display_end;
if (getChipType() == SM750LE)
return;
- switch (powerMode)
- {
+ switch (powerMode) {
case POWER_MODE_CTRL_MODE_MODE0:
control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, MODE0);
break;
}
/* Set up other fields in Power Control Register */
- if (powerMode == POWER_MODE_CTRL_MODE_SLEEP)
- {
+ if (powerMode == POWER_MODE_CTRL_MODE_SLEEP) {
control_value =
#ifdef VALIDATION_CHIP
FIELD_SET(control_value, POWER_MODE_CTRL, 336CLK, OFF) |
#endif
FIELD_SET(control_value, POWER_MODE_CTRL, OSC_INPUT, OFF);
- }
- else
- {
+ } else {
control_value =
#ifdef VALIDATION_CHIP
FIELD_SET(control_value, POWER_MODE_CTRL, 336CLK, ON) |
/* Get current power mode. */
mode = getPowerMode();
- switch (mode)
- {
+ switch (mode) {
case POWER_MODE_CTRL_MODE_MODE0:
gate_reg = MODE0_GATE;
break;
uint32_t gate;
gate = PEEK32(CURRENT_GATE);
- if (enable)
- {
+ if (enable) {
gate = FIELD_SET(gate, CURRENT_GATE, DE, ON);
gate = FIELD_SET(gate, CURRENT_GATE, CSC, ON);
- }
- else
- {
+ } else {
gate = FIELD_SET(gate, CURRENT_GATE, DE, OFF);
gate = FIELD_SET(gate, CURRENT_GATE, CSC, OFF);
}
/* Enable ZV Port Gate */
gate = PEEK32(CURRENT_GATE);
- if (enable)
- {
+ if (enable) {
gate = FIELD_SET(gate, CURRENT_GATE, ZVPORT, ON);
#if 1
/* Using Software I2C */
/* Using Hardware I2C */
gate = FIELD_SET(gate, CURRENT_GATE, I2C, ON);
#endif
- }
- else
- {
+ } else {
/* Disable ZV Port Gate. There is no way to know whether the GPIO pins are being used
or not. Therefore, do not disable the GPIO gate. */
gate = FIELD_SET(gate, CURRENT_GATE, ZVPORT, OFF);
#ifndef DDK750_POWER_H__
#define DDK750_POWER_H__
-typedef enum _DPMS_t
-{
+typedef enum _DPMS_t {
crtDPMS_ON = 0x0,
crtDPMS_STANDBY = 0x1,
crtDPMS_SUSPEND = 0x2,
#endif
/* Check if SII164 Chip exists */
- if ((sii164GetVendorID() == SII164_VENDOR_ID) && (sii164GetDeviceID() == SII164_DEVICE_ID))
- {
+ if ((sii164GetVendorID() == SII164_VENDOR_ID) && (sii164GetDeviceID() == SII164_DEVICE_ID)) {
/*
* Initialize SII164 controller chip.
*/
else
config = SII164_DESKEW_ENABLE;
- switch (deskewSetting)
- {
+ switch (deskewSetting) {
case 0:
config |= SII164_DESKEW_1_STEP;
break;
unsigned char config;
config = i2cReadReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION);
- if (powerUp == 1)
- {
+ if (powerUp == 1) {
/* Power up the chip */
config &= ~SII164_CONFIGURATION_POWER_MASK;
config |= SII164_CONFIGURATION_POWER_NORMAL;
i2cWriteReg(SII164_I2C_ADDRESS, SII164_CONFIGURATION, config);
- }
- else
- {
+ } else {
/* Power down the chip */
config &= ~SII164_CONFIGURATION_POWER_MASK;
config |= SII164_CONFIGURATION_POWER_DOWN;
unsigned char detectReg;
detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) & ~SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG;
- switch (hotPlugMode)
- {
+ switch (hotPlugMode) {
case SII164_HOTPLUG_DISABLE:
detectReg |= SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH;
break;
#define USE_DVICHIP
/* Hot Plug detection mode structure */
-typedef enum _sii164_hot_plug_mode_t
-{
+typedef enum _sii164_hot_plug_mode_t {
SII164_HOTPLUG_DISABLE = 0, /* Disable Hot Plug output bit (always high). */
SII164_HOTPLUG_USE_MDI, /* Use Monitor Detect Interrupt bit. */
SII164_HOTPLUG_USE_RSEN, /* Use Receiver Sense detect bit. */
{
u32 deCtrl;
- if (accel->de_wait() != 0)
- {
+ if (accel->de_wait() != 0) {
/* int time wait and always busy,seems hardware
* got something error */
pr_debug("De engine always busy\n");
de_ctrl = 0;
/* If source and destination are the same surface, need to check for overlay cases */
- if (sBase == dBase && sPitch == dPitch)
- {
+ if (sBase == dBase && sPitch == dPitch) {
/* Determine direction of operation */
- if (sy < dy)
- {
+ if (sy < dy) {
/* +----------+
|S |
| +----------+
+----------+ */
nDirection = BOTTOM_TO_TOP;
- }
- else if (sy > dy)
- {
+ } else if (sy > dy) {
/* +----------+
|D |
| +----------+
+----------+ */
nDirection = TOP_TO_BOTTOM;
- }
- else
- {
+ } else {
/* sy == dy */
- if (sx <= dx)
- {
+ if (sx <= dx) {
/* +------+---+------+
|S | | D|
| | | |
+------+---+------+ */
nDirection = RIGHT_TO_LEFT;
- }
- else
- {
+ } else {
/* sx > dx */
/* +------+---+------+
}
}
- if ((nDirection == BOTTOM_TO_TOP) || (nDirection == RIGHT_TO_LEFT))
- {
+ if ((nDirection == BOTTOM_TO_TOP) || (nDirection == RIGHT_TO_LEFT)) {
sx += width - 1;
sy += height - 1;
dx += width - 1;
write_dpr(accel, DE_PITCH,
FIELD_VALUE(0, DE_PITCH, DESTINATION, dPitch) |
FIELD_VALUE(0, DE_PITCH, SOURCE, sPitch)); /* dpr10 */
- }
- else
+ } else
#endif
{
write_dpr(accel, DE_PITCH,
ul4BytesPerScan = ulBytesPerScan & ~3;
ulBytesRemain = ulBytesPerScan & 3;
- if (accel->de_wait() != 0)
- {
+ if (accel->de_wait() != 0) {
return -1;
}
FIELD_VALUE(0, DE_PITCH, DESTINATION, dPitch) |
FIELD_VALUE(0, DE_PITCH, SOURCE, dPitch)); /* dpr10 */
- }
- else
+ } else
#endif
{
write_dpr(accel, DE_PITCH,
write_dpr(accel, DE_CONTROL, de_ctrl | deGetTransparency(accel));
/* Write MONO data (line by line) to 2D Engine data port */
- for (i = 0; i < height; i++)
- {
+ for (i = 0; i < height; i++) {
/* For each line, send the data in chunks of 4 bytes */
- for (j = 0; j < (ul4BytesPerScan/4); j++)
- {
+ for (j = 0; j < (ul4BytesPerScan/4); j++) {
write_dpPort(accel, *(unsigned int *)(pSrcbuf + (j * 4)));
}
- if (ulBytesRemain)
- {
+ if (ulBytesRemain) {
memcpy(ajRemain, pSrcbuf+ul4BytesPerScan, ulBytesRemain);
write_dpPort(accel, *(unsigned int *)ajRemain);
}
odd=0;
*/
- for (i = 0; i < count; i++)
- {
+ for (i = 0; i < count; i++) {
color = *pcol++;
mask = *pmsk++;
data = 0;
else
opr = mask & color;
- for (j = 0; j < 8; j++)
- {
+ for (j = 0; j < 8; j++) {
- if (opr & (0x80 >> j))
- { /* use fg color,id = 2 */
+ if (opr & (0x80 >> j)) {
+ /* use fg color,id = 2 */
data |= 2 << (j*2);
} else {
/* use bg color,id = 1 */
pstart = cursor->vstart;
pbuffer = pstart;
- for (i = 0; i < count; i++)
- {
+ for (i = 0; i < count; i++) {
color = *pcol++;
mask = *pmsk++;
data = 0;
else
opr = mask & color;
- for (j = 0; j < 8; j++)
- {
+ for (j = 0; j < 8; j++) {
- if (opr & (0x80 >> j))
- { /* use fg color,id = 2 */
+ if (opr & (0x80 >> j)) {
+ /* use fg color,id = 2 */
data |= 2 << (j*2);
} else {
/* use bg color,id = 1 */
iowrite16(data, pbuffer);
/* assume pitch is 1,2,4,8,...*/
- if (!(i&(pitch-1)))
- {
+ if (!(i&(pitch-1))) {
/* need a return */
pstart += offset;
pbuffer = pstart;
projects / platform / kernel / linux-starfive.git / commitdiff