Merge tag 'x86_cpu_for_v5.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86 cpu updates from Borislav Petkov:

 - New AMD models support

 - Allow MONITOR/MWAIT to be used for C1 state entry on Hygon too

 - Use the special RAPL CPUID bit to detect the functionality on AMD and
   Hygon instead of doing family matching.

 - Add support for new Intel microcode deprecating TSX on some models
   and do not enable kernel workarounds for those CPUs when TSX
   transactions always abort, as a result of that microcode update.

* tag 'x86_cpu_for_v5.14_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/tsx: Clear CPUID bits when TSX always force aborts
  x86/events/intel: Do not deploy TSX force abort workaround when TSX is deprecated
  x86/msr: Define new bits in TSX_FORCE_ABORT MSR
  perf/x86/rapl: Use CPUID bit on AMD and Hygon parts
  x86/cstate: Allow ACPI C1 FFH MWAIT use on Hygon systems
  x86/amd_nb: Add AMD family 19h model 50h PCI ids
  x86/cpu: Fix core name for Sapphire Rapids

diff --combined arch/x86/events/intel/core.c
index e288922,062bf89..3a77f66
--- 1/arch/x86/events/intel/core.c
--- 2/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@@ -6015,7 -6015,13 +6015,13 @@@ __init int intel_pmu_init(void
                tsx_attr = hsw_tsx_events_attrs;
                intel_pmu_pebs_data_source_skl(pmem);
  
-               if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
+               /*
+                * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
+                * TSX force abort hooks are not required on these systems. Only deploy
+                * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
+                */
+               if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
+                  !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
                        x86_pmu.flags |= PMU_FL_TFA;
                        x86_pmu.get_event_constraints = tfa_get_event_constraints;
                        x86_pmu.enable_all = intel_tfa_pmu_enable_all;
@@@ -6253,7 -6259,7 +6259,7 @@@
         * Check all LBT MSR here.
         * Disable LBR access if any LBR MSRs can not be accessed.
         */
 -      if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
 +      if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
                x86_pmu.lbr_nr = 0;
        for (i = 0; i < x86_pmu.lbr_nr; i++) {
                if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&

diff --combined arch/x86/include/asm/msr-index.h
index 211ba33,2bc1600..a7c4134
--- 1/arch/x86/include/asm/msr-index.h
--- 2/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@@ -537,9 -537,9 +537,9 @@@
  /* K8 MSRs */
  #define MSR_K8_TOP_MEM1                       0xc001001a
  #define MSR_K8_TOP_MEM2                       0xc001001d
 -#define MSR_K8_SYSCFG                 0xc0010010
 -#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23
 -#define MSR_K8_SYSCFG_MEM_ENCRYPT     BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT)
 +#define MSR_AMD64_SYSCFG              0xc0010010
 +#define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT      23
 +#define MSR_AMD64_SYSCFG_MEM_ENCRYPT  BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT)
  #define MSR_K8_INT_PENDING_MSG                0xc0010055
  /* C1E active bits in int pending message */
  #define K8_INTP_C1E_ACTIVE_MASK               0x18000000
@@@ -772,6 -772,10 +772,10 @@@
  
  #define MSR_TFA_RTM_FORCE_ABORT_BIT   0
  #define MSR_TFA_RTM_FORCE_ABORT               BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
+ #define MSR_TFA_TSX_CPUID_CLEAR_BIT   1
+ #define MSR_TFA_TSX_CPUID_CLEAR               BIT_ULL(MSR_TFA_TSX_CPUID_CLEAR_BIT)
+ #define MSR_TFA_SDV_ENABLE_RTM_BIT    2
+ #define MSR_TFA_SDV_ENABLE_RTM                BIT_ULL(MSR_TFA_SDV_ENABLE_RTM_BIT)
  
  /* P4/Xeon+ specific */
  #define MSR_IA32_MCG_EAX              0x00000180

diff --combined arch/x86/kernel/cpu/amd.c
index c06ac56,da57b96..b7c0030
--- 1/arch/x86/kernel/cpu/amd.c
--- 2/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@@ -593,8 -593,8 +593,8 @@@ static void early_detect_mem_encrypt(st
         */
        if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
                /* Check if memory encryption is enabled */
 -              rdmsrl(MSR_K8_SYSCFG, msr);
 -              if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 +              rdmsrl(MSR_AMD64_SYSCFG, msr);
 +              if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
                        goto clear_all;
  
                /*
@@@ -646,6 -646,10 +646,10 @@@ static void early_init_amd(struct cpuin
        if (c->x86_power & BIT(12))
                set_cpu_cap(c, X86_FEATURE_ACC_POWER);
  
+       /* Bit 14 indicates the Runtime Average Power Limit interface. */
+       if (c->x86_power & BIT(14))
+               set_cpu_cap(c, X86_FEATURE_RAPL);
+ 
  #ifdef CONFIG_X86_64
        set_cpu_cap(c, X86_FEATURE_SYSCALL32);
  #else
@@@ -1165,19 -1169,3 +1169,19 @@@ void set_dr_addr_mask(unsigned long mas
                break;
        }
  }
 +
 +u32 amd_get_highest_perf(void)
 +{
 +      struct cpuinfo_x86 *c = &boot_cpu_data;
 +
 +      if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) ||
 +                             (c->x86_model >= 0x70 && c->x86_model < 0x80)))
 +              return 166;
 +
 +      if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) ||
 +                             (c->x86_model >= 0x40 && c->x86_model < 0x70)))
 +              return 166;
 +
 +      return 255;
 +}
 +EXPORT_SYMBOL_GPL(amd_get_highest_perf);

diff --combined include/linux/pci_ids.h
index 803ec44,5356ccf..4bac183
--- 1/include/linux/pci_ids.h
--- 2/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@@ -555,6 -555,7 +555,7 @@@
  #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 0x144b
  #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443
  #define PCI_DEVICE_ID_AMD_19H_DF_F3   0x1653
+ #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 0x166d
  #define PCI_DEVICE_ID_AMD_CNB17H_F3   0x1703
  #define PCI_DEVICE_ID_AMD_LANCE               0x2000
  #define PCI_DEVICE_ID_AMD_LANCE_HOME  0x2001
@@@ -631,8 -632,6 +632,8 @@@
  #define PCI_DEVICE_ID_DELL_RAC4               0x0012
  #define PCI_DEVICE_ID_DELL_PERC5      0x0015
  
 +#define PCI_SUBVENDOR_ID_DELL         0x1028
 +
  #define PCI_VENDOR_ID_MATROX          0x102B
  #define PCI_DEVICE_ID_MATROX_MGA_2    0x0518
  #define PCI_DEVICE_ID_MATROX_MIL      0x0519