[X86] Teach computeKnownBitsForTargetNode about MUL_IMM

This patch teaches computeKnownBitsForTargetNode about MUL_IMM.

MUL_IMM comes up in certain select of constants.  Specifically, it is
used to multiply the result of SETCC.  Computing the known zero bits
of MUL_IMM allows matchAddressRecursively us to convert some OR into
ADD, which eventually becomes a part of LEA.

This patch fixes:

https://github.com/llvm/llvm-project/issues/61365

Differential Revision: https://reviews.llvm.org/D146787

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2597403..b0d9c97 100644 (file)
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38282,6 +38282,13 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
   Known.resetAll();
   switch (Opc) {
   default: break;
+  case X86ISD::MUL_IMM: {
+    KnownBits Known2;
+    Known = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
+    Known2 = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+    Known = KnownBits::mul(Known, Known2);
+    break;
+  }
   case X86ISD::SETCC:
     Known.Zero.setBitsFrom(1);
     break;

diff --git a/llvm/test/CodeGen/X86/pr57402.ll b/llvm/test/CodeGen/X86/pr57402.ll
index 72f0aa3..5368bc2 100644 (file)
--- a/llvm/test/CodeGen/X86/pr57402.ll
+++ b/llvm/test/CodeGen/X86/pr57402.ll
@@ -6,8 +6,7 @@ define void @PR57402() {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    notl %eax
 ; CHECK-NEXT:    andl $-2, %eax
-; CHECK-NEXT:    leal (%rax,%rax,2), %ecx
-; CHECK-NEXT:    orl $1, %ecx
+; CHECK-NEXT:    leal 1(%rax,%rax,2), %ecx
 ; CHECK-NEXT:    movswq %cx, %rsi
 ; CHECK-NEXT:    xorl %edi, %edi
 ; CHECK-NEXT:    movq $-1, %rax

diff --git a/llvm/test/CodeGen/X86/select-constant-lea.ll b/llvm/test/CodeGen/X86/select-constant-lea.ll
index e847205..7e24a8c 100644 (file)
--- a/llvm/test/CodeGen/X86/select-constant-lea.ll
+++ b/llvm/test/CodeGen/X86/select-constant-lea.ll
@@ -8,8 +8,7 @@ define i32 @select_unsigned_lt_10_8_13j(i32 %0) {
 ; BASE-NEXT:    xorl %eax, %eax
 ; BASE-NEXT:    cmpl $10, %edi
 ; BASE-NEXT:    setae %al
-; BASE-NEXT:    leal (%rax,%rax,4), %eax
-; BASE-NEXT:    orl $8, %eax
+; BASE-NEXT:    leal 8(%rax,%rax,4), %eax
 ; BASE-NEXT:    retq
 ;
 ; SLOWLEA3-LABEL: select_unsigned_lt_10_8_13j:
@@ -18,7 +17,7 @@ define i32 @select_unsigned_lt_10_8_13j(i32 %0) {
 ; SLOWLEA3-NEXT:    cmpl $10, %edi
 ; SLOWLEA3-NEXT:    setae %al
 ; SLOWLEA3-NEXT:    leal (%rax,%rax,4), %eax
-; SLOWLEA3-NEXT:    orl $8, %eax
+; SLOWLEA3-NEXT:    addl $8, %eax
 ; SLOWLEA3-NEXT:    retq
   %2 = icmp ult i32 %0, 10
   %3 = select i1 %2, i32 8, i32 13