[Hexagon] Standardize "select" pseudo-instructions

- PS_pselect: general register pairs
- PS_vselect: vector registers (+ 128B version)
- PS_wselect: vector register pairs (+ 128B version)

llvm-svn: 278390

diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 8fc4d95..c86a7c6 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -52,7 +52,7 @@
 //         %vreg41<def> = S2_tstbit_i %vreg40<kill>, 0
 // spec->  %vreg11<def> = A2_addp %vreg6, %vreg10
 // pred->  S2_pstorerdf_io %vreg41, %vreg32, 16, %vreg11
-//         %vreg46<def> = MUX64_rr %vreg41, %vreg6, %vreg11
+//         %vreg46<def> = PS_pselect %vreg41, %vreg6, %vreg11
 //         %vreg13<def> = A2_addp %vreg7, %vreg46
 //         %vreg42<def> = C2_cmpeqi %vreg9, 10
 //         J2_jumpf %vreg42<kill>, <BB#3>, %PC<imp-def,dead>
@@ -761,15 +761,15 @@ void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB,
     if (RC == &IntRegsRegClass)
       Opc = C2_mux;
     else if (RC == &DoubleRegsRegClass)
-      Opc = MUX64_rr;
+      Opc = PS_pselect;
     else if (RC == &VectorRegsRegClass)
-      Opc = VSelectPseudo_V6;
+      Opc = PS_vselect;
     else if (RC == &VecDblRegsRegClass)
-      Opc = VSelectDblPseudo_V6;
+      Opc = PS_wselect;
     else if (RC == &VectorRegs128BRegClass)
-      Opc = VSelectPseudo_V6_128B;
+      Opc = PS_vselect_128B;
     else if (RC == &VecDblRegs128BRegClass)
-      Opc = VSelectDblPseudo_V6_128B;
+      Opc = PS_wselect_128B;
     else
       llvm_unreachable("unexpected register type");
     const MCInstrDesc &D = HII->get(Opc);

diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index bd5bb9c..259d68f 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -305,7 +305,7 @@ bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) {
     case Hexagon::C2_muxii:
     case Hexagon::C2_muxir:
     case Hexagon::C2_muxri:
-    case Hexagon::MUX64_rr:
+    case Hexagon::PS_pselect:
         return true;
       break;
   }

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index b1e2375..4e034a4 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -1233,7 +1233,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MRI.clearKillFlags(DstSubLo);
       return true;
     }
-    case Hexagon::MUX64_rr: {
+    case Hexagon::PS_pselect: {
       const MachineOperand &Op0 = MI.getOperand(0);
       const MachineOperand &Op1 = MI.getOperand(1);
       const MachineOperand &Op2 = MI.getOperand(2);
@@ -1257,7 +1257,8 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MBB.erase(MI);
       return true;
     }
-    case Hexagon::VSelectPseudo_V6: {
+    case Hexagon::PS_vselect:
+    case Hexagon::PS_vselect_128B: {
       const MachineOperand &Op0 = MI.getOperand(0);
       const MachineOperand &Op1 = MI.getOperand(1);
       const MachineOperand &Op2 = MI.getOperand(2);
@@ -1273,7 +1274,8 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MBB.erase(MI);
       return true;
     }
-    case Hexagon::VSelectDblPseudo_V6: {
+    case Hexagon::PS_wselect:
+    case Hexagon::PS_wselect_128B: {
       MachineOperand &Op0 = MI.getOperand(0);
       MachineOperand &Op1 = MI.getOperand(1);
       MachineOperand &Op2 = MI.getOperand(2);

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index 6378be3..6b855dc 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -729,9 +729,9 @@ def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
   }
 
 let isCodeGenOnly = 1, isPseudo = 1 in
-def MUX64_rr : ALU64_rr<(outs DoubleRegs:$Rd),
-               (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
-               ".error \"should not emit\" ", []>;
+def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd),
+      (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
+      ".error \"should not emit\" ", []>;
 
 
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td
index 8e984fb..83485f0 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td
@@ -1033,29 +1033,33 @@ class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
               IType type = TypeCVI_VA_DV>
   : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
 
-multiclass VSelect<RegisterClass RC, ValueType V> {
-  let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
-    def NAME : VSELInst<(outs RC:$dst),
-                        (ins PredRegs:$src1, RC:$src2, RC:$src3),
-                        ".error \"should not emit\" ",
-                        []>;
-  }
-
-  def : Pat <(V (selectcc (i32 IntRegs:$lhs), (i32 IntRegs:$rhs), (V RC:$tval),
-                          (V RC:$fval), SETEQ)),
-             (V (!cast<Instruction>(NAME) (i32 (C2_cmpeq (i32 IntRegs:$lhs),
-                                               (i32 IntRegs:$rhs))),
-                                          (V RC:$tval), (V RC:$fval)))>;
-}
-
-defm VSelectPseudo_V6 : VSelect<VectorRegs, v16i32>,
-                        Requires<[HasV60T,UseHVXSgl]>;
-defm VSelectDblPseudo_V6 : VSelect<VecDblRegs, v32i32>,
-                           Requires<[HasV60T,UseHVXSgl]>;
-defm VSelectPseudo_V6_128B : VSelect<VectorRegs128B, v32i32>,
-                             Requires<[HasV60T,UseHVXDbl]>;
-defm VSelectDblPseudo_V6_128B : VSelect<VecDblRegs128B, v64i32>,
-                                Requires<[HasV60T,UseHVXDbl]>;
+let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
+  def PS_vselect: VSELInst<(outs VectorRegs:$dst),
+        (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>,
+        Requires<[HasV60T,UseHVXSgl]>;
+  def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst),
+        (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
+        "", []>, Requires<[HasV60T,UseHVXDbl]>;
+  def PS_wselect: VSELInst<(outs VecDblRegs:$dst),
+        (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>,
+        Requires<[HasV60T,UseHVXSgl]>;
+  def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst),
+        (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3),
+        "", []>, Requires<[HasV60T,UseHVXDbl]>;
+}
+
+class VSelPat<ValueType VT, RegisterClass RC, InstHexagon MI>
+  : Pat<(selectcc I32:$lhs, I32:$rhs, (VT RC:$tval), (VT RC:$fval), SETEQ),
+        (MI (C2_cmpeq I32:$lhs, I32:$rhs), RC:$tval, RC:$fval)>;
+
+def: VSelPat<v16i32, VectorRegs, PS_vselect>,
+      Requires<[HasV60T,UseHVXSgl]>;
+def: VSelPat<v32i32, VecDblRegs, PS_wselect>,
+      Requires<[HasV60T,UseHVXSgl]>;
+def: VSelPat<v32i32, VectorRegs128B, PS_vselect_128B>,
+      Requires<[HasV60T,UseHVXDbl]>;
+def: VSelPat<v64i32, VecDblRegs128B, PS_wselect_128B>,
+      Requires<[HasV60T,UseHVXDbl]>;
 
 let hasNewValue = 1 in
 class T_vmpy <string asmString, RegisterClass RCout, RegisterClass RCin>