drm/amd/display: cache trace buffer size
authorJosip Pavic <josip.pavic@amd.com>
Fri, 12 May 2023 13:56:05 +0000 (09:56 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Jun 2023 14:44:22 +0000 (10:44 -0400)
[Why & How]
Cache the trace buffer size retrieved from DMUB FW in the driver

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Josip Pavic <josip.pavic@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

index 7c9a2b3..e210cb0 100644 (file)
@@ -428,6 +428,7 @@ struct dmub_srv {
        enum dmub_asic asic;
        void *user_ctx;
        uint32_t fw_version;
+       uint32_t trace_buffer_size;
        bool is_virtual;
        struct dmub_fb scratch_mem_fb;
        volatile const struct dmub_fw_state *fw_state;
index 9e9a6a4..8b9af18 100644 (file)
@@ -427,6 +427,8 @@ dmub_srv_calc_region_info(struct dmub_srv *dmub,
                        dmub->fw_version = fw_info->fw_version;
        }
 
+       dmub->trace_buffer_size = trace_buffer_size;
+
        trace_buff->base = dmub_align(mail->top, 256);
        trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64);