dmaengine: xilinx_dma: Reset DMA channel in dma_terminate_all

Reset DMA channel after stop to ensure that pending transfers and FIFOs
in the datapath are flushed or completed. It also cleanup the terminate
path and removes stop for the cyclic mode as after the reset stop is not
required. This fixes intermittent data verification failure when xilinx
dma test the client is stressed and loaded/unloaded multiple times.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Link: https://lore.kernel.org/r/1580283909-32678-1-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index a9c5d5c..6f1539c 100644 (file)
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -2404,16 +2404,17 @@ static int xilinx_dma_terminate_all(struct dma_chan *dchan)
        u32 reg;
        int err;
 
-       if (chan->cyclic)
-               xilinx_dma_chan_reset(chan);
-
-       err = chan->stop_transfer(chan);
-       if (err) {
-               dev_err(chan->dev, "Cannot stop channel %p: %x\n",
-                       chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR));
-               chan->err = true;
+       if (!chan->cyclic) {
+               err = chan->stop_transfer(chan);
+               if (err) {
+                       dev_err(chan->dev, "Cannot stop channel %p: %x\n",
+                               chan, dma_ctrl_read(chan,
+                               XILINX_DMA_REG_DMASR));
+                       chan->err = true;
+               }
        }
 
+       xilinx_dma_chan_reset(chan);
        /* Remove and free all of the descriptors in the lists */
        xilinx_dma_free_descriptors(chan);
        chan->idle = true;