COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o
-COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o
+COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
{
phys_size_t dram_size = fsl_ddr_sdram();
+#ifdef CONFIG_MPC85xx
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
dram_size *= 0x100000;
+#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize and enable DDR ECC */
void board_add_ram_info(int use_default)
{
#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_MPC85xx)
volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#elif defined(CONFIG_MPC86xx)
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+#endif
#endif
puts(" (");