{
struct radeon_info *info = &device->physical_device->rad_info;
enum amd_gfx_level gfx_level = info->gfx_level;
+ enum radeon_family family = info->family;
uint8_t wave_size = shader->info.wave_size;
struct ac_shader_config *conf = &shader->config;
unsigned max_simd_waves;
if (conf->num_vgprs) {
unsigned physical_vgprs = info->num_physical_wave64_vgprs_per_simd * (64 / wave_size);
unsigned vgprs = align(conf->num_vgprs, wave_size == 32 ? 8 : 4);
- if (gfx_level == GFX10_3)
+ if (family == CHIP_GFX1100 || family == CHIP_GFX1101)
+ vgprs = util_align_npot(vgprs, wave_size == 32 ? 24 : 12);
+ else if (gfx_level == GFX10_3)
vgprs = align(vgprs, wave_size == 32 ? 16 : 8);
max_simd_waves = MIN2(max_simd_waves, physical_vgprs / vgprs);
}
else
info->num_physical_sgprs_per_simd = 512;
- info->num_physical_wave64_vgprs_per_simd = info->gfx_level >= GFX10 ? 512 : 256;
+ if (info->family == CHIP_GFX1100 || info->family == CHIP_GFX1101)
+ info->num_physical_wave64_vgprs_per_simd = 768;
+ else if (info->gfx_level >= GFX10)
+ info->num_physical_wave64_vgprs_per_simd = 512;
+ else
+ info->num_physical_wave64_vgprs_per_simd = 256;
info->num_simd_per_compute_unit = info->gfx_level >= GFX10 ? 2 : 4;
info->lds_size_per_workgroup = info->gfx_level >= GFX10 ? 128 * 1024 : 64 * 1024;
info->lds_encode_granularity = info->gfx_level >= GFX7 ? 128 * 4 : 64 * 4;