{
struct msm_clk_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct msm_pinctrl_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ priv->base = dev_read_addr(dev);
priv->data = (struct msm_pinctrl_data *)dev->driver_data;
return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
struct dwc_ahci_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- priv->base = map_physmem(devfdt_get_addr(dev), sizeof(void *),
+ priv->base = map_physmem(dev_read_addr(dev), sizeof(void *),
MAP_NOCACHE);
addr = devfdt_get_addr_index(dev, 1);
struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->regs = (void __iomem *)addr;
socfpga_a10_handoff_workaround(dev);
if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
- plat->regs = devfdt_get_addr(dev);
+ plat->regs = dev_read_addr(dev);
} else {
pdev = dev_get_parent(dev);
if (!pdev)
fdt_addr_t base;
int ret;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
if (!priv)
return -EINVAL;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
struct uniphier_clk_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev->parent);
+ addr = dev_read_addr(dev->parent);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct ti_edma3_priv *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ priv->base = dev_read_addr(dev);
return 0;
}
{
struct altera_pio_platdata *plat = dev_get_platdata(dev);
- plat->regs = map_physmem(devfdt_get_addr(dev),
+ plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_pio_regs),
MAP_NOCACHE);
plat->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
clk_free(&clk);
- addr_base = devfdt_get_addr(dev);
+ addr_base = dev_read_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
struct bcm2835_gpio_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct davinci_gpio_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
uc_priv->bank_name = dev->name;
dev = dev_get_parent(dev);
- addr_base = devfdt_get_addr(dev);
+ addr_base = dev_read_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ priv->base = dev_read_addr(dev);
return priv->base == FDT_ADDR_T_NONE ? -EINVAL : 0;
}
fdt_addr_t addr;
struct mxc_gpio_plat *plat = dev_get_platdata(dev);
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
int node = dev_of_offset(dev);
int ret;
- plat->bank = devfdt_get_addr(dev);
+ plat->bank = dev_read_addr(dev);
if (plat->bank == FDT_ADDR_T_NONE) {
printf("%s: No 'reg' property defined!\n", __func__);
return -EINVAL;
if (plat)
return 0;
- base_addr = devfdt_get_addr(dev);
+ base_addr = dev_read_addr(dev);
if (base_addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct omap_gpio_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct pm8916_gpio_bank *priv = dev_get_priv(dev);
int reg;
- priv->pid = devfdt_get_addr(dev);
+ priv->pid = dev_read_addr(dev);
if (priv->pid == FDT_ADDR_T_NONE)
return log_msg_ret("bad address", -EINVAL);
dev_set_of_offset(dev, node);
- reg = devfdt_get_addr(dev);
+ reg = dev_read_addr(dev);
if (reg != FDT_ADDR_T_NONE)
bank = (struct s5p_gpio_bank *)((ulong)base + reg);
struct sifive_gpio_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct vybrid_gpio_platdata *plat = dev_get_platdata(dev);
fdt_addr_t base_addr;
- base_addr = devfdt_get_addr(dev);
+ base_addr = dev_read_addr(dev);
if (base_addr == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t addr;
struct uniphier_fi2c_priv *priv = dev_get_priv(dev);
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t addr;
struct uniphier_i2c_priv *priv = dev_get_priv(dev);
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
i2c_bus->driver_data = dev_get_driver_data(bus);
- addr = devfdt_get_addr(bus);
+ addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
int node = dev_of_offset(bus);
const void *blob = gd->fdt_blob;
- bus_prvdata->base = map_physmem(devfdt_get_addr(bus),
+ bus_prvdata->base = map_physmem(dev_read_addr(bus),
sizeof(void *),
MAP_NOCACHE);
i2c_bus->driver_data = dev_get_driver_data(bus);
- addr = devfdt_get_addr(bus);
+ addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct omap_i2c_platdata *plat = dev_get_platdata(bus);
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
plat->speed = dev_read_u32_default(bus, "clock-frequency",
I2C_SPEED_STANDARD_RATE);
plat->ip_rev = dev_get_driver_data(bus);
debug("%s(dev=%p)\n", __func__, dev);
- thsp->regs = devfdt_get_addr(dev);
+ thsp->regs = dev_read_addr(dev);
if (thsp->regs == FDT_ADDR_T_NONE)
return -ENODEV;
{
struct altera_sysid_platdata *plat = dev_get_platdata(dev);
- plat->regs = map_physmem(devfdt_get_addr(dev),
+ plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_sysid_regs),
MAP_NOCACHE);
debug("%s(dev=%p) (plat=%p)\n", __func__, dev, plat);
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct microchip_flexcom_platdata *plat = dev_get_platdata(dev);
int ret;
- plat->regs = map_physmem(devfdt_get_addr(dev),
+ plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct microchip_flexcom_regs),
MAP_NOCACHE);
int ret;
int clock_id = (int)dev_get_driver_data(dev);
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
upriv->mmc = &plat->mmc;
plat->cfg.name = dev->name;
- host->phys_addr = devfdt_get_addr(dev);
+ host->phys_addr = dev_read_addr(dev);
if (host->phys_addr == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t base;
int ret;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
struct mmc_config *cfg;
int ret;
- priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
+ priv->regs = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
cfg = &plat->cfg;
cfg->name = "MSC";
struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
int node = dev_of_offset(dev);
int ret;
- plat->base_addr = map_physmem(devfdt_get_addr(dev),
+ plat->base_addr = map_physmem(dev_read_addr(dev),
sizeof(struct hsmmc *),
MAP_NOCACHE);
plat->controller_flags |= of_data->controller_flags;
#ifdef CONFIG_OMAP54XX
- fixups = platform_fixups_mmc(devfdt_get_addr(dev));
+ fixups = platform_fixups_mmc(dev_read_addr(dev));
if (fixups) {
plat->hw_rev = fixups->hw_rev;
cfg->host_caps &= ~fixups->unsupported_caps;
fdt_addr_t base;
int ret;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t base;
int ret;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t base;
int ret;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t base;
int ret;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
ulong mclk;
int ret;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
const char *phy_mode;
int ret;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
/* Decoding of convoluted PHY wiring on Atheros MIPS. */
eqos->dev = dev;
eqos->config = (void *)dev_get_driver_data(dev);
- eqos->regs = devfdt_get_addr(dev);
+ eqos->regs = dev_read_addr(dev);
if (eqos->regs == FDT_ADDR_T_NONE) {
- pr_err("devfdt_get_addr() failed");
+ pr_err("dev_read_addr() failed");
return -ENODEV;
}
eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
fdt_addr_t addr;
- pdata->eth_pdata.iobase = devfdt_get_addr(dev);
+ pdata->eth_pdata.iobase = dev_read_addr(dev);
addr = devfdt_get_addr_index(dev, 1);
if (addr != FDT_ADDR_T_NONE)
pdata->packet_base = addr;
struct fec_priv *priv = dev_get_priv(dev);
const char *phy_mode;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
priv->eth = (struct ethernet_regs *)pdata->iobase;
pdata->phy_interface = -1;
struct eth_pdata *pdata = dev_get_platdata(dev);
const u32 *val;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
/* Default to 10Mbit/s */
pdata->max_speed = 10;
struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
phy_mode = dev_read_string(dev, "phy-mode");
if (phy_mode)
struct ftmac100_data *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
const char *mac;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
priv->iobase = pdata->iobase;
mac = dtbmacaddr(0);
if (mac)
struct ks_net *ks = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
ks->iobase = pdata->iobase;
return 0;
struct eth_pdata *pdata = dev_get_platdata(dev);
const u32 *val;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
/* Default to 10Mbit/s */
pdata->max_speed = 10;
priv->soc = dev_get_driver_data(dev);
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
/* get corresponding ethsys phandle */
ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0,
int pnode;
unsigned long addr;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
pnode = fdt_node_offset_by_compatible(blob, node,
struct eth_pdata *pdata = dev_get_platdata(dev);
const char *phy_mode;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
/* Get phy-mode / phy_interface from DT */
pdata->phy_interface = -1;
const fdt32_t *cell;
int ret = 0;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
const fdt32_t *cell;
int ret = 0;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
struct smc911x_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
priv->iobase = pdata->iobase;
return 0;
if (!priv->data)
return -EINVAL;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = -1;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
#endif
int ret;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
if (pdata->iobase == FDT_ADDR_T_NONE) {
debug("%s: Cannot find MAC base address\n", __func__);
return -EINVAL;
{
struct eth_pdata *pdata = dev_get_platdata(dev);
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
return 0;
}
ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
return 0;
}
int offset = 0;
const char *phy_mode;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
priv->iobase = (struct axi_regs *)pdata->iobase;
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
struct xemaclite *emaclite = dev_get_priv(dev);
int offset = 0;
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
0x10000);
struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct qca953x_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
if (!priv)
return -EINVAL;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t addr_base;
dev = dev_get_parent(dev);
- addr_base = devfdt_get_addr(dev);
+ addr_base = dev_read_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t addr_base;
ofnode node;
- addr_base = devfdt_get_addr(dev);
+ addr_base = dev_read_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -EINVAL;
enum sh_pfc_model model = dev_get_driver_data(dev);
fdt_addr_t base;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
struct uniphier_pinctrl_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev->parent);
+ addr = dev_read_addr(dev->parent);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct uniphier_reset_priv *priv = dev_get_priv(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev->parent);
+ addr = dev_read_addr(dev->parent);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct mvrtc_pdata *pdata = dev_get_platdata(dev);
- pdata->iobase = devfdt_get_addr(dev);
+ pdata->iobase = dev_read_addr(dev);
return 0;
}
{
struct altera_jtaguart_platdata *plat = dev_get_platdata(dev);
- plat->regs = map_physmem(devfdt_get_addr(dev),
+ plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_jtaguart_regs),
MAP_NOCACHE);
{
struct altera_uart_platdata *plat = dev_get_platdata(dev);
- plat->regs = map_physmem(devfdt_get_addr(dev),
+ plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_uart_regs),
MAP_NOCACHE);
plat->uartclk = dev_read_u32_default(dev, "clock-frequency", 0);
#if CONFIG_IS_ENABLED(OF_CONTROL)
fdt_addr_t addr_base;
- addr_base = devfdt_get_addr(dev);
+ addr_base = dev_read_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -ENODEV;
fdt_addr_t addr;
u32 val;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
* since we need the soc simple-bus to be probed so that the 'ranges'
* property is used.
*/
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
int node = dev_of_offset(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr_base;
- addr_base = devfdt_get_addr(dev);
+ addr_base = dev_read_addr(dev);
if (addr_base == FDT_ADDR_T_NONE)
return -ENODEV;
struct meson_serial_platdata *plat = dev->platdata;
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct msm_serial_data *priv = dev_get_priv(dev);
- priv->base = devfdt_get_addr(dev);
+ priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
struct mxc_serial_platdata *plat = dev->platdata;
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t addr;
int ret;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
struct s5p_serial_platdata *plat = dev->platdata;
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t addr;
int ret;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (!addr)
return -EINVAL;
unsigned long val;
fdt_addr_t base;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
- plat->base = devfdt_get_addr(dev);
+ plat->base = dev_read_addr(dev);
if (plat->base == FDT_ADDR_T_NONE)
return -EINVAL;
fdt_addr_t base;
u32 tmp;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct altera_spi_platdata *plat = dev_get_platdata(bus);
- plat->regs = map_physmem(devfdt_get_addr(bus),
+ plat->regs = map_physmem(dev_read_addr(bus),
sizeof(struct altera_spi_regs),
MAP_NOCACHE);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
- ns->regs = map_physmem(devfdt_get_addr(bus),
+ ns->regs = map_physmem(dev_read_addr(bus),
sizeof(struct atcspi200_spi_regs),
MAP_NOCACHE);
if (!ns->regs) {
struct ath79_spi_priv *priv = dev_get_priv(bus);
fdt_addr_t addr;
- addr = devfdt_get_addr(bus);
+ addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
int node = dev_of_offset(bus);
int *ctar, len;
- addr = devfdt_get_addr(bus);
+ addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE)
return -ENOMEM;
struct davinci_spi_platdata *plat = bus->platdata;
fdt_addr_t addr;
- addr = devfdt_get_addr(bus);
+ addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->num_chipselect =
fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
- addr = devfdt_get_addr(bus);
+ addr = dev_read_addr(bus);
if (addr == FDT_ADDR_T_NONE) {
debug("DSPI: Can't get base address or size\n");
return -ENOMEM;
}
}
- mxcs->base = devfdt_get_addr(bus);
+ mxcs->base = dev_read_addr(bus);
if (mxcs->base == FDT_ADDR_T_NONE)
return -ENODEV;
struct omap2_mcspi_platform_config* data =
(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
- priv->regs = (struct mcspi *)(devfdt_get_addr(dev) + data->regs_offset);
+ priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
else
struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
"spi-max-frequency",
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
const void *blob = gd->fdt_blob;
int node = dev_of_offset(bus);
- plat->base = devfdt_get_addr(bus);
+ plat->base = dev_read_addr(bus);
plat->periph_id = clock_decode_periph_id(bus);
if (plat->periph_id == PERIPH_ID_NONE) {
fdt_addr_t mmap_size;
priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
- priv->base = map_physmem(devfdt_get_addr(bus),
+ priv->base = map_physmem(dev_read_addr(bus),
sizeof(struct ti_qspi_regs), MAP_NOCACHE);
mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
debug("%s\n", __func__);
- plat->regs = (struct zynqmp_qspi_regs *)(devfdt_get_addr(bus) +
+ plat->regs = (struct zynqmp_qspi_regs *)(dev_read_addr(bus) +
GQSPI_REG_OFFSET);
plat->dma_regs = (struct zynqmp_qspi_dma_regs *)
- (devfdt_get_addr(bus) + GQSPI_DMA_REG_OFFSET);
+ (dev_read_addr(bus) + GQSPI_DMA_REG_OFFSET);
return 0;
}
bool is_v1;
int i;
- priv->arb_chnl = devfdt_get_addr(dev);
+ priv->arb_chnl = dev_read_addr(dev);
priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
dev_of_offset(parent), node, "reg", 1, NULL, false);
priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
static int atftme_timer_ofdata_to_platdata(struct udevice *dev)
{
struct atftmr_timer_platdata *plat = dev_get_platdata(dev);
- plat->regs = map_physmem(devfdt_get_addr(dev),
+ plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct atftmr_timer_regs),
MAP_NOCACHE);
return 0;
{
struct altera_timer_platdata *plat = dev_get_platdata(dev);
- plat->regs = map_physmem(devfdt_get_addr(dev),
+ plat->regs = map_physmem(dev_read_addr(dev),
sizeof(struct altera_timer_regs),
MAP_NOCACHE);
static int atcpit_timer_ofdata_to_platdata(struct udevice *dev)
{
struct atcpit_timer_platdata *plat = dev_get_platdata(dev);
- plat->regs = map_physmem(devfdt_get_addr(dev) , 0x100 , MAP_NOCACHE);
+ plat->regs = map_physmem(dev_read_addr(dev), 0x100 , MAP_NOCACHE);
return 0;
}
{
struct omap_timer_priv *priv = dev_get_priv(dev);
- priv->regs = map_physmem(devfdt_get_addr(dev),
+ priv->regs = map_physmem(dev_read_addr(dev),
sizeof(struct omap_gptimer_regs), MAP_NOCACHE);
return 0;
int (*init)(void __iomem *regs);
int ret;
- base = devfdt_get_addr(dev);
+ base = dev_read_addr(dev);
if (base == FDT_ADDR_T_NONE)
return -EINVAL;
/*
* Get the base address for EHCI controller from the device node
*/
- hcd_base = devfdt_get_addr(dev);
+ hcd_base = dev_read_addr(dev);
if (hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the EHCI register base address\n");
return -ENXIO;
/*
* Get the base address for XHCI controller from the device node
*/
- plat->hcd_base = devfdt_get_addr(dev);
+ plat->hcd_base = dev_read_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the XHCI register base address\n");
return -ENXIO;
/*
* Get the base address for EHCI controller from the device node
*/
- priv->hcd_base = devfdt_get_addr(dev);
+ priv->hcd_base = dev_read_addr(dev);
if (priv->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the EHCI register base address\n");
return -ENXIO;
/*
* Get the base address for EHCI controller from the device node
*/
- priv->hcd_base = devfdt_get_addr(dev);
+ priv->hcd_base = dev_read_addr(dev);
if (priv->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the EHCI register base address\n");
return -ENXIO;
/*
* Get the base address for XHCI controller from the device node
*/
- plat->hcd_base = devfdt_get_addr(dev);
+ plat->hcd_base = dev_read_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the XHCI register base address\n");
return -ENXIO;
/*
* Get the base address for XHCI controller from the device node
*/
- priv->hcd_base = devfdt_get_addr(dev);
+ priv->hcd_base = dev_read_addr(dev);
if (priv->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the XHCI register base address\n");
return -ENXIO;
/*
* Get the base address for XHCI controller from the device node
*/
- plat->hcd_base = devfdt_get_addr(dev);
+ plat->hcd_base = dev_read_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the XHCI register base address\n");
return -ENXIO;
{
struct rcar_xhci_platdata *plat = dev_get_platdata(dev);
- plat->hcd_base = devfdt_get_addr(dev);
+ plat->hcd_base = dev_read_addr(dev);
if (plat->hcd_base == FDT_ADDR_T_NONE) {
debug("Can't get the XHCI register base address\n");
return -ENXIO;
unsigned int node = dev_of_offset(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE) {
debug("Can't get the DP base address\n");
return -EINVAL;
const void *blob = gd->fdt_blob;
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE) {
debug("Can't get the FIMD base address\n");
return -EINVAL;
struct mxc_w1_pdata *pdata = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = devfdt_get_addr(dev);
+ addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
debug("IWDG init\n");
- priv->base = devfdt_get_addr(dev);
+ priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;