{
struct zink_context *ctx = zink_context(pctx);
+ bool prev_zsread = ctx->dsa_state ? ctx->dsa_state->hw_state.depth_test || ctx->dsa_state->hw_state.stencil_test : false;
bool prev_zswrite = ctx->dsa_state ? ctx->dsa_state->hw_state.depth_write || ctx->dsa_state->hw_state.stencil_test : false;
zink_flush_dgc_if_enabled(ctx);
ctx->dsa_state = cso;
state->dirty |= !zink_screen(pctx->screen)->info.have_EXT_extended_dynamic_state;
ctx->dsa_state_changed = true;
}
- if (!ctx->track_renderpasses && !ctx->blitting)
- zink_parse_tc_info(ctx);
}
if (!ctx->track_renderpasses && !ctx->blitting) {
bool zs_write = ctx->dsa_state ? ctx->dsa_state->hw_state.depth_write || ctx->dsa_state->hw_state.stencil_test : false;
- if (prev_zswrite != zs_write) {
- /* flag renderpass for re-check on next draw */
- ctx->rp_layout_changed = true;
- }
+ bool zs_read = ctx->dsa_state ? ctx->dsa_state->hw_state.depth_test || ctx->dsa_state->hw_state.stencil_test : false;
+ if (prev_zswrite != zs_write || prev_zsread != zs_read)
+ zink_parse_tc_info(ctx);
}
}